1*a944c127SJinzhou Su /* 2*a944c127SJinzhou Su * Copyright 2019 Advanced Micro Devices, Inc. 3*a944c127SJinzhou Su * 4*a944c127SJinzhou Su * Permission is hereby granted, free of charge, to any person obtaining a 5*a944c127SJinzhou Su * copy of this software and associated documentation files (the "Software"), 6*a944c127SJinzhou Su * to deal in the Software without restriction, including without limitation 7*a944c127SJinzhou Su * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*a944c127SJinzhou Su * and/or sell copies of the Software, and to permit persons to whom the 9*a944c127SJinzhou Su * Software is furnished to do so, subject to the following conditions: 10*a944c127SJinzhou Su * 11*a944c127SJinzhou Su * The above copyright notice and this permission notice shall be included in 12*a944c127SJinzhou Su * all copies or substantial portions of the Software. 13*a944c127SJinzhou Su * 14*a944c127SJinzhou Su * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*a944c127SJinzhou Su * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*a944c127SJinzhou Su * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*a944c127SJinzhou Su * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*a944c127SJinzhou Su * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*a944c127SJinzhou Su * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*a944c127SJinzhou Su * OTHER DEALINGS IN THE SOFTWARE. 21*a944c127SJinzhou Su * 22*a944c127SJinzhou Su */ 23*a944c127SJinzhou Su 24*a944c127SJinzhou Su #ifndef _TA_SECUREDISPLAY_IF_H 25*a944c127SJinzhou Su #define _TA_SECUREDISPLAY_IF_H 26*a944c127SJinzhou Su 27*a944c127SJinzhou Su /** Secure Display related enumerations */ 28*a944c127SJinzhou Su /**********************************************************/ 29*a944c127SJinzhou Su 30*a944c127SJinzhou Su /** @enum ta_securedisplay_command 31*a944c127SJinzhou Su * Secure Display Command ID 32*a944c127SJinzhou Su */ 33*a944c127SJinzhou Su enum ta_securedisplay_command { 34*a944c127SJinzhou Su /* Query whether TA is responding used only for validation purpose */ 35*a944c127SJinzhou Su TA_SECUREDISPLAY_COMMAND__QUERY_TA = 1, 36*a944c127SJinzhou Su /* Send region of Interest and CRC value to I2C */ 37*a944c127SJinzhou Su TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC = 2, 38*a944c127SJinzhou Su /* Maximum Command ID */ 39*a944c127SJinzhou Su TA_SECUREDISPLAY_COMMAND__MAX_ID = 0x7FFFFFFF, 40*a944c127SJinzhou Su }; 41*a944c127SJinzhou Su 42*a944c127SJinzhou Su /** @enum ta_securedisplay_status 43*a944c127SJinzhou Su * Secure Display status returns in shared buffer status 44*a944c127SJinzhou Su */ 45*a944c127SJinzhou Su enum ta_securedisplay_status { 46*a944c127SJinzhou Su TA_SECUREDISPLAY_STATUS__SUCCESS = 0x00, /* Success */ 47*a944c127SJinzhou Su TA_SECUREDISPLAY_STATUS__GENERIC_FAILURE = 0x01, /* Generic Failure */ 48*a944c127SJinzhou Su TA_SECUREDISPLAY_STATUS__INVALID_PARAMETER = 0x02, /* Invalid Parameter */ 49*a944c127SJinzhou Su TA_SECUREDISPLAY_STATUS__NULL_POINTER = 0x03, /* Null Pointer*/ 50*a944c127SJinzhou Su TA_SECUREDISPLAY_STATUS__I2C_WRITE_ERROR = 0x04, /* Fail to Write to I2C */ 51*a944c127SJinzhou Su TA_SECUREDISPLAY_STATUS__READ_DIO_SCRATCH_ERROR = 0x05, /*Fail Read DIO Scratch Register*/ 52*a944c127SJinzhou Su TA_SECUREDISPLAY_STATUS__READ_CRC_ERROR = 0x06, /* Fail to Read CRC*/ 53*a944c127SJinzhou Su 54*a944c127SJinzhou Su TA_SECUREDISPLAY_STATUS__MAX = 0x7FFFFFFF,/* Maximum Value for status*/ 55*a944c127SJinzhou Su }; 56*a944c127SJinzhou Su 57*a944c127SJinzhou Su /** @enum ta_securedisplay_max_phy 58*a944c127SJinzhou Su * Physical ID number to use for reading corresponding DIO Scratch register for ROI 59*a944c127SJinzhou Su */ 60*a944c127SJinzhou Su enum ta_securedisplay_max_phy { 61*a944c127SJinzhou Su TA_SECUREDISPLAY_PHY0 = 0, 62*a944c127SJinzhou Su TA_SECUREDISPLAY_PHY1 = 1, 63*a944c127SJinzhou Su TA_SECUREDISPLAY_PHY2 = 2, 64*a944c127SJinzhou Su TA_SECUREDISPLAY_PHY3 = 3, 65*a944c127SJinzhou Su TA_SECUREDISPLAY_MAX_PHY = 4, 66*a944c127SJinzhou Su }; 67*a944c127SJinzhou Su 68*a944c127SJinzhou Su /** @enum ta_securedisplay_ta_query_cmd_ret 69*a944c127SJinzhou Su * A predefined specific reteurn value which is 0xAB only used to validate 70*a944c127SJinzhou Su * communication to Secure Display TA is functional. 71*a944c127SJinzhou Su * This value is used to validate whether TA is responding successfully 72*a944c127SJinzhou Su */ 73*a944c127SJinzhou Su enum ta_securedisplay_ta_query_cmd_ret { 74*a944c127SJinzhou Su /* This is a value to validate if TA is loaded successfully */ 75*a944c127SJinzhou Su TA_SECUREDISPLAY_QUERY_CMD_RET = 0xAB, 76*a944c127SJinzhou Su }; 77*a944c127SJinzhou Su 78*a944c127SJinzhou Su /** @enum ta_securedisplay_buffer_size 79*a944c127SJinzhou Su * I2C Buffer size which contains 8 bytes of ROI (X start, X end, Y start, Y end) 80*a944c127SJinzhou Su * and 6 bytes of CRC( R,G,B) and 1 byte for physical ID 81*a944c127SJinzhou Su */ 82*a944c127SJinzhou Su enum ta_securedisplay_buffer_size { 83*a944c127SJinzhou Su /* 15 bytes = 8 byte (ROI) + 6 byte(CRC) + 1 byte(phy_id) */ 84*a944c127SJinzhou Su TA_SECUREDISPLAY_I2C_BUFFER_SIZE = 15, 85*a944c127SJinzhou Su }; 86*a944c127SJinzhou Su 87*a944c127SJinzhou Su /** Input/output structures for Secure Display commands */ 88*a944c127SJinzhou Su /**********************************************************/ 89*a944c127SJinzhou Su /** 90*a944c127SJinzhou Su * Input structures 91*a944c127SJinzhou Su */ 92*a944c127SJinzhou Su 93*a944c127SJinzhou Su /** @struct ta_securedisplay_send_roi_crc_input 94*a944c127SJinzhou Su * Physical ID to determine which DIO scratch register should be used to get ROI 95*a944c127SJinzhou Su */ 96*a944c127SJinzhou Su struct ta_securedisplay_send_roi_crc_input { 97*a944c127SJinzhou Su uint32_t phy_id; /* Physical ID */ 98*a944c127SJinzhou Su }; 99*a944c127SJinzhou Su 100*a944c127SJinzhou Su /** @union ta_securedisplay_cmd_input 101*a944c127SJinzhou Su * Input buffer 102*a944c127SJinzhou Su */ 103*a944c127SJinzhou Su union ta_securedisplay_cmd_input { 104*a944c127SJinzhou Su /* send ROI and CRC input buffer format */ 105*a944c127SJinzhou Su struct ta_securedisplay_send_roi_crc_input send_roi_crc; 106*a944c127SJinzhou Su uint32_t reserved[4]; 107*a944c127SJinzhou Su }; 108*a944c127SJinzhou Su 109*a944c127SJinzhou Su /** 110*a944c127SJinzhou Su * Output structures 111*a944c127SJinzhou Su */ 112*a944c127SJinzhou Su 113*a944c127SJinzhou Su /** @struct ta_securedisplay_query_ta_output 114*a944c127SJinzhou Su * Output buffer format for query TA whether TA is responding used only for validation purpose 115*a944c127SJinzhou Su */ 116*a944c127SJinzhou Su struct ta_securedisplay_query_ta_output { 117*a944c127SJinzhou Su /* return value from TA when it is queried for validation purpose only */ 118*a944c127SJinzhou Su uint32_t query_cmd_ret; 119*a944c127SJinzhou Su }; 120*a944c127SJinzhou Su 121*a944c127SJinzhou Su /** @struct ta_securedisplay_send_roi_crc_output 122*a944c127SJinzhou Su * Output buffer format for send ROI CRC command which will pass I2c buffer created inside TA 123*a944c127SJinzhou Su * and used to write to I2C used only for validation purpose 124*a944c127SJinzhou Su */ 125*a944c127SJinzhou Su struct ta_securedisplay_send_roi_crc_output { 126*a944c127SJinzhou Su uint8_t i2c_buf[TA_SECUREDISPLAY_I2C_BUFFER_SIZE]; /* I2C buffer */ 127*a944c127SJinzhou Su uint8_t reserved; 128*a944c127SJinzhou Su }; 129*a944c127SJinzhou Su 130*a944c127SJinzhou Su /** @union ta_securedisplay_cmd_output 131*a944c127SJinzhou Su * Output buffer 132*a944c127SJinzhou Su */ 133*a944c127SJinzhou Su union ta_securedisplay_cmd_output { 134*a944c127SJinzhou Su /* Query TA output buffer format used only for validation purpose*/ 135*a944c127SJinzhou Su struct ta_securedisplay_query_ta_output query_ta; 136*a944c127SJinzhou Su /* Send ROI CRC output buffer format used only for validation purpose */ 137*a944c127SJinzhou Su struct ta_securedisplay_send_roi_crc_output send_roi_crc; 138*a944c127SJinzhou Su uint32_t reserved[4]; 139*a944c127SJinzhou Su }; 140*a944c127SJinzhou Su 141*a944c127SJinzhou Su /** @struct securedisplay_cmd 142*a944c127SJinzhou Su * Secure Display Command which is shared buffer memory 143*a944c127SJinzhou Su */ 144*a944c127SJinzhou Su struct securedisplay_cmd { 145*a944c127SJinzhou Su uint32_t cmd_id; /* +0 Bytes Command ID */ 146*a944c127SJinzhou Su enum ta_securedisplay_status status; /* +4 Bytes Status of Secure Display TA */ 147*a944c127SJinzhou Su uint32_t reserved[2]; /* +8 Bytes Reserved */ 148*a944c127SJinzhou Su union ta_securedisplay_cmd_input securedisplay_in_message; /* +16 Bytes Input Buffer */ 149*a944c127SJinzhou Su union ta_securedisplay_cmd_output securedisplay_out_message;/* +32 Bytes Output Buffer */ 150*a944c127SJinzhou Su /**@note Total 48 Bytes */ 151*a944c127SJinzhou Su }; 152*a944c127SJinzhou Su 153*a944c127SJinzhou Su #endif //_TA_SECUREDISPLAY_IF_H 154*a944c127SJinzhou Su 155