1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef _TA_RAS_IF_H
25 #define _TA_RAS_IF_H
26 
27 #define RAS_TA_HOST_IF_VER	0
28 
29 /* Responses have bit 31 set */
30 #define RSP_ID_MASK (1U << 31)
31 #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK)
32 
33 /* RAS related enumerations */
34 /**********************************************************/
35 enum ras_command {
36 	TA_RAS_COMMAND__ENABLE_FEATURES = 0,
37 	TA_RAS_COMMAND__DISABLE_FEATURES,
38 	TA_RAS_COMMAND__TRIGGER_ERROR,
39 };
40 
41 enum ta_ras_status
42 {
43 	TA_RAS_STATUS__SUCCESS                          = 0x00,
44 	TA_RAS_STATUS__RESET_NEEDED                     = 0xA001,
45 	TA_RAS_STATUS__ERROR_INVALID_PARAMETER          = 0xA002,
46 	TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE          = 0xA003,
47 	TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD          = 0xA004,
48 	TA_RAS_STATUS__ERROR_INJECTION_FAILED           = 0xA005,
49 	TA_RAS_STATUS__ERROR_ASD_READ_WRITE             = 0xA006,
50 	TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE           = 0xA007,
51 	TA_RAS_STATUS__ERROR_TIMEOUT                    = 0xA008,
52 	TA_RAS_STATUS__ERROR_BLOCK_DISABLED             = 0XA009,
53 	TA_RAS_STATUS__ERROR_GENERIC                    = 0xA00A,
54 	TA_RAS_STATUS__ERROR_RAS_MMHUB_INIT             = 0xA00B,
55 	TA_RAS_STATUS__ERROR_GET_DEV_INFO               = 0xA00C,
56 	TA_RAS_STATUS__ERROR_UNSUPPORTED_DEV            = 0xA00D,
57 	TA_RAS_STATUS__ERROR_NOT_INITIALIZED            = 0xA00E,
58 	TA_RAS_STATUS__ERROR_TEE_INTERNAL               = 0xA00F
59 };
60 
61 enum ta_ras_block {
62 	TA_RAS_BLOCK__UMC = 0,
63 	TA_RAS_BLOCK__SDMA,
64 	TA_RAS_BLOCK__GFX,
65 	TA_RAS_BLOCK__MMHUB,
66 	TA_RAS_BLOCK__ATHUB,
67 	TA_RAS_BLOCK__PCIE_BIF,
68 	TA_RAS_BLOCK__HDP,
69 	TA_RAS_BLOCK__XGMI_WAFL,
70 	TA_RAS_BLOCK__DF,
71 	TA_RAS_BLOCK__SMN,
72 	TA_RAS_BLOCK__SEM,
73 	TA_RAS_BLOCK__MP0,
74 	TA_RAS_BLOCK__MP1,
75 	TA_RAS_BLOCK__FUSE,
76 	TA_NUM_BLOCK_MAX
77 };
78 
79 enum ta_ras_error_type {
80 	TA_RAS_ERROR__NONE			= 0,
81 	TA_RAS_ERROR__PARITY			= 1,
82 	TA_RAS_ERROR__SINGLE_CORRECTABLE	= 2,
83 	TA_RAS_ERROR__MULTI_UNCORRECTABLE	= 4,
84 	TA_RAS_ERROR__POISON			= 8,
85 };
86 
87 /* Input/output structures for RAS commands */
88 /**********************************************************/
89 
90 struct ta_ras_enable_features_input {
91 	enum ta_ras_block	block_id;
92 	enum ta_ras_error_type	error_type;
93 };
94 
95 struct ta_ras_disable_features_input {
96 	enum ta_ras_block	block_id;
97 	enum ta_ras_error_type	error_type;
98 };
99 
100 struct ta_ras_trigger_error_input {
101 	enum ta_ras_block	block_id;		// ras-block. i.e. umc, gfx
102 	enum ta_ras_error_type	inject_error_type;	// type of error. i.e. single_correctable
103 	uint32_t		sub_block_index;	// mem block. i.e. hbm, sram etc.
104 	uint64_t		address;		// explicit address of error
105 	uint64_t		value;			// method if error injection. i.e persistent, coherent etc.
106 };
107 
108 struct ta_ras_init_flags
109 {
110     uint8_t     poison_mode_en;
111     uint8_t     dgpu_mode;
112 };
113 
114 struct ta_ras_output_flags
115 {
116 	uint8_t    ras_init_success_flag;
117 	uint8_t    err_inject_switch_disable_flag;
118 	uint8_t    reg_access_failure_flag;
119 };
120 
121 /* Common input structure for RAS callbacks */
122 /**********************************************************/
123 union ta_ras_cmd_input {
124 	struct ta_ras_init_flags		init_flags;
125 	struct ta_ras_enable_features_input	enable_features;
126 	struct ta_ras_disable_features_input	disable_features;
127 	struct ta_ras_trigger_error_input	trigger_error;
128 
129 	uint32_t	reserve_pad[256];
130 };
131 
132 union ta_ras_cmd_output
133 {
134 	struct ta_ras_output_flags  flags;
135 
136 	uint32_t	reserve_pad[256];
137 };
138 
139 /* Shared Memory structures */
140 /**********************************************************/
141 struct ta_ras_shared_memory {
142 	uint32_t		    cmd_id;
143 	uint32_t		    resp_id;
144 	uint32_t	    	    ras_status;
145 	uint32_t		    if_version;
146 	union ta_ras_cmd_input	    ras_in_message;
147 	union ta_ras_cmd_output     ras_out_message;
148 };
149 
150 #endif // TL_RAS_IF_H_
151