1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _TA_RAS_IF_H 25 #define _TA_RAS_IF_H 26 27 /* Responses have bit 31 set */ 28 #define RSP_ID_MASK (1U << 31) 29 #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK) 30 31 /* RAS related enumerations */ 32 /**********************************************************/ 33 enum ras_command { 34 TA_RAS_COMMAND__ENABLE_FEATURES = 0, 35 TA_RAS_COMMAND__DISABLE_FEATURES, 36 TA_RAS_COMMAND__TRIGGER_ERROR, 37 }; 38 39 enum ta_ras_status { 40 TA_RAS_STATUS__SUCCESS = 0x00, 41 TA_RAS_STATUS__RESET_NEEDED = 0x01, 42 TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0x02, 43 TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0x03, 44 TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0x04, 45 TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0x05, 46 TA_RAS_STATUS__ERROR_ASD_READ_WRITE = 0x06, 47 TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE = 0x07, 48 TA_RAS_STATUS__ERROR_TIMEOUT = 0x08, 49 TA_RAS_STATUS__ERROR_BLOCK_DISABLED = 0x09, 50 TA_RAS_STATUS__ERROR_GENERIC = 0x10, 51 }; 52 53 enum ta_ras_block { 54 TA_RAS_BLOCK__UMC = 0, 55 TA_RAS_BLOCK__SDMA, 56 TA_RAS_BLOCK__GFX, 57 TA_RAS_BLOCK__MMHUB, 58 TA_RAS_BLOCK__ATHUB, 59 TA_RAS_BLOCK__PCIE_BIF, 60 TA_RAS_BLOCK__HDP, 61 TA_RAS_BLOCK__XGMI_WAFL, 62 TA_RAS_BLOCK__DF, 63 TA_RAS_BLOCK__SMN, 64 TA_RAS_BLOCK__SEM, 65 TA_RAS_BLOCK__MP0, 66 TA_RAS_BLOCK__MP1, 67 TA_RAS_BLOCK__FUSE, 68 TA_NUM_BLOCK_MAX 69 }; 70 71 enum ta_ras_error_type { 72 TA_RAS_ERROR__NONE = 0, 73 TA_RAS_ERROR__PARITY = 1, 74 TA_RAS_ERROR__SINGLE_CORRECTABLE = 2, 75 TA_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 76 TA_RAS_ERROR__POISON = 8, 77 }; 78 79 /* Input/output structures for RAS commands */ 80 /**********************************************************/ 81 82 struct ta_ras_enable_features_input { 83 enum ta_ras_block block_id; 84 enum ta_ras_error_type error_type; 85 }; 86 87 struct ta_ras_disable_features_input { 88 enum ta_ras_block block_id; 89 enum ta_ras_error_type error_type; 90 }; 91 92 struct ta_ras_trigger_error_input { 93 enum ta_ras_block block_id; // ras-block. i.e. umc, gfx 94 enum ta_ras_error_type inject_error_type; // type of error. i.e. single_correctable 95 uint32_t sub_block_index; // mem block. i.e. hbm, sram etc. 96 uint64_t address; // explicit address of error 97 uint64_t value; // method if error injection. i.e persistent, coherent etc. 98 }; 99 100 /* Common input structure for RAS callbacks */ 101 /**********************************************************/ 102 union ta_ras_cmd_input { 103 struct ta_ras_enable_features_input enable_features; 104 struct ta_ras_disable_features_input disable_features; 105 struct ta_ras_trigger_error_input trigger_error; 106 }; 107 108 /* Shared Memory structures */ 109 /**********************************************************/ 110 struct ta_ras_shared_memory { 111 uint32_t cmd_id; 112 uint32_t resp_id; 113 enum ta_ras_status ras_status; 114 uint32_t reserved; 115 union ta_ras_cmd_input ras_in_message; 116 }; 117 118 #endif // TL_RAS_IF_H_ 119