1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_11_0_0_offset.h" 40 #include "gc/gc_11_0_0_sh_mask.h" 41 #include "mp/mp_13_0_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15_common.h" 45 #include "soc21.h" 46 #include "mxgpu_nv.h" 47 48 static const struct amd_ip_funcs soc21_common_ip_funcs; 49 50 /* SOC21 */ 51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = 52 { 53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 55 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 56 }; 57 58 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = 59 { 60 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 61 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 62 }; 63 64 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = 65 { 66 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0), 67 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0, 68 }; 69 70 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = 71 { 72 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1), 73 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1, 74 }; 75 76 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = 77 { 78 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 79 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 80 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 83 }; 84 85 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = 86 { 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 91 }; 92 93 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = 94 { 95 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0), 96 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0, 97 }; 98 99 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = 100 { 101 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1), 102 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1, 103 }; 104 105 /* SRIOV SOC21, not const since data is controlled by host */ 106 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 110 }; 111 112 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 114 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 115 }; 116 117 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = { 118 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 119 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 120 }; 121 122 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = { 123 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 124 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 125 }; 126 127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136 }; 137 138 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 139 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 146 }; 147 148 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = { 149 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0), 150 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 151 }; 152 153 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = { 154 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1), 155 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 156 }; 157 158 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, 159 const struct amdgpu_video_codecs **codecs) 160 { 161 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 162 return -EINVAL; 163 164 switch (adev->ip_versions[UVD_HWIP][0]) { 165 case IP_VERSION(4, 0, 0): 166 case IP_VERSION(4, 0, 2): 167 case IP_VERSION(4, 0, 4): 168 if (amdgpu_sriov_vf(adev)) { 169 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 170 !amdgpu_sriov_is_av1_support(adev)) { 171 if (encode) 172 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1; 173 else 174 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1; 175 } else { 176 if (encode) 177 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0; 178 else 179 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0; 180 } 181 } else { 182 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { 183 if (encode) 184 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1; 185 else 186 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1; 187 } else { 188 if (encode) 189 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 190 else 191 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 192 } 193 } 194 return 0; 195 default: 196 return -EINVAL; 197 } 198 } 199 200 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) 201 { 202 unsigned long flags, address, data; 203 u32 r; 204 205 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 206 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 207 208 spin_lock_irqsave(&adev->didt_idx_lock, flags); 209 WREG32(address, (reg)); 210 r = RREG32(data); 211 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 212 return r; 213 } 214 215 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 216 { 217 unsigned long flags, address, data; 218 219 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 220 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 221 222 spin_lock_irqsave(&adev->didt_idx_lock, flags); 223 WREG32(address, (reg)); 224 WREG32(data, (v)); 225 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 226 } 227 228 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) 229 { 230 return adev->nbio.funcs->get_memsize(adev); 231 } 232 233 static u32 soc21_get_xclk(struct amdgpu_device *adev) 234 { 235 return adev->clock.spll.reference_freq; 236 } 237 238 239 void soc21_grbm_select(struct amdgpu_device *adev, 240 u32 me, u32 pipe, u32 queue, u32 vmid) 241 { 242 u32 grbm_gfx_cntl = 0; 243 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 244 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 245 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 246 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 247 248 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); 249 } 250 251 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) 252 { 253 /* todo */ 254 return false; 255 } 256 257 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { 258 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, 259 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, 260 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, 261 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, 262 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, 263 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, 264 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, 265 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, 266 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, 267 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, 268 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, 269 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, 270 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, 271 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, 272 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, 273 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, 274 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, 275 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, 276 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, 277 }; 278 279 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 280 u32 sh_num, u32 reg_offset) 281 { 282 uint32_t val; 283 284 mutex_lock(&adev->grbm_idx_mutex); 285 if (se_num != 0xffffffff || sh_num != 0xffffffff) 286 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 287 288 val = RREG32(reg_offset); 289 290 if (se_num != 0xffffffff || sh_num != 0xffffffff) 291 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 292 mutex_unlock(&adev->grbm_idx_mutex); 293 return val; 294 } 295 296 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, 297 bool indexed, u32 se_num, 298 u32 sh_num, u32 reg_offset) 299 { 300 if (indexed) { 301 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); 302 } else { 303 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 304 return adev->gfx.config.gb_addr_config; 305 return RREG32(reg_offset); 306 } 307 } 308 309 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, 310 u32 sh_num, u32 reg_offset, u32 *value) 311 { 312 uint32_t i; 313 struct soc15_allowed_register_entry *en; 314 315 *value = 0; 316 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { 317 en = &soc21_allowed_read_registers[i]; 318 if (!adev->reg_offset[en->hwip][en->inst]) 319 continue; 320 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 321 + en->reg_offset)) 322 continue; 323 324 *value = soc21_get_register_value(adev, 325 soc21_allowed_read_registers[i].grbm_indexed, 326 se_num, sh_num, reg_offset); 327 return 0; 328 } 329 return -EINVAL; 330 } 331 332 #if 0 333 static int soc21_asic_mode1_reset(struct amdgpu_device *adev) 334 { 335 u32 i; 336 int ret = 0; 337 338 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 339 340 /* disable BM */ 341 pci_clear_master(adev->pdev); 342 343 amdgpu_device_cache_pci_state(adev->pdev); 344 345 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 346 dev_info(adev->dev, "GPU smu mode1 reset\n"); 347 ret = amdgpu_dpm_mode1_reset(adev); 348 } else { 349 dev_info(adev->dev, "GPU psp mode1 reset\n"); 350 ret = psp_gpu_reset(adev); 351 } 352 353 if (ret) 354 dev_err(adev->dev, "GPU mode1 reset failed\n"); 355 amdgpu_device_load_pci_state(adev->pdev); 356 357 /* wait for asic to come out of reset */ 358 for (i = 0; i < adev->usec_timeout; i++) { 359 u32 memsize = adev->nbio.funcs->get_memsize(adev); 360 361 if (memsize != 0xffffffff) 362 break; 363 udelay(1); 364 } 365 366 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 367 368 return ret; 369 } 370 #endif 371 372 static enum amd_reset_method 373 soc21_asic_reset_method(struct amdgpu_device *adev) 374 { 375 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 376 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 377 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 378 return amdgpu_reset_method; 379 380 if (amdgpu_reset_method != -1) 381 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 382 amdgpu_reset_method); 383 384 switch (adev->ip_versions[MP1_HWIP][0]) { 385 case IP_VERSION(13, 0, 0): 386 case IP_VERSION(13, 0, 7): 387 case IP_VERSION(13, 0, 10): 388 return AMD_RESET_METHOD_MODE1; 389 case IP_VERSION(13, 0, 4): 390 case IP_VERSION(13, 0, 11): 391 return AMD_RESET_METHOD_MODE2; 392 default: 393 if (amdgpu_dpm_is_baco_supported(adev)) 394 return AMD_RESET_METHOD_BACO; 395 else 396 return AMD_RESET_METHOD_MODE1; 397 } 398 } 399 400 static int soc21_asic_reset(struct amdgpu_device *adev) 401 { 402 int ret = 0; 403 404 switch (soc21_asic_reset_method(adev)) { 405 case AMD_RESET_METHOD_PCI: 406 dev_info(adev->dev, "PCI reset\n"); 407 ret = amdgpu_device_pci_reset(adev); 408 break; 409 case AMD_RESET_METHOD_BACO: 410 dev_info(adev->dev, "BACO reset\n"); 411 ret = amdgpu_dpm_baco_reset(adev); 412 break; 413 case AMD_RESET_METHOD_MODE2: 414 dev_info(adev->dev, "MODE2 reset\n"); 415 ret = amdgpu_dpm_mode2_reset(adev); 416 break; 417 default: 418 dev_info(adev->dev, "MODE1 reset\n"); 419 ret = amdgpu_device_mode1_reset(adev); 420 break; 421 } 422 423 return ret; 424 } 425 426 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 427 { 428 /* todo */ 429 return 0; 430 } 431 432 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 433 { 434 /* todo */ 435 return 0; 436 } 437 438 static void soc21_program_aspm(struct amdgpu_device *adev) 439 { 440 if (!amdgpu_device_should_use_aspm(adev)) 441 return; 442 443 if (!(adev->flags & AMD_IS_APU) && 444 (adev->nbio.funcs->program_aspm)) 445 adev->nbio.funcs->program_aspm(adev); 446 } 447 448 const struct amdgpu_ip_block_version soc21_common_ip_block = 449 { 450 .type = AMD_IP_BLOCK_TYPE_COMMON, 451 .major = 1, 452 .minor = 0, 453 .rev = 0, 454 .funcs = &soc21_common_ip_funcs, 455 }; 456 457 static bool soc21_need_full_reset(struct amdgpu_device *adev) 458 { 459 switch (adev->ip_versions[GC_HWIP][0]) { 460 case IP_VERSION(11, 0, 0): 461 return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC); 462 case IP_VERSION(11, 0, 2): 463 case IP_VERSION(11, 0, 3): 464 return false; 465 default: 466 return true; 467 } 468 } 469 470 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) 471 { 472 u32 sol_reg; 473 474 if (adev->flags & AMD_IS_APU) 475 return false; 476 477 /* Check sOS sign of life register to confirm sys driver and sOS 478 * are already been loaded. 479 */ 480 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 481 if (sol_reg) 482 return true; 483 484 return false; 485 } 486 487 static void soc21_init_doorbell_index(struct amdgpu_device *adev) 488 { 489 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 490 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 491 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 492 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 493 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 494 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 495 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 496 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 497 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 498 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 499 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 500 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 501 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 502 adev->doorbell_index.gfx_userqueue_start = 503 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 504 adev->doorbell_index.gfx_userqueue_end = 505 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 506 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 507 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 508 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 509 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 510 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 511 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 512 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 513 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 514 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 515 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 516 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 517 518 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 519 adev->doorbell_index.sdma_doorbell_range = 20; 520 } 521 522 static void soc21_pre_asic_init(struct amdgpu_device *adev) 523 { 524 } 525 526 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, 527 bool enter) 528 { 529 if (enter) 530 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 531 else 532 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 533 534 if (adev->gfx.funcs->update_perfmon_mgcg) 535 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 536 537 return 0; 538 } 539 540 static const struct amdgpu_asic_funcs soc21_asic_funcs = 541 { 542 .read_disabled_bios = &soc21_read_disabled_bios, 543 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 544 .read_register = &soc21_read_register, 545 .reset = &soc21_asic_reset, 546 .reset_method = &soc21_asic_reset_method, 547 .get_xclk = &soc21_get_xclk, 548 .set_uvd_clocks = &soc21_set_uvd_clocks, 549 .set_vce_clocks = &soc21_set_vce_clocks, 550 .get_config_memsize = &soc21_get_config_memsize, 551 .init_doorbell_index = &soc21_init_doorbell_index, 552 .need_full_reset = &soc21_need_full_reset, 553 .need_reset_on_init = &soc21_need_reset_on_init, 554 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 555 .supports_baco = &amdgpu_dpm_is_baco_supported, 556 .pre_asic_init = &soc21_pre_asic_init, 557 .query_video_codecs = &soc21_query_video_codecs, 558 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, 559 }; 560 561 static int soc21_common_early_init(void *handle) 562 { 563 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 564 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 565 566 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 567 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 568 adev->smc_rreg = NULL; 569 adev->smc_wreg = NULL; 570 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 571 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 572 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 573 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 574 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 575 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 576 577 /* TODO: will add them during VCN v2 implementation */ 578 adev->uvd_ctx_rreg = NULL; 579 adev->uvd_ctx_wreg = NULL; 580 581 adev->didt_rreg = &soc21_didt_rreg; 582 adev->didt_wreg = &soc21_didt_wreg; 583 584 adev->asic_funcs = &soc21_asic_funcs; 585 586 adev->rev_id = amdgpu_device_get_rev_id(adev); 587 adev->external_rev_id = 0xff; 588 switch (adev->ip_versions[GC_HWIP][0]) { 589 case IP_VERSION(11, 0, 0): 590 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 591 AMD_CG_SUPPORT_GFX_CGLS | 592 #if 0 593 AMD_CG_SUPPORT_GFX_3D_CGCG | 594 AMD_CG_SUPPORT_GFX_3D_CGLS | 595 #endif 596 AMD_CG_SUPPORT_GFX_MGCG | 597 AMD_CG_SUPPORT_REPEATER_FGCG | 598 AMD_CG_SUPPORT_GFX_FGCG | 599 AMD_CG_SUPPORT_GFX_PERF_CLK | 600 AMD_CG_SUPPORT_VCN_MGCG | 601 AMD_CG_SUPPORT_JPEG_MGCG | 602 AMD_CG_SUPPORT_ATHUB_MGCG | 603 AMD_CG_SUPPORT_ATHUB_LS | 604 AMD_CG_SUPPORT_MC_MGCG | 605 AMD_CG_SUPPORT_MC_LS | 606 AMD_CG_SUPPORT_IH_CG | 607 AMD_CG_SUPPORT_HDP_SD; 608 adev->pg_flags = AMD_PG_SUPPORT_VCN | 609 AMD_PG_SUPPORT_VCN_DPG | 610 AMD_PG_SUPPORT_JPEG | 611 AMD_PG_SUPPORT_ATHUB | 612 AMD_PG_SUPPORT_MMHUB; 613 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update 614 break; 615 case IP_VERSION(11, 0, 2): 616 adev->cg_flags = 617 AMD_CG_SUPPORT_GFX_CGCG | 618 AMD_CG_SUPPORT_GFX_CGLS | 619 AMD_CG_SUPPORT_REPEATER_FGCG | 620 AMD_CG_SUPPORT_VCN_MGCG | 621 AMD_CG_SUPPORT_JPEG_MGCG | 622 AMD_CG_SUPPORT_ATHUB_MGCG | 623 AMD_CG_SUPPORT_ATHUB_LS | 624 AMD_CG_SUPPORT_IH_CG | 625 AMD_CG_SUPPORT_HDP_SD; 626 adev->pg_flags = 627 AMD_PG_SUPPORT_VCN | 628 AMD_PG_SUPPORT_VCN_DPG | 629 AMD_PG_SUPPORT_JPEG | 630 AMD_PG_SUPPORT_ATHUB | 631 AMD_PG_SUPPORT_MMHUB; 632 adev->external_rev_id = adev->rev_id + 0x10; 633 break; 634 case IP_VERSION(11, 0, 1): 635 adev->cg_flags = 636 AMD_CG_SUPPORT_GFX_CGCG | 637 AMD_CG_SUPPORT_GFX_CGLS | 638 AMD_CG_SUPPORT_GFX_MGCG | 639 AMD_CG_SUPPORT_GFX_FGCG | 640 AMD_CG_SUPPORT_REPEATER_FGCG | 641 AMD_CG_SUPPORT_GFX_PERF_CLK | 642 AMD_CG_SUPPORT_MC_MGCG | 643 AMD_CG_SUPPORT_MC_LS | 644 AMD_CG_SUPPORT_HDP_MGCG | 645 AMD_CG_SUPPORT_HDP_LS | 646 AMD_CG_SUPPORT_ATHUB_MGCG | 647 AMD_CG_SUPPORT_ATHUB_LS | 648 AMD_CG_SUPPORT_IH_CG | 649 AMD_CG_SUPPORT_BIF_MGCG | 650 AMD_CG_SUPPORT_BIF_LS | 651 AMD_CG_SUPPORT_VCN_MGCG | 652 AMD_CG_SUPPORT_JPEG_MGCG; 653 adev->pg_flags = 654 AMD_PG_SUPPORT_GFX_PG | 655 AMD_PG_SUPPORT_VCN | 656 AMD_PG_SUPPORT_VCN_DPG | 657 AMD_PG_SUPPORT_JPEG; 658 adev->external_rev_id = adev->rev_id + 0x1; 659 break; 660 case IP_VERSION(11, 0, 3): 661 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 662 AMD_CG_SUPPORT_JPEG_MGCG | 663 AMD_CG_SUPPORT_GFX_CGCG | 664 AMD_CG_SUPPORT_GFX_CGLS | 665 AMD_CG_SUPPORT_REPEATER_FGCG | 666 AMD_CG_SUPPORT_GFX_MGCG | 667 AMD_CG_SUPPORT_HDP_SD | 668 AMD_CG_SUPPORT_ATHUB_MGCG | 669 AMD_CG_SUPPORT_ATHUB_LS; 670 adev->pg_flags = AMD_PG_SUPPORT_VCN | 671 AMD_PG_SUPPORT_VCN_DPG | 672 AMD_PG_SUPPORT_JPEG; 673 adev->external_rev_id = adev->rev_id + 0x20; 674 break; 675 case IP_VERSION(11, 0, 4): 676 adev->cg_flags = 677 AMD_CG_SUPPORT_GFX_CGCG | 678 AMD_CG_SUPPORT_GFX_CGLS | 679 AMD_CG_SUPPORT_GFX_MGCG | 680 AMD_CG_SUPPORT_GFX_FGCG | 681 AMD_CG_SUPPORT_REPEATER_FGCG | 682 AMD_CG_SUPPORT_GFX_PERF_CLK | 683 AMD_CG_SUPPORT_MC_MGCG | 684 AMD_CG_SUPPORT_MC_LS | 685 AMD_CG_SUPPORT_HDP_MGCG | 686 AMD_CG_SUPPORT_HDP_LS | 687 AMD_CG_SUPPORT_ATHUB_MGCG | 688 AMD_CG_SUPPORT_ATHUB_LS | 689 AMD_CG_SUPPORT_IH_CG | 690 AMD_CG_SUPPORT_BIF_MGCG | 691 AMD_CG_SUPPORT_BIF_LS | 692 AMD_CG_SUPPORT_VCN_MGCG | 693 AMD_CG_SUPPORT_JPEG_MGCG; 694 adev->pg_flags = AMD_PG_SUPPORT_VCN | 695 AMD_PG_SUPPORT_VCN_DPG | 696 AMD_PG_SUPPORT_GFX_PG | 697 AMD_PG_SUPPORT_JPEG; 698 adev->external_rev_id = adev->rev_id + 0x80; 699 break; 700 701 default: 702 /* FIXME: not supported yet */ 703 return -EINVAL; 704 } 705 706 if (amdgpu_sriov_vf(adev)) { 707 amdgpu_virt_init_setting(adev); 708 xgpu_nv_mailbox_set_irq_funcs(adev); 709 } 710 711 return 0; 712 } 713 714 static int soc21_common_late_init(void *handle) 715 { 716 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 717 718 if (amdgpu_sriov_vf(adev)) { 719 xgpu_nv_mailbox_get_irq(adev); 720 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 721 !amdgpu_sriov_is_av1_support(adev)) { 722 amdgpu_virt_update_sriov_video_codec(adev, 723 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 724 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 725 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 726 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1)); 727 } else { 728 amdgpu_virt_update_sriov_video_codec(adev, 729 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 730 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 731 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 732 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0)); 733 } 734 } else { 735 if (adev->nbio.ras && 736 adev->nbio.ras_err_event_athub_irq.funcs) 737 /* don't need to fail gpu late init 738 * if enabling athub_err_event interrupt failed 739 * nbio v4_3 only support fatal error hanlding 740 * just enable the interrupt directly */ 741 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); 742 } 743 744 /* Enable selfring doorbell aperture late because doorbell BAR 745 * aperture will change if resize BAR successfully in gmc sw_init. 746 */ 747 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 748 749 return 0; 750 } 751 752 static int soc21_common_sw_init(void *handle) 753 { 754 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 755 756 if (amdgpu_sriov_vf(adev)) 757 xgpu_nv_mailbox_add_irq_id(adev); 758 759 return 0; 760 } 761 762 static int soc21_common_sw_fini(void *handle) 763 { 764 return 0; 765 } 766 767 static int soc21_common_hw_init(void *handle) 768 { 769 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 770 771 /* enable aspm */ 772 soc21_program_aspm(adev); 773 /* setup nbio registers */ 774 adev->nbio.funcs->init_registers(adev); 775 /* remap HDP registers to a hole in mmio space, 776 * for the purpose of expose those registers 777 * to process space 778 */ 779 if (adev->nbio.funcs->remap_hdp_registers) 780 adev->nbio.funcs->remap_hdp_registers(adev); 781 /* enable the doorbell aperture */ 782 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 783 784 return 0; 785 } 786 787 static int soc21_common_hw_fini(void *handle) 788 { 789 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 790 791 /* Disable the doorbell aperture and selfring doorbell aperture 792 * separately in hw_fini because soc21_enable_doorbell_aperture 793 * has been removed and there is no need to delay disabling 794 * selfring doorbell. 795 */ 796 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 797 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 798 799 if (amdgpu_sriov_vf(adev)) { 800 xgpu_nv_mailbox_put_irq(adev); 801 } else { 802 if (adev->nbio.ras && 803 adev->nbio.ras_err_event_athub_irq.funcs) 804 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 805 } 806 807 return 0; 808 } 809 810 static int soc21_common_suspend(void *handle) 811 { 812 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 813 814 return soc21_common_hw_fini(adev); 815 } 816 817 static int soc21_common_resume(void *handle) 818 { 819 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 820 821 return soc21_common_hw_init(adev); 822 } 823 824 static bool soc21_common_is_idle(void *handle) 825 { 826 return true; 827 } 828 829 static int soc21_common_wait_for_idle(void *handle) 830 { 831 return 0; 832 } 833 834 static int soc21_common_soft_reset(void *handle) 835 { 836 return 0; 837 } 838 839 static int soc21_common_set_clockgating_state(void *handle, 840 enum amd_clockgating_state state) 841 { 842 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 843 844 switch (adev->ip_versions[NBIO_HWIP][0]) { 845 case IP_VERSION(4, 3, 0): 846 case IP_VERSION(4, 3, 1): 847 case IP_VERSION(7, 7, 0): 848 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 849 state == AMD_CG_STATE_GATE); 850 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 851 state == AMD_CG_STATE_GATE); 852 adev->hdp.funcs->update_clock_gating(adev, 853 state == AMD_CG_STATE_GATE); 854 break; 855 default: 856 break; 857 } 858 return 0; 859 } 860 861 static int soc21_common_set_powergating_state(void *handle, 862 enum amd_powergating_state state) 863 { 864 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 865 866 switch (adev->ip_versions[LSDMA_HWIP][0]) { 867 case IP_VERSION(6, 0, 0): 868 case IP_VERSION(6, 0, 2): 869 adev->lsdma.funcs->update_memory_power_gating(adev, 870 state == AMD_PG_STATE_GATE); 871 break; 872 default: 873 break; 874 } 875 876 return 0; 877 } 878 879 static void soc21_common_get_clockgating_state(void *handle, u64 *flags) 880 { 881 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 882 883 adev->nbio.funcs->get_clockgating_state(adev, flags); 884 885 adev->hdp.funcs->get_clock_gating_state(adev, flags); 886 887 return; 888 } 889 890 static const struct amd_ip_funcs soc21_common_ip_funcs = { 891 .name = "soc21_common", 892 .early_init = soc21_common_early_init, 893 .late_init = soc21_common_late_init, 894 .sw_init = soc21_common_sw_init, 895 .sw_fini = soc21_common_sw_fini, 896 .hw_init = soc21_common_hw_init, 897 .hw_fini = soc21_common_hw_fini, 898 .suspend = soc21_common_suspend, 899 .resume = soc21_common_resume, 900 .is_idle = soc21_common_is_idle, 901 .wait_for_idle = soc21_common_wait_for_idle, 902 .soft_reset = soc21_common_soft_reset, 903 .set_clockgating_state = soc21_common_set_clockgating_state, 904 .set_powergating_state = soc21_common_set_powergating_state, 905 .get_clockgating_state = soc21_common_get_clockgating_state, 906 }; 907