1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_11_0_0_offset.h" 40 #include "gc/gc_11_0_0_sh_mask.h" 41 #include "mp/mp_13_0_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15_common.h" 45 #include "soc21.h" 46 #include "mxgpu_nv.h" 47 48 static const struct amd_ip_funcs soc21_common_ip_funcs; 49 50 /* SOC21 */ 51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 55 }; 56 57 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 60 }; 61 62 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = { 63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0), 64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0, 65 }; 66 67 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = { 68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1), 69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1, 70 }; 71 72 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 78 }; 79 80 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 85 }; 86 87 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = { 88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0), 89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0, 90 }; 91 92 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = { 93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1), 94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1, 95 }; 96 97 /* SRIOV SOC21, not const since data is controlled by host */ 98 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 102 }; 103 104 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 107 }; 108 109 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = { 110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 112 }; 113 114 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = { 115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 117 }; 118 119 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 128 }; 129 130 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 136 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 137 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 138 }; 139 140 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = { 141 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0), 142 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 143 }; 144 145 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = { 146 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1), 147 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 148 }; 149 150 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, 151 const struct amdgpu_video_codecs **codecs) 152 { 153 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 154 return -EINVAL; 155 156 switch (adev->ip_versions[UVD_HWIP][0]) { 157 case IP_VERSION(4, 0, 0): 158 case IP_VERSION(4, 0, 2): 159 case IP_VERSION(4, 0, 4): 160 if (amdgpu_sriov_vf(adev)) { 161 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 162 !amdgpu_sriov_is_av1_support(adev)) { 163 if (encode) 164 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1; 165 else 166 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1; 167 } else { 168 if (encode) 169 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0; 170 else 171 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0; 172 } 173 } else { 174 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { 175 if (encode) 176 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1; 177 else 178 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1; 179 } else { 180 if (encode) 181 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 182 else 183 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 184 } 185 } 186 return 0; 187 default: 188 return -EINVAL; 189 } 190 } 191 192 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) 193 { 194 unsigned long flags, address, data; 195 u32 r; 196 197 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 198 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 199 200 spin_lock_irqsave(&adev->didt_idx_lock, flags); 201 WREG32(address, (reg)); 202 r = RREG32(data); 203 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 204 return r; 205 } 206 207 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 208 { 209 unsigned long flags, address, data; 210 211 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 212 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 213 214 spin_lock_irqsave(&adev->didt_idx_lock, flags); 215 WREG32(address, (reg)); 216 WREG32(data, (v)); 217 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 218 } 219 220 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) 221 { 222 return adev->nbio.funcs->get_memsize(adev); 223 } 224 225 static u32 soc21_get_xclk(struct amdgpu_device *adev) 226 { 227 return adev->clock.spll.reference_freq; 228 } 229 230 231 void soc21_grbm_select(struct amdgpu_device *adev, 232 u32 me, u32 pipe, u32 queue, u32 vmid) 233 { 234 u32 grbm_gfx_cntl = 0; 235 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 236 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 237 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 238 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 239 240 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); 241 } 242 243 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) 244 { 245 /* todo */ 246 return false; 247 } 248 249 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { 250 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, 251 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, 252 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, 253 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, 254 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, 255 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, 256 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, 257 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, 258 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, 259 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, 260 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, 261 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, 262 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, 263 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, 264 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, 265 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, 266 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, 267 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, 268 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, 269 }; 270 271 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 272 u32 sh_num, u32 reg_offset) 273 { 274 uint32_t val; 275 276 mutex_lock(&adev->grbm_idx_mutex); 277 if (se_num != 0xffffffff || sh_num != 0xffffffff) 278 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 279 280 val = RREG32(reg_offset); 281 282 if (se_num != 0xffffffff || sh_num != 0xffffffff) 283 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 284 mutex_unlock(&adev->grbm_idx_mutex); 285 return val; 286 } 287 288 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, 289 bool indexed, u32 se_num, 290 u32 sh_num, u32 reg_offset) 291 { 292 if (indexed) { 293 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); 294 } else { 295 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 296 return adev->gfx.config.gb_addr_config; 297 return RREG32(reg_offset); 298 } 299 } 300 301 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, 302 u32 sh_num, u32 reg_offset, u32 *value) 303 { 304 uint32_t i; 305 struct soc15_allowed_register_entry *en; 306 307 *value = 0; 308 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { 309 en = &soc21_allowed_read_registers[i]; 310 if (!adev->reg_offset[en->hwip][en->inst]) 311 continue; 312 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 313 + en->reg_offset)) 314 continue; 315 316 *value = soc21_get_register_value(adev, 317 soc21_allowed_read_registers[i].grbm_indexed, 318 se_num, sh_num, reg_offset); 319 return 0; 320 } 321 return -EINVAL; 322 } 323 324 #if 0 325 static int soc21_asic_mode1_reset(struct amdgpu_device *adev) 326 { 327 u32 i; 328 int ret = 0; 329 330 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 331 332 /* disable BM */ 333 pci_clear_master(adev->pdev); 334 335 amdgpu_device_cache_pci_state(adev->pdev); 336 337 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 338 dev_info(adev->dev, "GPU smu mode1 reset\n"); 339 ret = amdgpu_dpm_mode1_reset(adev); 340 } else { 341 dev_info(adev->dev, "GPU psp mode1 reset\n"); 342 ret = psp_gpu_reset(adev); 343 } 344 345 if (ret) 346 dev_err(adev->dev, "GPU mode1 reset failed\n"); 347 amdgpu_device_load_pci_state(adev->pdev); 348 349 /* wait for asic to come out of reset */ 350 for (i = 0; i < adev->usec_timeout; i++) { 351 u32 memsize = adev->nbio.funcs->get_memsize(adev); 352 353 if (memsize != 0xffffffff) 354 break; 355 udelay(1); 356 } 357 358 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 359 360 return ret; 361 } 362 #endif 363 364 static enum amd_reset_method 365 soc21_asic_reset_method(struct amdgpu_device *adev) 366 { 367 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 368 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 369 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 370 return amdgpu_reset_method; 371 372 if (amdgpu_reset_method != -1) 373 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 374 amdgpu_reset_method); 375 376 switch (adev->ip_versions[MP1_HWIP][0]) { 377 case IP_VERSION(13, 0, 0): 378 case IP_VERSION(13, 0, 7): 379 case IP_VERSION(13, 0, 10): 380 return AMD_RESET_METHOD_MODE1; 381 case IP_VERSION(13, 0, 4): 382 case IP_VERSION(13, 0, 11): 383 return AMD_RESET_METHOD_MODE2; 384 default: 385 if (amdgpu_dpm_is_baco_supported(adev)) 386 return AMD_RESET_METHOD_BACO; 387 else 388 return AMD_RESET_METHOD_MODE1; 389 } 390 } 391 392 static int soc21_asic_reset(struct amdgpu_device *adev) 393 { 394 int ret = 0; 395 396 switch (soc21_asic_reset_method(adev)) { 397 case AMD_RESET_METHOD_PCI: 398 dev_info(adev->dev, "PCI reset\n"); 399 ret = amdgpu_device_pci_reset(adev); 400 break; 401 case AMD_RESET_METHOD_BACO: 402 dev_info(adev->dev, "BACO reset\n"); 403 ret = amdgpu_dpm_baco_reset(adev); 404 break; 405 case AMD_RESET_METHOD_MODE2: 406 dev_info(adev->dev, "MODE2 reset\n"); 407 ret = amdgpu_dpm_mode2_reset(adev); 408 break; 409 default: 410 dev_info(adev->dev, "MODE1 reset\n"); 411 ret = amdgpu_device_mode1_reset(adev); 412 break; 413 } 414 415 return ret; 416 } 417 418 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 419 { 420 /* todo */ 421 return 0; 422 } 423 424 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 425 { 426 /* todo */ 427 return 0; 428 } 429 430 static void soc21_program_aspm(struct amdgpu_device *adev) 431 { 432 if (!amdgpu_device_should_use_aspm(adev)) 433 return; 434 435 if (!(adev->flags & AMD_IS_APU) && 436 (adev->nbio.funcs->program_aspm)) 437 adev->nbio.funcs->program_aspm(adev); 438 } 439 440 const struct amdgpu_ip_block_version soc21_common_ip_block = { 441 .type = AMD_IP_BLOCK_TYPE_COMMON, 442 .major = 1, 443 .minor = 0, 444 .rev = 0, 445 .funcs = &soc21_common_ip_funcs, 446 }; 447 448 static bool soc21_need_full_reset(struct amdgpu_device *adev) 449 { 450 switch (adev->ip_versions[GC_HWIP][0]) { 451 case IP_VERSION(11, 0, 0): 452 case IP_VERSION(11, 0, 2): 453 case IP_VERSION(11, 0, 3): 454 default: 455 return true; 456 } 457 } 458 459 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) 460 { 461 u32 sol_reg; 462 463 if (adev->flags & AMD_IS_APU) 464 return false; 465 466 /* Check sOS sign of life register to confirm sys driver and sOS 467 * are already been loaded. 468 */ 469 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 470 if (sol_reg) 471 return true; 472 473 return false; 474 } 475 476 static void soc21_init_doorbell_index(struct amdgpu_device *adev) 477 { 478 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 479 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 480 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 481 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 482 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 483 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 484 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 485 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 486 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 487 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 488 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 489 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 490 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 491 adev->doorbell_index.gfx_userqueue_start = 492 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 493 adev->doorbell_index.gfx_userqueue_end = 494 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 495 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 496 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 497 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 498 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 499 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 500 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 501 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 502 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 503 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 504 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 505 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 506 507 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 508 adev->doorbell_index.sdma_doorbell_range = 20; 509 } 510 511 static void soc21_pre_asic_init(struct amdgpu_device *adev) 512 { 513 } 514 515 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, 516 bool enter) 517 { 518 if (enter) 519 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 520 else 521 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 522 523 if (adev->gfx.funcs->update_perfmon_mgcg) 524 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 525 526 return 0; 527 } 528 529 static const struct amdgpu_asic_funcs soc21_asic_funcs = { 530 .read_disabled_bios = &soc21_read_disabled_bios, 531 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 532 .read_register = &soc21_read_register, 533 .reset = &soc21_asic_reset, 534 .reset_method = &soc21_asic_reset_method, 535 .get_xclk = &soc21_get_xclk, 536 .set_uvd_clocks = &soc21_set_uvd_clocks, 537 .set_vce_clocks = &soc21_set_vce_clocks, 538 .get_config_memsize = &soc21_get_config_memsize, 539 .init_doorbell_index = &soc21_init_doorbell_index, 540 .need_full_reset = &soc21_need_full_reset, 541 .need_reset_on_init = &soc21_need_reset_on_init, 542 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 543 .supports_baco = &amdgpu_dpm_is_baco_supported, 544 .pre_asic_init = &soc21_pre_asic_init, 545 .query_video_codecs = &soc21_query_video_codecs, 546 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, 547 }; 548 549 static int soc21_common_early_init(void *handle) 550 { 551 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 552 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 553 554 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 555 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 556 adev->smc_rreg = NULL; 557 adev->smc_wreg = NULL; 558 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 559 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 560 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 561 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 562 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 563 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 564 565 /* TODO: will add them during VCN v2 implementation */ 566 adev->uvd_ctx_rreg = NULL; 567 adev->uvd_ctx_wreg = NULL; 568 569 adev->didt_rreg = &soc21_didt_rreg; 570 adev->didt_wreg = &soc21_didt_wreg; 571 572 adev->asic_funcs = &soc21_asic_funcs; 573 574 adev->rev_id = amdgpu_device_get_rev_id(adev); 575 adev->external_rev_id = 0xff; 576 switch (adev->ip_versions[GC_HWIP][0]) { 577 case IP_VERSION(11, 0, 0): 578 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 579 AMD_CG_SUPPORT_GFX_CGLS | 580 #if 0 581 AMD_CG_SUPPORT_GFX_3D_CGCG | 582 AMD_CG_SUPPORT_GFX_3D_CGLS | 583 #endif 584 AMD_CG_SUPPORT_GFX_MGCG | 585 AMD_CG_SUPPORT_REPEATER_FGCG | 586 AMD_CG_SUPPORT_GFX_FGCG | 587 AMD_CG_SUPPORT_GFX_PERF_CLK | 588 AMD_CG_SUPPORT_VCN_MGCG | 589 AMD_CG_SUPPORT_JPEG_MGCG | 590 AMD_CG_SUPPORT_ATHUB_MGCG | 591 AMD_CG_SUPPORT_ATHUB_LS | 592 AMD_CG_SUPPORT_MC_MGCG | 593 AMD_CG_SUPPORT_MC_LS | 594 AMD_CG_SUPPORT_IH_CG | 595 AMD_CG_SUPPORT_HDP_SD; 596 adev->pg_flags = AMD_PG_SUPPORT_VCN | 597 AMD_PG_SUPPORT_VCN_DPG | 598 AMD_PG_SUPPORT_JPEG | 599 AMD_PG_SUPPORT_ATHUB | 600 AMD_PG_SUPPORT_MMHUB; 601 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update 602 break; 603 case IP_VERSION(11, 0, 2): 604 adev->cg_flags = 605 AMD_CG_SUPPORT_GFX_CGCG | 606 AMD_CG_SUPPORT_GFX_CGLS | 607 AMD_CG_SUPPORT_REPEATER_FGCG | 608 AMD_CG_SUPPORT_VCN_MGCG | 609 AMD_CG_SUPPORT_JPEG_MGCG | 610 AMD_CG_SUPPORT_ATHUB_MGCG | 611 AMD_CG_SUPPORT_ATHUB_LS | 612 AMD_CG_SUPPORT_IH_CG | 613 AMD_CG_SUPPORT_HDP_SD; 614 adev->pg_flags = 615 AMD_PG_SUPPORT_VCN | 616 AMD_PG_SUPPORT_VCN_DPG | 617 AMD_PG_SUPPORT_JPEG | 618 AMD_PG_SUPPORT_ATHUB | 619 AMD_PG_SUPPORT_MMHUB; 620 adev->external_rev_id = adev->rev_id + 0x10; 621 break; 622 case IP_VERSION(11, 0, 1): 623 adev->cg_flags = 624 AMD_CG_SUPPORT_GFX_CGCG | 625 AMD_CG_SUPPORT_GFX_CGLS | 626 AMD_CG_SUPPORT_GFX_MGCG | 627 AMD_CG_SUPPORT_GFX_FGCG | 628 AMD_CG_SUPPORT_REPEATER_FGCG | 629 AMD_CG_SUPPORT_GFX_PERF_CLK | 630 AMD_CG_SUPPORT_MC_MGCG | 631 AMD_CG_SUPPORT_MC_LS | 632 AMD_CG_SUPPORT_HDP_MGCG | 633 AMD_CG_SUPPORT_HDP_LS | 634 AMD_CG_SUPPORT_ATHUB_MGCG | 635 AMD_CG_SUPPORT_ATHUB_LS | 636 AMD_CG_SUPPORT_IH_CG | 637 AMD_CG_SUPPORT_BIF_MGCG | 638 AMD_CG_SUPPORT_BIF_LS | 639 AMD_CG_SUPPORT_VCN_MGCG | 640 AMD_CG_SUPPORT_JPEG_MGCG; 641 adev->pg_flags = 642 AMD_PG_SUPPORT_GFX_PG | 643 AMD_PG_SUPPORT_VCN | 644 AMD_PG_SUPPORT_VCN_DPG | 645 AMD_PG_SUPPORT_JPEG; 646 adev->external_rev_id = adev->rev_id + 0x1; 647 break; 648 case IP_VERSION(11, 0, 3): 649 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 650 AMD_CG_SUPPORT_JPEG_MGCG | 651 AMD_CG_SUPPORT_GFX_CGCG | 652 AMD_CG_SUPPORT_GFX_CGLS | 653 AMD_CG_SUPPORT_REPEATER_FGCG | 654 AMD_CG_SUPPORT_GFX_MGCG | 655 AMD_CG_SUPPORT_HDP_SD | 656 AMD_CG_SUPPORT_ATHUB_MGCG | 657 AMD_CG_SUPPORT_ATHUB_LS; 658 adev->pg_flags = AMD_PG_SUPPORT_VCN | 659 AMD_PG_SUPPORT_VCN_DPG | 660 AMD_PG_SUPPORT_JPEG; 661 adev->external_rev_id = adev->rev_id + 0x20; 662 break; 663 case IP_VERSION(11, 0, 4): 664 adev->cg_flags = 665 AMD_CG_SUPPORT_GFX_CGCG | 666 AMD_CG_SUPPORT_GFX_CGLS | 667 AMD_CG_SUPPORT_GFX_MGCG | 668 AMD_CG_SUPPORT_GFX_FGCG | 669 AMD_CG_SUPPORT_REPEATER_FGCG | 670 AMD_CG_SUPPORT_GFX_PERF_CLK | 671 AMD_CG_SUPPORT_MC_MGCG | 672 AMD_CG_SUPPORT_MC_LS | 673 AMD_CG_SUPPORT_HDP_MGCG | 674 AMD_CG_SUPPORT_HDP_LS | 675 AMD_CG_SUPPORT_ATHUB_MGCG | 676 AMD_CG_SUPPORT_ATHUB_LS | 677 AMD_CG_SUPPORT_IH_CG | 678 AMD_CG_SUPPORT_BIF_MGCG | 679 AMD_CG_SUPPORT_BIF_LS | 680 AMD_CG_SUPPORT_VCN_MGCG | 681 AMD_CG_SUPPORT_JPEG_MGCG; 682 adev->pg_flags = AMD_PG_SUPPORT_VCN | 683 AMD_PG_SUPPORT_VCN_DPG | 684 AMD_PG_SUPPORT_GFX_PG | 685 AMD_PG_SUPPORT_JPEG; 686 adev->external_rev_id = adev->rev_id + 0x80; 687 break; 688 689 default: 690 /* FIXME: not supported yet */ 691 return -EINVAL; 692 } 693 694 if (amdgpu_sriov_vf(adev)) { 695 amdgpu_virt_init_setting(adev); 696 xgpu_nv_mailbox_set_irq_funcs(adev); 697 } 698 699 return 0; 700 } 701 702 static int soc21_common_late_init(void *handle) 703 { 704 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 705 706 if (amdgpu_sriov_vf(adev)) { 707 xgpu_nv_mailbox_get_irq(adev); 708 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 709 !amdgpu_sriov_is_av1_support(adev)) { 710 amdgpu_virt_update_sriov_video_codec(adev, 711 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 712 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 713 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 714 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1)); 715 } else { 716 amdgpu_virt_update_sriov_video_codec(adev, 717 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 718 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 719 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 720 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0)); 721 } 722 } else { 723 if (adev->nbio.ras && 724 adev->nbio.ras_err_event_athub_irq.funcs) 725 /* don't need to fail gpu late init 726 * if enabling athub_err_event interrupt failed 727 * nbio v4_3 only support fatal error hanlding 728 * just enable the interrupt directly */ 729 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); 730 } 731 732 /* Enable selfring doorbell aperture late because doorbell BAR 733 * aperture will change if resize BAR successfully in gmc sw_init. 734 */ 735 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 736 737 return 0; 738 } 739 740 static int soc21_common_sw_init(void *handle) 741 { 742 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 743 744 if (amdgpu_sriov_vf(adev)) 745 xgpu_nv_mailbox_add_irq_id(adev); 746 747 return 0; 748 } 749 750 static int soc21_common_sw_fini(void *handle) 751 { 752 return 0; 753 } 754 755 static int soc21_common_hw_init(void *handle) 756 { 757 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 758 759 /* enable aspm */ 760 soc21_program_aspm(adev); 761 /* setup nbio registers */ 762 adev->nbio.funcs->init_registers(adev); 763 /* remap HDP registers to a hole in mmio space, 764 * for the purpose of expose those registers 765 * to process space 766 */ 767 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 768 adev->nbio.funcs->remap_hdp_registers(adev); 769 /* enable the doorbell aperture */ 770 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 771 772 return 0; 773 } 774 775 static int soc21_common_hw_fini(void *handle) 776 { 777 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 778 779 /* Disable the doorbell aperture and selfring doorbell aperture 780 * separately in hw_fini because soc21_enable_doorbell_aperture 781 * has been removed and there is no need to delay disabling 782 * selfring doorbell. 783 */ 784 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 785 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 786 787 if (amdgpu_sriov_vf(adev)) { 788 xgpu_nv_mailbox_put_irq(adev); 789 } else { 790 if (adev->nbio.ras && 791 adev->nbio.ras_err_event_athub_irq.funcs) 792 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 793 } 794 795 return 0; 796 } 797 798 static int soc21_common_suspend(void *handle) 799 { 800 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 801 802 return soc21_common_hw_fini(adev); 803 } 804 805 static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) 806 { 807 u32 sol_reg1, sol_reg2; 808 809 /* Will reset for the following suspend abort cases. 810 * 1) Only reset dGPU side. 811 * 2) S3 suspend got aborted and TOS is active. 812 */ 813 if (!(adev->flags & AMD_IS_APU) && adev->in_s3 && 814 !adev->suspend_complete) { 815 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 816 msleep(100); 817 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 818 819 return (sol_reg1 != sol_reg2); 820 } 821 822 return false; 823 } 824 825 static int soc21_common_resume(void *handle) 826 { 827 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 828 829 if (soc21_need_reset_on_resume(adev)) { 830 dev_info(adev->dev, "S3 suspend aborted, resetting..."); 831 soc21_asic_reset(adev); 832 } 833 834 return soc21_common_hw_init(adev); 835 } 836 837 static bool soc21_common_is_idle(void *handle) 838 { 839 return true; 840 } 841 842 static int soc21_common_wait_for_idle(void *handle) 843 { 844 return 0; 845 } 846 847 static int soc21_common_soft_reset(void *handle) 848 { 849 return 0; 850 } 851 852 static int soc21_common_set_clockgating_state(void *handle, 853 enum amd_clockgating_state state) 854 { 855 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 856 857 switch (adev->ip_versions[NBIO_HWIP][0]) { 858 case IP_VERSION(4, 3, 0): 859 case IP_VERSION(4, 3, 1): 860 case IP_VERSION(7, 7, 0): 861 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 862 state == AMD_CG_STATE_GATE); 863 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 864 state == AMD_CG_STATE_GATE); 865 adev->hdp.funcs->update_clock_gating(adev, 866 state == AMD_CG_STATE_GATE); 867 break; 868 default: 869 break; 870 } 871 return 0; 872 } 873 874 static int soc21_common_set_powergating_state(void *handle, 875 enum amd_powergating_state state) 876 { 877 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 878 879 switch (adev->ip_versions[LSDMA_HWIP][0]) { 880 case IP_VERSION(6, 0, 0): 881 case IP_VERSION(6, 0, 2): 882 adev->lsdma.funcs->update_memory_power_gating(adev, 883 state == AMD_PG_STATE_GATE); 884 break; 885 default: 886 break; 887 } 888 889 return 0; 890 } 891 892 static void soc21_common_get_clockgating_state(void *handle, u64 *flags) 893 { 894 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 895 896 adev->nbio.funcs->get_clockgating_state(adev, flags); 897 898 adev->hdp.funcs->get_clock_gating_state(adev, flags); 899 900 return; 901 } 902 903 static const struct amd_ip_funcs soc21_common_ip_funcs = { 904 .name = "soc21_common", 905 .early_init = soc21_common_early_init, 906 .late_init = soc21_common_late_init, 907 .sw_init = soc21_common_sw_init, 908 .sw_fini = soc21_common_sw_fini, 909 .hw_init = soc21_common_hw_init, 910 .hw_fini = soc21_common_hw_fini, 911 .suspend = soc21_common_suspend, 912 .resume = soc21_common_resume, 913 .is_idle = soc21_common_is_idle, 914 .wait_for_idle = soc21_common_wait_for_idle, 915 .soft_reset = soc21_common_soft_reset, 916 .set_clockgating_state = soc21_common_set_clockgating_state, 917 .set_powergating_state = soc21_common_set_powergating_state, 918 .get_clockgating_state = soc21_common_get_clockgating_state, 919 }; 920