1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_11_0_0_offset.h" 40 #include "gc/gc_11_0_0_sh_mask.h" 41 #include "mp/mp_13_0_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15_common.h" 45 #include "soc21.h" 46 #include "mxgpu_nv.h" 47 48 static const struct amd_ip_funcs soc21_common_ip_funcs; 49 50 /* SOC21 */ 51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = 52 { 53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 55 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 56 }; 57 58 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = 59 { 60 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 61 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 62 }; 63 64 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = 65 { 66 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0), 67 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0, 68 }; 69 70 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = 71 { 72 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1), 73 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1, 74 }; 75 76 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = 77 { 78 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 79 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 80 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 83 }; 84 85 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = 86 { 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 91 }; 92 93 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = 94 { 95 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0), 96 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0, 97 }; 98 99 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = 100 { 101 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1), 102 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1, 103 }; 104 105 /* SRIOV SOC21, not const since data is controlled by host */ 106 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 110 }; 111 112 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 114 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 115 }; 116 117 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = { 118 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 119 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 120 }; 121 122 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = { 123 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 124 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 125 }; 126 127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136 }; 137 138 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 139 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 146 }; 147 148 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = { 149 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0), 150 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 151 }; 152 153 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = { 154 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1), 155 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 156 }; 157 158 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, 159 const struct amdgpu_video_codecs **codecs) 160 { 161 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 162 return -EINVAL; 163 164 switch (adev->ip_versions[UVD_HWIP][0]) { 165 case IP_VERSION(4, 0, 0): 166 case IP_VERSION(4, 0, 2): 167 case IP_VERSION(4, 0, 4): 168 if (amdgpu_sriov_vf(adev)) { 169 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 170 !amdgpu_sriov_is_av1_support(adev)) { 171 if (encode) 172 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1; 173 else 174 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1; 175 } else { 176 if (encode) 177 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0; 178 else 179 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0; 180 } 181 } else { 182 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { 183 if (encode) 184 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1; 185 else 186 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1; 187 } else { 188 if (encode) 189 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 190 else 191 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 192 } 193 } 194 return 0; 195 default: 196 return -EINVAL; 197 } 198 } 199 200 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) 201 { 202 unsigned long flags, address, data; 203 u32 r; 204 205 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 206 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 207 208 spin_lock_irqsave(&adev->didt_idx_lock, flags); 209 WREG32(address, (reg)); 210 r = RREG32(data); 211 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 212 return r; 213 } 214 215 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 216 { 217 unsigned long flags, address, data; 218 219 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 220 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 221 222 spin_lock_irqsave(&adev->didt_idx_lock, flags); 223 WREG32(address, (reg)); 224 WREG32(data, (v)); 225 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 226 } 227 228 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) 229 { 230 return adev->nbio.funcs->get_memsize(adev); 231 } 232 233 static u32 soc21_get_xclk(struct amdgpu_device *adev) 234 { 235 return adev->clock.spll.reference_freq; 236 } 237 238 239 void soc21_grbm_select(struct amdgpu_device *adev, 240 u32 me, u32 pipe, u32 queue, u32 vmid) 241 { 242 u32 grbm_gfx_cntl = 0; 243 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 244 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 245 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 246 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 247 248 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); 249 } 250 251 static void soc21_vga_set_state(struct amdgpu_device *adev, bool state) 252 { 253 /* todo */ 254 } 255 256 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) 257 { 258 /* todo */ 259 return false; 260 } 261 262 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { 263 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, 264 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, 265 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, 266 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, 267 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, 268 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, 269 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, 270 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, 271 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, 272 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, 273 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, 274 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, 275 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, 276 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, 277 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, 278 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, 279 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, 280 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, 281 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, 282 }; 283 284 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 285 u32 sh_num, u32 reg_offset) 286 { 287 uint32_t val; 288 289 mutex_lock(&adev->grbm_idx_mutex); 290 if (se_num != 0xffffffff || sh_num != 0xffffffff) 291 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 292 293 val = RREG32(reg_offset); 294 295 if (se_num != 0xffffffff || sh_num != 0xffffffff) 296 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 297 mutex_unlock(&adev->grbm_idx_mutex); 298 return val; 299 } 300 301 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, 302 bool indexed, u32 se_num, 303 u32 sh_num, u32 reg_offset) 304 { 305 if (indexed) { 306 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); 307 } else { 308 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 309 return adev->gfx.config.gb_addr_config; 310 return RREG32(reg_offset); 311 } 312 } 313 314 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, 315 u32 sh_num, u32 reg_offset, u32 *value) 316 { 317 uint32_t i; 318 struct soc15_allowed_register_entry *en; 319 320 *value = 0; 321 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { 322 en = &soc21_allowed_read_registers[i]; 323 if (!adev->reg_offset[en->hwip][en->inst]) 324 continue; 325 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 326 + en->reg_offset)) 327 continue; 328 329 *value = soc21_get_register_value(adev, 330 soc21_allowed_read_registers[i].grbm_indexed, 331 se_num, sh_num, reg_offset); 332 return 0; 333 } 334 return -EINVAL; 335 } 336 337 #if 0 338 static int soc21_asic_mode1_reset(struct amdgpu_device *adev) 339 { 340 u32 i; 341 int ret = 0; 342 343 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 344 345 /* disable BM */ 346 pci_clear_master(adev->pdev); 347 348 amdgpu_device_cache_pci_state(adev->pdev); 349 350 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 351 dev_info(adev->dev, "GPU smu mode1 reset\n"); 352 ret = amdgpu_dpm_mode1_reset(adev); 353 } else { 354 dev_info(adev->dev, "GPU psp mode1 reset\n"); 355 ret = psp_gpu_reset(adev); 356 } 357 358 if (ret) 359 dev_err(adev->dev, "GPU mode1 reset failed\n"); 360 amdgpu_device_load_pci_state(adev->pdev); 361 362 /* wait for asic to come out of reset */ 363 for (i = 0; i < adev->usec_timeout; i++) { 364 u32 memsize = adev->nbio.funcs->get_memsize(adev); 365 366 if (memsize != 0xffffffff) 367 break; 368 udelay(1); 369 } 370 371 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 372 373 return ret; 374 } 375 #endif 376 377 static enum amd_reset_method 378 soc21_asic_reset_method(struct amdgpu_device *adev) 379 { 380 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 381 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 382 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 383 return amdgpu_reset_method; 384 385 if (amdgpu_reset_method != -1) 386 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 387 amdgpu_reset_method); 388 389 switch (adev->ip_versions[MP1_HWIP][0]) { 390 case IP_VERSION(13, 0, 0): 391 case IP_VERSION(13, 0, 7): 392 case IP_VERSION(13, 0, 10): 393 return AMD_RESET_METHOD_MODE1; 394 case IP_VERSION(13, 0, 4): 395 case IP_VERSION(13, 0, 11): 396 return AMD_RESET_METHOD_MODE2; 397 default: 398 if (amdgpu_dpm_is_baco_supported(adev)) 399 return AMD_RESET_METHOD_BACO; 400 else 401 return AMD_RESET_METHOD_MODE1; 402 } 403 } 404 405 static int soc21_asic_reset(struct amdgpu_device *adev) 406 { 407 int ret = 0; 408 409 switch (soc21_asic_reset_method(adev)) { 410 case AMD_RESET_METHOD_PCI: 411 dev_info(adev->dev, "PCI reset\n"); 412 ret = amdgpu_device_pci_reset(adev); 413 break; 414 case AMD_RESET_METHOD_BACO: 415 dev_info(adev->dev, "BACO reset\n"); 416 ret = amdgpu_dpm_baco_reset(adev); 417 break; 418 case AMD_RESET_METHOD_MODE2: 419 dev_info(adev->dev, "MODE2 reset\n"); 420 ret = amdgpu_dpm_mode2_reset(adev); 421 break; 422 default: 423 dev_info(adev->dev, "MODE1 reset\n"); 424 ret = amdgpu_device_mode1_reset(adev); 425 break; 426 } 427 428 return ret; 429 } 430 431 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 432 { 433 /* todo */ 434 return 0; 435 } 436 437 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 438 { 439 /* todo */ 440 return 0; 441 } 442 443 static void soc21_program_aspm(struct amdgpu_device *adev) 444 { 445 if (!amdgpu_device_should_use_aspm(adev)) 446 return; 447 448 if (!(adev->flags & AMD_IS_APU) && 449 (adev->nbio.funcs->program_aspm)) 450 adev->nbio.funcs->program_aspm(adev); 451 } 452 453 static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev, 454 bool enable) 455 { 456 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 457 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 458 } 459 460 const struct amdgpu_ip_block_version soc21_common_ip_block = 461 { 462 .type = AMD_IP_BLOCK_TYPE_COMMON, 463 .major = 1, 464 .minor = 0, 465 .rev = 0, 466 .funcs = &soc21_common_ip_funcs, 467 }; 468 469 static bool soc21_need_full_reset(struct amdgpu_device *adev) 470 { 471 switch (adev->ip_versions[GC_HWIP][0]) { 472 case IP_VERSION(11, 0, 0): 473 return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC); 474 case IP_VERSION(11, 0, 2): 475 case IP_VERSION(11, 0, 3): 476 return false; 477 default: 478 return true; 479 } 480 } 481 482 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) 483 { 484 u32 sol_reg; 485 486 if (adev->flags & AMD_IS_APU) 487 return false; 488 489 /* Check sOS sign of life register to confirm sys driver and sOS 490 * are already been loaded. 491 */ 492 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 493 if (sol_reg) 494 return true; 495 496 return false; 497 } 498 499 static uint64_t soc21_get_pcie_replay_count(struct amdgpu_device *adev) 500 { 501 502 /* TODO 503 * dummy implement for pcie_replay_count sysfs interface 504 * */ 505 506 return 0; 507 } 508 509 static void soc21_init_doorbell_index(struct amdgpu_device *adev) 510 { 511 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 512 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 513 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 514 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 515 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 516 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 517 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 518 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 519 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 520 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 521 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 522 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 523 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 524 adev->doorbell_index.gfx_userqueue_start = 525 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 526 adev->doorbell_index.gfx_userqueue_end = 527 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 528 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 529 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 530 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 531 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 532 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 533 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 534 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 535 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 536 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 537 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 538 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 539 540 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 541 adev->doorbell_index.sdma_doorbell_range = 20; 542 } 543 544 static void soc21_pre_asic_init(struct amdgpu_device *adev) 545 { 546 } 547 548 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, 549 bool enter) 550 { 551 if (enter) 552 amdgpu_gfx_rlc_enter_safe_mode(adev); 553 else 554 amdgpu_gfx_rlc_exit_safe_mode(adev); 555 556 if (adev->gfx.funcs->update_perfmon_mgcg) 557 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 558 559 return 0; 560 } 561 562 static const struct amdgpu_asic_funcs soc21_asic_funcs = 563 { 564 .read_disabled_bios = &soc21_read_disabled_bios, 565 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 566 .read_register = &soc21_read_register, 567 .reset = &soc21_asic_reset, 568 .reset_method = &soc21_asic_reset_method, 569 .set_vga_state = &soc21_vga_set_state, 570 .get_xclk = &soc21_get_xclk, 571 .set_uvd_clocks = &soc21_set_uvd_clocks, 572 .set_vce_clocks = &soc21_set_vce_clocks, 573 .get_config_memsize = &soc21_get_config_memsize, 574 .init_doorbell_index = &soc21_init_doorbell_index, 575 .need_full_reset = &soc21_need_full_reset, 576 .need_reset_on_init = &soc21_need_reset_on_init, 577 .get_pcie_replay_count = &soc21_get_pcie_replay_count, 578 .supports_baco = &amdgpu_dpm_is_baco_supported, 579 .pre_asic_init = &soc21_pre_asic_init, 580 .query_video_codecs = &soc21_query_video_codecs, 581 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, 582 }; 583 584 static int soc21_common_early_init(void *handle) 585 { 586 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 587 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 588 589 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 590 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 591 adev->smc_rreg = NULL; 592 adev->smc_wreg = NULL; 593 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 594 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 595 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 596 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 597 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 598 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 599 600 /* TODO: will add them during VCN v2 implementation */ 601 adev->uvd_ctx_rreg = NULL; 602 adev->uvd_ctx_wreg = NULL; 603 604 adev->didt_rreg = &soc21_didt_rreg; 605 adev->didt_wreg = &soc21_didt_wreg; 606 607 adev->asic_funcs = &soc21_asic_funcs; 608 609 adev->rev_id = amdgpu_device_get_rev_id(adev); 610 adev->external_rev_id = 0xff; 611 switch (adev->ip_versions[GC_HWIP][0]) { 612 case IP_VERSION(11, 0, 0): 613 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 614 AMD_CG_SUPPORT_GFX_CGLS | 615 #if 0 616 AMD_CG_SUPPORT_GFX_3D_CGCG | 617 AMD_CG_SUPPORT_GFX_3D_CGLS | 618 #endif 619 AMD_CG_SUPPORT_GFX_MGCG | 620 AMD_CG_SUPPORT_REPEATER_FGCG | 621 AMD_CG_SUPPORT_GFX_FGCG | 622 AMD_CG_SUPPORT_GFX_PERF_CLK | 623 AMD_CG_SUPPORT_VCN_MGCG | 624 AMD_CG_SUPPORT_JPEG_MGCG | 625 AMD_CG_SUPPORT_ATHUB_MGCG | 626 AMD_CG_SUPPORT_ATHUB_LS | 627 AMD_CG_SUPPORT_MC_MGCG | 628 AMD_CG_SUPPORT_MC_LS | 629 AMD_CG_SUPPORT_IH_CG | 630 AMD_CG_SUPPORT_HDP_SD; 631 adev->pg_flags = AMD_PG_SUPPORT_VCN | 632 AMD_PG_SUPPORT_VCN_DPG | 633 AMD_PG_SUPPORT_JPEG | 634 AMD_PG_SUPPORT_ATHUB | 635 AMD_PG_SUPPORT_MMHUB; 636 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update 637 break; 638 case IP_VERSION(11, 0, 2): 639 adev->cg_flags = 640 AMD_CG_SUPPORT_GFX_CGCG | 641 AMD_CG_SUPPORT_GFX_CGLS | 642 AMD_CG_SUPPORT_REPEATER_FGCG | 643 AMD_CG_SUPPORT_VCN_MGCG | 644 AMD_CG_SUPPORT_JPEG_MGCG | 645 AMD_CG_SUPPORT_ATHUB_MGCG | 646 AMD_CG_SUPPORT_ATHUB_LS | 647 AMD_CG_SUPPORT_IH_CG | 648 AMD_CG_SUPPORT_HDP_SD; 649 adev->pg_flags = 650 AMD_PG_SUPPORT_VCN | 651 AMD_PG_SUPPORT_VCN_DPG | 652 AMD_PG_SUPPORT_JPEG | 653 AMD_PG_SUPPORT_ATHUB | 654 AMD_PG_SUPPORT_MMHUB; 655 adev->external_rev_id = adev->rev_id + 0x10; 656 break; 657 case IP_VERSION(11, 0, 1): 658 adev->cg_flags = 659 AMD_CG_SUPPORT_GFX_CGCG | 660 AMD_CG_SUPPORT_GFX_CGLS | 661 AMD_CG_SUPPORT_GFX_MGCG | 662 AMD_CG_SUPPORT_GFX_FGCG | 663 AMD_CG_SUPPORT_REPEATER_FGCG | 664 AMD_CG_SUPPORT_GFX_PERF_CLK | 665 AMD_CG_SUPPORT_MC_MGCG | 666 AMD_CG_SUPPORT_MC_LS | 667 AMD_CG_SUPPORT_HDP_MGCG | 668 AMD_CG_SUPPORT_HDP_LS | 669 AMD_CG_SUPPORT_ATHUB_MGCG | 670 AMD_CG_SUPPORT_ATHUB_LS | 671 AMD_CG_SUPPORT_IH_CG | 672 AMD_CG_SUPPORT_BIF_MGCG | 673 AMD_CG_SUPPORT_BIF_LS | 674 AMD_CG_SUPPORT_VCN_MGCG | 675 AMD_CG_SUPPORT_JPEG_MGCG; 676 adev->pg_flags = 677 AMD_PG_SUPPORT_GFX_PG | 678 AMD_PG_SUPPORT_VCN | 679 AMD_PG_SUPPORT_VCN_DPG | 680 AMD_PG_SUPPORT_JPEG; 681 adev->external_rev_id = adev->rev_id + 0x1; 682 break; 683 case IP_VERSION(11, 0, 3): 684 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 685 AMD_CG_SUPPORT_JPEG_MGCG | 686 AMD_CG_SUPPORT_GFX_CGCG | 687 AMD_CG_SUPPORT_GFX_CGLS | 688 AMD_CG_SUPPORT_REPEATER_FGCG | 689 AMD_CG_SUPPORT_GFX_MGCG | 690 AMD_CG_SUPPORT_HDP_SD | 691 AMD_CG_SUPPORT_ATHUB_MGCG | 692 AMD_CG_SUPPORT_ATHUB_LS; 693 adev->pg_flags = AMD_PG_SUPPORT_VCN | 694 AMD_PG_SUPPORT_VCN_DPG | 695 AMD_PG_SUPPORT_JPEG; 696 adev->external_rev_id = adev->rev_id + 0x20; 697 break; 698 case IP_VERSION(11, 0, 4): 699 adev->cg_flags = 700 AMD_CG_SUPPORT_GFX_CGCG | 701 AMD_CG_SUPPORT_GFX_CGLS | 702 AMD_CG_SUPPORT_GFX_MGCG | 703 AMD_CG_SUPPORT_GFX_FGCG | 704 AMD_CG_SUPPORT_REPEATER_FGCG | 705 AMD_CG_SUPPORT_GFX_PERF_CLK | 706 AMD_CG_SUPPORT_MC_MGCG | 707 AMD_CG_SUPPORT_MC_LS | 708 AMD_CG_SUPPORT_HDP_MGCG | 709 AMD_CG_SUPPORT_HDP_LS | 710 AMD_CG_SUPPORT_ATHUB_MGCG | 711 AMD_CG_SUPPORT_ATHUB_LS | 712 AMD_CG_SUPPORT_IH_CG | 713 AMD_CG_SUPPORT_BIF_MGCG | 714 AMD_CG_SUPPORT_BIF_LS | 715 AMD_CG_SUPPORT_VCN_MGCG | 716 AMD_CG_SUPPORT_JPEG_MGCG; 717 adev->pg_flags = AMD_PG_SUPPORT_VCN | 718 AMD_PG_SUPPORT_VCN_DPG | 719 AMD_PG_SUPPORT_GFX_PG | 720 AMD_PG_SUPPORT_JPEG; 721 adev->external_rev_id = adev->rev_id + 0x1; 722 break; 723 724 default: 725 /* FIXME: not supported yet */ 726 return -EINVAL; 727 } 728 729 if (amdgpu_sriov_vf(adev)) { 730 amdgpu_virt_init_setting(adev); 731 xgpu_nv_mailbox_set_irq_funcs(adev); 732 } 733 734 return 0; 735 } 736 737 static int soc21_common_late_init(void *handle) 738 { 739 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 740 741 if (amdgpu_sriov_vf(adev)) { 742 xgpu_nv_mailbox_get_irq(adev); 743 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 744 !amdgpu_sriov_is_av1_support(adev)) { 745 amdgpu_virt_update_sriov_video_codec(adev, 746 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 747 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 748 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 749 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1)); 750 } else { 751 amdgpu_virt_update_sriov_video_codec(adev, 752 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 753 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 754 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 755 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0)); 756 } 757 } else { 758 if (adev->nbio.ras && 759 adev->nbio.ras_err_event_athub_irq.funcs) 760 /* don't need to fail gpu late init 761 * if enabling athub_err_event interrupt failed 762 * nbio v4_3 only support fatal error hanlding 763 * just enable the interrupt directly */ 764 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); 765 } 766 767 return 0; 768 } 769 770 static int soc21_common_sw_init(void *handle) 771 { 772 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 773 774 if (amdgpu_sriov_vf(adev)) 775 xgpu_nv_mailbox_add_irq_id(adev); 776 777 return 0; 778 } 779 780 static int soc21_common_sw_fini(void *handle) 781 { 782 return 0; 783 } 784 785 static int soc21_common_hw_init(void *handle) 786 { 787 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 788 789 /* enable aspm */ 790 soc21_program_aspm(adev); 791 /* setup nbio registers */ 792 adev->nbio.funcs->init_registers(adev); 793 /* remap HDP registers to a hole in mmio space, 794 * for the purpose of expose those registers 795 * to process space 796 */ 797 if (adev->nbio.funcs->remap_hdp_registers) 798 adev->nbio.funcs->remap_hdp_registers(adev); 799 /* enable the doorbell aperture */ 800 soc21_enable_doorbell_aperture(adev, true); 801 802 return 0; 803 } 804 805 static int soc21_common_hw_fini(void *handle) 806 { 807 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 808 809 /* disable the doorbell aperture */ 810 soc21_enable_doorbell_aperture(adev, false); 811 812 if (amdgpu_sriov_vf(adev)) { 813 xgpu_nv_mailbox_put_irq(adev); 814 } else { 815 if (adev->nbio.ras && 816 adev->nbio.ras_err_event_athub_irq.funcs) 817 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 818 } 819 820 return 0; 821 } 822 823 static int soc21_common_suspend(void *handle) 824 { 825 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 826 827 return soc21_common_hw_fini(adev); 828 } 829 830 static int soc21_common_resume(void *handle) 831 { 832 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 833 834 return soc21_common_hw_init(adev); 835 } 836 837 static bool soc21_common_is_idle(void *handle) 838 { 839 return true; 840 } 841 842 static int soc21_common_wait_for_idle(void *handle) 843 { 844 return 0; 845 } 846 847 static int soc21_common_soft_reset(void *handle) 848 { 849 return 0; 850 } 851 852 static int soc21_common_set_clockgating_state(void *handle, 853 enum amd_clockgating_state state) 854 { 855 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 856 857 switch (adev->ip_versions[NBIO_HWIP][0]) { 858 case IP_VERSION(4, 3, 0): 859 case IP_VERSION(4, 3, 1): 860 case IP_VERSION(7, 7, 0): 861 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 862 state == AMD_CG_STATE_GATE); 863 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 864 state == AMD_CG_STATE_GATE); 865 adev->hdp.funcs->update_clock_gating(adev, 866 state == AMD_CG_STATE_GATE); 867 break; 868 default: 869 break; 870 } 871 return 0; 872 } 873 874 static int soc21_common_set_powergating_state(void *handle, 875 enum amd_powergating_state state) 876 { 877 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 878 879 switch (adev->ip_versions[LSDMA_HWIP][0]) { 880 case IP_VERSION(6, 0, 0): 881 case IP_VERSION(6, 0, 2): 882 adev->lsdma.funcs->update_memory_power_gating(adev, 883 state == AMD_PG_STATE_GATE); 884 break; 885 default: 886 break; 887 } 888 889 return 0; 890 } 891 892 static void soc21_common_get_clockgating_state(void *handle, u64 *flags) 893 { 894 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 895 896 adev->nbio.funcs->get_clockgating_state(adev, flags); 897 898 adev->hdp.funcs->get_clock_gating_state(adev, flags); 899 900 return; 901 } 902 903 static const struct amd_ip_funcs soc21_common_ip_funcs = { 904 .name = "soc21_common", 905 .early_init = soc21_common_early_init, 906 .late_init = soc21_common_late_init, 907 .sw_init = soc21_common_sw_init, 908 .sw_fini = soc21_common_sw_fini, 909 .hw_init = soc21_common_hw_init, 910 .hw_fini = soc21_common_hw_fini, 911 .suspend = soc21_common_suspend, 912 .resume = soc21_common_resume, 913 .is_idle = soc21_common_is_idle, 914 .wait_for_idle = soc21_common_wait_for_idle, 915 .soft_reset = soc21_common_soft_reset, 916 .set_clockgating_state = soc21_common_set_clockgating_state, 917 .set_powergating_state = soc21_common_set_powergating_state, 918 .get_clockgating_state = soc21_common_get_clockgating_state, 919 }; 920