1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_11_0_0_offset.h" 40 #include "gc/gc_11_0_0_sh_mask.h" 41 #include "mp/mp_13_0_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15_common.h" 45 #include "soc21.h" 46 47 static const struct amd_ip_funcs soc21_common_ip_funcs; 48 49 /* SOC21 */ 50 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array[] = 51 { 52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 54 }; 55 56 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode = 57 { 58 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array), 59 .codec_array = vcn_4_0_0_video_codecs_encode_array, 60 }; 61 62 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array[] = 63 { 64 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 65 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 66 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 67 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 68 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 69 }; 70 71 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode = 72 { 73 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array), 74 .codec_array = vcn_4_0_0_video_codecs_decode_array, 75 }; 76 77 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, 78 const struct amdgpu_video_codecs **codecs) 79 { 80 switch (adev->ip_versions[UVD_HWIP][0]) { 81 82 case IP_VERSION(4, 0, 0): 83 if (encode) 84 *codecs = &vcn_4_0_0_video_codecs_encode; 85 else 86 *codecs = &vcn_4_0_0_video_codecs_decode; 87 return 0; 88 default: 89 return -EINVAL; 90 } 91 } 92 /* 93 * Indirect registers accessor 94 */ 95 static u32 soc21_pcie_rreg(struct amdgpu_device *adev, u32 reg) 96 { 97 unsigned long address, data; 98 address = adev->nbio.funcs->get_pcie_index_offset(adev); 99 data = adev->nbio.funcs->get_pcie_data_offset(adev); 100 101 return amdgpu_device_indirect_rreg(adev, address, data, reg); 102 } 103 104 static void soc21_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 105 { 106 unsigned long address, data; 107 108 address = adev->nbio.funcs->get_pcie_index_offset(adev); 109 data = adev->nbio.funcs->get_pcie_data_offset(adev); 110 111 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 112 } 113 114 static u64 soc21_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 115 { 116 unsigned long address, data; 117 address = adev->nbio.funcs->get_pcie_index_offset(adev); 118 data = adev->nbio.funcs->get_pcie_data_offset(adev); 119 120 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 121 } 122 123 static void soc21_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 124 { 125 unsigned long address, data; 126 127 address = adev->nbio.funcs->get_pcie_index_offset(adev); 128 data = adev->nbio.funcs->get_pcie_data_offset(adev); 129 130 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 131 } 132 133 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) 134 { 135 unsigned long flags, address, data; 136 u32 r; 137 138 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 139 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 140 141 spin_lock_irqsave(&adev->didt_idx_lock, flags); 142 WREG32(address, (reg)); 143 r = RREG32(data); 144 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 145 return r; 146 } 147 148 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 149 { 150 unsigned long flags, address, data; 151 152 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 153 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 154 155 spin_lock_irqsave(&adev->didt_idx_lock, flags); 156 WREG32(address, (reg)); 157 WREG32(data, (v)); 158 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 159 } 160 161 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) 162 { 163 return adev->nbio.funcs->get_memsize(adev); 164 } 165 166 static u32 soc21_get_xclk(struct amdgpu_device *adev) 167 { 168 return adev->clock.spll.reference_freq; 169 } 170 171 172 void soc21_grbm_select(struct amdgpu_device *adev, 173 u32 me, u32 pipe, u32 queue, u32 vmid) 174 { 175 u32 grbm_gfx_cntl = 0; 176 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 177 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 178 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 179 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 180 181 WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL), grbm_gfx_cntl); 182 } 183 184 static void soc21_vga_set_state(struct amdgpu_device *adev, bool state) 185 { 186 /* todo */ 187 } 188 189 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) 190 { 191 /* todo */ 192 return false; 193 } 194 195 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { 196 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, 197 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, 198 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, 199 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, 200 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, 201 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, 202 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, 203 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, 204 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, 205 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, 206 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, 207 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, 208 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, 209 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, 210 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, 211 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, 212 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, 213 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, 214 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, 215 }; 216 217 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 218 u32 sh_num, u32 reg_offset) 219 { 220 uint32_t val; 221 222 mutex_lock(&adev->grbm_idx_mutex); 223 if (se_num != 0xffffffff || sh_num != 0xffffffff) 224 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 225 226 val = RREG32(reg_offset); 227 228 if (se_num != 0xffffffff || sh_num != 0xffffffff) 229 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 230 mutex_unlock(&adev->grbm_idx_mutex); 231 return val; 232 } 233 234 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, 235 bool indexed, u32 se_num, 236 u32 sh_num, u32 reg_offset) 237 { 238 if (indexed) { 239 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); 240 } else { 241 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 242 return adev->gfx.config.gb_addr_config; 243 return RREG32(reg_offset); 244 } 245 } 246 247 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, 248 u32 sh_num, u32 reg_offset, u32 *value) 249 { 250 uint32_t i; 251 struct soc15_allowed_register_entry *en; 252 253 *value = 0; 254 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { 255 en = &soc21_allowed_read_registers[i]; 256 if (adev->reg_offset[en->hwip][en->inst] && 257 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 258 + en->reg_offset)) 259 continue; 260 261 *value = soc21_get_register_value(adev, 262 soc21_allowed_read_registers[i].grbm_indexed, 263 se_num, sh_num, reg_offset); 264 return 0; 265 } 266 return -EINVAL; 267 } 268 269 #if 0 270 static int soc21_asic_mode1_reset(struct amdgpu_device *adev) 271 { 272 u32 i; 273 int ret = 0; 274 275 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 276 277 /* disable BM */ 278 pci_clear_master(adev->pdev); 279 280 amdgpu_device_cache_pci_state(adev->pdev); 281 282 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 283 dev_info(adev->dev, "GPU smu mode1 reset\n"); 284 ret = amdgpu_dpm_mode1_reset(adev); 285 } else { 286 dev_info(adev->dev, "GPU psp mode1 reset\n"); 287 ret = psp_gpu_reset(adev); 288 } 289 290 if (ret) 291 dev_err(adev->dev, "GPU mode1 reset failed\n"); 292 amdgpu_device_load_pci_state(adev->pdev); 293 294 /* wait for asic to come out of reset */ 295 for (i = 0; i < adev->usec_timeout; i++) { 296 u32 memsize = adev->nbio.funcs->get_memsize(adev); 297 298 if (memsize != 0xffffffff) 299 break; 300 udelay(1); 301 } 302 303 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 304 305 return ret; 306 } 307 #endif 308 309 static enum amd_reset_method 310 soc21_asic_reset_method(struct amdgpu_device *adev) 311 { 312 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 313 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 314 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 315 return amdgpu_reset_method; 316 317 if (amdgpu_reset_method != -1) 318 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 319 amdgpu_reset_method); 320 321 switch (adev->ip_versions[MP1_HWIP][0]) { 322 case IP_VERSION(13, 0, 0): 323 return AMD_RESET_METHOD_MODE1; 324 case IP_VERSION(13, 0, 4): 325 return AMD_RESET_METHOD_MODE2; 326 default: 327 if (amdgpu_dpm_is_baco_supported(adev)) 328 return AMD_RESET_METHOD_BACO; 329 else 330 return AMD_RESET_METHOD_MODE1; 331 } 332 } 333 334 static int soc21_asic_reset(struct amdgpu_device *adev) 335 { 336 int ret = 0; 337 338 switch (soc21_asic_reset_method(adev)) { 339 case AMD_RESET_METHOD_PCI: 340 dev_info(adev->dev, "PCI reset\n"); 341 ret = amdgpu_device_pci_reset(adev); 342 break; 343 case AMD_RESET_METHOD_BACO: 344 dev_info(adev->dev, "BACO reset\n"); 345 ret = amdgpu_dpm_baco_reset(adev); 346 break; 347 case AMD_RESET_METHOD_MODE2: 348 dev_info(adev->dev, "MODE2 reset\n"); 349 ret = amdgpu_dpm_mode2_reset(adev); 350 break; 351 default: 352 dev_info(adev->dev, "MODE1 reset\n"); 353 ret = amdgpu_device_mode1_reset(adev); 354 break; 355 } 356 357 return ret; 358 } 359 360 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 361 { 362 /* todo */ 363 return 0; 364 } 365 366 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 367 { 368 /* todo */ 369 return 0; 370 } 371 372 static void soc21_pcie_gen3_enable(struct amdgpu_device *adev) 373 { 374 if (pci_is_root_bus(adev->pdev->bus)) 375 return; 376 377 if (amdgpu_pcie_gen2 == 0) 378 return; 379 380 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 381 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 382 return; 383 384 /* todo */ 385 } 386 387 static void soc21_program_aspm(struct amdgpu_device *adev) 388 { 389 if (!amdgpu_device_should_use_aspm(adev)) 390 return; 391 392 if (!(adev->flags & AMD_IS_APU) && 393 (adev->nbio.funcs->program_aspm)) 394 adev->nbio.funcs->program_aspm(adev); 395 } 396 397 static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev, 398 bool enable) 399 { 400 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 401 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 402 } 403 404 const struct amdgpu_ip_block_version soc21_common_ip_block = 405 { 406 .type = AMD_IP_BLOCK_TYPE_COMMON, 407 .major = 1, 408 .minor = 0, 409 .rev = 0, 410 .funcs = &soc21_common_ip_funcs, 411 }; 412 413 static uint32_t soc21_get_rev_id(struct amdgpu_device *adev) 414 { 415 return adev->nbio.funcs->get_rev_id(adev); 416 } 417 418 static bool soc21_need_full_reset(struct amdgpu_device *adev) 419 { 420 return true; 421 } 422 423 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) 424 { 425 u32 sol_reg; 426 427 if (adev->flags & AMD_IS_APU) 428 return false; 429 430 /* Check sOS sign of life register to confirm sys driver and sOS 431 * are already been loaded. 432 */ 433 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 434 if (sol_reg) 435 return true; 436 437 return false; 438 } 439 440 static uint64_t soc21_get_pcie_replay_count(struct amdgpu_device *adev) 441 { 442 443 /* TODO 444 * dummy implement for pcie_replay_count sysfs interface 445 * */ 446 447 return 0; 448 } 449 450 static void soc21_init_doorbell_index(struct amdgpu_device *adev) 451 { 452 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 453 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 454 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 455 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 456 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 457 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 458 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 459 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 460 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 461 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 462 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 463 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 464 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 465 adev->doorbell_index.gfx_userqueue_start = 466 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 467 adev->doorbell_index.gfx_userqueue_end = 468 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 469 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 470 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 471 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 472 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 473 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 474 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 475 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 476 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 477 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 478 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 479 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 480 481 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 482 adev->doorbell_index.sdma_doorbell_range = 20; 483 } 484 485 static void soc21_pre_asic_init(struct amdgpu_device *adev) 486 { 487 } 488 489 static const struct amdgpu_asic_funcs soc21_asic_funcs = 490 { 491 .read_disabled_bios = &soc21_read_disabled_bios, 492 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 493 .read_register = &soc21_read_register, 494 .reset = &soc21_asic_reset, 495 .reset_method = &soc21_asic_reset_method, 496 .set_vga_state = &soc21_vga_set_state, 497 .get_xclk = &soc21_get_xclk, 498 .set_uvd_clocks = &soc21_set_uvd_clocks, 499 .set_vce_clocks = &soc21_set_vce_clocks, 500 .get_config_memsize = &soc21_get_config_memsize, 501 .init_doorbell_index = &soc21_init_doorbell_index, 502 .need_full_reset = &soc21_need_full_reset, 503 .need_reset_on_init = &soc21_need_reset_on_init, 504 .get_pcie_replay_count = &soc21_get_pcie_replay_count, 505 .supports_baco = &amdgpu_dpm_is_baco_supported, 506 .pre_asic_init = &soc21_pre_asic_init, 507 .query_video_codecs = &soc21_query_video_codecs, 508 }; 509 510 static int soc21_common_early_init(void *handle) 511 { 512 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 513 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 514 515 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 516 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 517 adev->smc_rreg = NULL; 518 adev->smc_wreg = NULL; 519 adev->pcie_rreg = &soc21_pcie_rreg; 520 adev->pcie_wreg = &soc21_pcie_wreg; 521 adev->pcie_rreg64 = &soc21_pcie_rreg64; 522 adev->pcie_wreg64 = &soc21_pcie_wreg64; 523 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 524 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 525 526 /* TODO: will add them during VCN v2 implementation */ 527 adev->uvd_ctx_rreg = NULL; 528 adev->uvd_ctx_wreg = NULL; 529 530 adev->didt_rreg = &soc21_didt_rreg; 531 adev->didt_wreg = &soc21_didt_wreg; 532 533 adev->asic_funcs = &soc21_asic_funcs; 534 535 adev->rev_id = soc21_get_rev_id(adev); 536 adev->external_rev_id = 0xff; 537 switch (adev->ip_versions[GC_HWIP][0]) { 538 case IP_VERSION(11, 0, 0): 539 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 540 AMD_CG_SUPPORT_GFX_CGLS | 541 AMD_CG_SUPPORT_GFX_3D_CGCG | 542 AMD_CG_SUPPORT_GFX_3D_CGLS | 543 AMD_CG_SUPPORT_GFX_MGCG | 544 AMD_CG_SUPPORT_REPEATER_FGCG | 545 AMD_CG_SUPPORT_GFX_FGCG | 546 AMD_CG_SUPPORT_GFX_PERF_CLK | 547 AMD_CG_SUPPORT_VCN_MGCG | 548 AMD_CG_SUPPORT_JPEG_MGCG | 549 AMD_CG_SUPPORT_ATHUB_MGCG | 550 AMD_CG_SUPPORT_ATHUB_LS | 551 AMD_CG_SUPPORT_MC_MGCG | 552 AMD_CG_SUPPORT_MC_LS | 553 AMD_CG_SUPPORT_IH_CG | 554 AMD_CG_SUPPORT_HDP_SD; 555 adev->pg_flags = AMD_PG_SUPPORT_VCN | 556 AMD_PG_SUPPORT_VCN_DPG | 557 AMD_PG_SUPPORT_JPEG | 558 AMD_PG_SUPPORT_ATHUB | 559 AMD_PG_SUPPORT_MMHUB; 560 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update 561 break; 562 case IP_VERSION(11, 0, 2): 563 adev->cg_flags = 564 AMD_CG_SUPPORT_GFX_CGCG | 565 AMD_CG_SUPPORT_GFX_CGLS | 566 AMD_CG_SUPPORT_REPEATER_FGCG | 567 AMD_CG_SUPPORT_VCN_MGCG | 568 AMD_CG_SUPPORT_JPEG_MGCG | 569 AMD_CG_SUPPORT_ATHUB_MGCG | 570 AMD_CG_SUPPORT_ATHUB_LS; 571 adev->pg_flags = 572 AMD_PG_SUPPORT_VCN | 573 AMD_PG_SUPPORT_VCN_DPG | 574 AMD_PG_SUPPORT_JPEG | 575 AMD_PG_SUPPORT_ATHUB | 576 AMD_PG_SUPPORT_MMHUB; 577 adev->external_rev_id = adev->rev_id + 0x10; 578 break; 579 case IP_VERSION(11, 0, 1): 580 adev->cg_flags = 0; 581 adev->pg_flags = 0; 582 adev->external_rev_id = adev->rev_id + 0x1; 583 break; 584 default: 585 /* FIXME: not supported yet */ 586 return -EINVAL; 587 } 588 589 return 0; 590 } 591 592 static int soc21_common_late_init(void *handle) 593 { 594 return 0; 595 } 596 597 static int soc21_common_sw_init(void *handle) 598 { 599 return 0; 600 } 601 602 static int soc21_common_sw_fini(void *handle) 603 { 604 return 0; 605 } 606 607 static int soc21_common_hw_init(void *handle) 608 { 609 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 610 611 /* enable pcie gen2/3 link */ 612 soc21_pcie_gen3_enable(adev); 613 /* enable aspm */ 614 soc21_program_aspm(adev); 615 /* setup nbio registers */ 616 adev->nbio.funcs->init_registers(adev); 617 /* remap HDP registers to a hole in mmio space, 618 * for the purpose of expose those registers 619 * to process space 620 */ 621 if (adev->nbio.funcs->remap_hdp_registers) 622 adev->nbio.funcs->remap_hdp_registers(adev); 623 /* enable the doorbell aperture */ 624 soc21_enable_doorbell_aperture(adev, true); 625 626 return 0; 627 } 628 629 static int soc21_common_hw_fini(void *handle) 630 { 631 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 632 633 /* disable the doorbell aperture */ 634 soc21_enable_doorbell_aperture(adev, false); 635 636 return 0; 637 } 638 639 static int soc21_common_suspend(void *handle) 640 { 641 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 642 643 return soc21_common_hw_fini(adev); 644 } 645 646 static int soc21_common_resume(void *handle) 647 { 648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 649 650 return soc21_common_hw_init(adev); 651 } 652 653 static bool soc21_common_is_idle(void *handle) 654 { 655 return true; 656 } 657 658 static int soc21_common_wait_for_idle(void *handle) 659 { 660 return 0; 661 } 662 663 static int soc21_common_soft_reset(void *handle) 664 { 665 return 0; 666 } 667 668 static int soc21_common_set_clockgating_state(void *handle, 669 enum amd_clockgating_state state) 670 { 671 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 672 673 switch (adev->ip_versions[NBIO_HWIP][0]) { 674 case IP_VERSION(4, 3, 0): 675 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 676 state == AMD_CG_STATE_GATE); 677 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 678 state == AMD_CG_STATE_GATE); 679 adev->hdp.funcs->update_clock_gating(adev, 680 state == AMD_CG_STATE_GATE); 681 break; 682 default: 683 break; 684 } 685 return 0; 686 } 687 688 static int soc21_common_set_powergating_state(void *handle, 689 enum amd_powergating_state state) 690 { 691 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 692 693 switch (adev->ip_versions[LSDMA_HWIP][0]) { 694 case IP_VERSION(6, 0, 0): 695 case IP_VERSION(6, 0, 2): 696 adev->lsdma.funcs->update_memory_power_gating(adev, 697 state == AMD_PG_STATE_GATE); 698 break; 699 default: 700 break; 701 } 702 703 return 0; 704 } 705 706 static void soc21_common_get_clockgating_state(void *handle, u64 *flags) 707 { 708 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 709 710 adev->nbio.funcs->get_clockgating_state(adev, flags); 711 712 adev->hdp.funcs->get_clock_gating_state(adev, flags); 713 714 return; 715 } 716 717 static const struct amd_ip_funcs soc21_common_ip_funcs = { 718 .name = "soc21_common", 719 .early_init = soc21_common_early_init, 720 .late_init = soc21_common_late_init, 721 .sw_init = soc21_common_sw_init, 722 .sw_fini = soc21_common_sw_fini, 723 .hw_init = soc21_common_hw_init, 724 .hw_fini = soc21_common_hw_fini, 725 .suspend = soc21_common_suspend, 726 .resume = soc21_common_resume, 727 .is_idle = soc21_common_is_idle, 728 .wait_for_idle = soc21_common_wait_for_idle, 729 .soft_reset = soc21_common_soft_reset, 730 .set_clockgating_state = soc21_common_set_clockgating_state, 731 .set_powergating_state = soc21_common_set_powergating_state, 732 .get_clockgating_state = soc21_common_get_clockgating_state, 733 }; 734