1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SOC15_H 24 #define SOC15_H 25 26 #define GFX9_NUM_GFX_RINGS 1 27 #define GFX9_NUM_COMPUTE_RINGS 8 28 29 /* 30 * PM4 31 */ 32 #define PACKET_TYPE0 0 33 #define PACKET_TYPE1 1 34 #define PACKET_TYPE2 2 35 #define PACKET_TYPE3 3 36 37 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 38 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 39 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 40 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 41 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 42 ((reg) & 0xFFFF) | \ 43 ((n) & 0x3FFF) << 16) 44 #define CP_PACKET2 0x80000000 45 #define PACKET2_PAD_SHIFT 0 46 #define PACKET2_PAD_MASK (0x3fffffff << 0) 47 48 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 49 50 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 51 (((op) & 0xFF) << 8) | \ 52 ((n) & 0x3FFF) << 16) 53 54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 55 56 /* Packet 3 types */ 57 #define PACKET3_NOP 0x10 58 #define PACKET3_SET_BASE 0x11 59 #define PACKET3_BASE_INDEX(x) ((x) << 0) 60 #define CE_PARTITION_BASE 3 61 #define PACKET3_CLEAR_STATE 0x12 62 #define PACKET3_INDEX_BUFFER_SIZE 0x13 63 #define PACKET3_DISPATCH_DIRECT 0x15 64 #define PACKET3_DISPATCH_INDIRECT 0x16 65 #define PACKET3_ATOMIC_GDS 0x1D 66 #define PACKET3_ATOMIC_MEM 0x1E 67 #define PACKET3_OCCLUSION_QUERY 0x1F 68 #define PACKET3_SET_PREDICATION 0x20 69 #define PACKET3_REG_RMW 0x21 70 #define PACKET3_COND_EXEC 0x22 71 #define PACKET3_PRED_EXEC 0x23 72 #define PACKET3_DRAW_INDIRECT 0x24 73 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 74 #define PACKET3_INDEX_BASE 0x26 75 #define PACKET3_DRAW_INDEX_2 0x27 76 #define PACKET3_CONTEXT_CONTROL 0x28 77 #define PACKET3_INDEX_TYPE 0x2A 78 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 79 #define PACKET3_DRAW_INDEX_AUTO 0x2D 80 #define PACKET3_NUM_INSTANCES 0x2F 81 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 82 #define PACKET3_INDIRECT_BUFFER_CONST 0x33 83 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 84 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 85 #define PACKET3_DRAW_PREAMBLE 0x36 86 #define PACKET3_WRITE_DATA 0x37 87 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 88 /* 0 - register 89 * 1 - memory (sync - via GRBM) 90 * 2 - gl2 91 * 3 - gds 92 * 4 - reserved 93 * 5 - memory (async - direct) 94 */ 95 #define WR_ONE_ADDR (1 << 16) 96 #define WR_CONFIRM (1 << 20) 97 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 98 /* 0 - LRU 99 * 1 - Stream 100 */ 101 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 102 /* 0 - me 103 * 1 - pfp 104 * 2 - ce 105 */ 106 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 107 #define PACKET3_MEM_SEMAPHORE 0x39 108 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 109 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 110 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 111 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 112 #define PACKET3_WAIT_REG_MEM 0x3C 113 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 114 /* 0 - always 115 * 1 - < 116 * 2 - <= 117 * 3 - == 118 * 4 - != 119 * 5 - >= 120 * 6 - > 121 */ 122 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 123 /* 0 - reg 124 * 1 - mem 125 */ 126 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 127 /* 0 - wait_reg_mem 128 * 1 - wr_wait_wr_reg 129 */ 130 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 131 /* 0 - me 132 * 1 - pfp 133 */ 134 #define PACKET3_INDIRECT_BUFFER 0x3F 135 #define INDIRECT_BUFFER_VALID (1 << 23) 136 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 137 /* 0 - LRU 138 * 1 - Stream 139 * 2 - Bypass 140 */ 141 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) 142 #define PACKET3_COPY_DATA 0x40 143 #define PACKET3_PFP_SYNC_ME 0x42 144 #define PACKET3_COND_WRITE 0x45 145 #define PACKET3_EVENT_WRITE 0x46 146 #define EVENT_TYPE(x) ((x) << 0) 147 #define EVENT_INDEX(x) ((x) << 8) 148 /* 0 - any non-TS event 149 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 150 * 2 - SAMPLE_PIPELINESTAT 151 * 3 - SAMPLE_STREAMOUTSTAT* 152 * 4 - *S_PARTIAL_FLUSH 153 */ 154 #define PACKET3_RELEASE_MEM 0x49 155 #define EVENT_TYPE(x) ((x) << 0) 156 #define EVENT_INDEX(x) ((x) << 8) 157 #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 158 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 159 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 160 #define EOP_TCL1_ACTION_EN (1 << 16) 161 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 162 #define EOP_TC_NC_ACTION_EN (1 << 19) 163 #define EOP_TC_MD_ACTION_EN (1 << 21) /* L2 metadata */ 164 165 #define DATA_SEL(x) ((x) << 29) 166 /* 0 - discard 167 * 1 - send low 32bit data 168 * 2 - send 64bit data 169 * 3 - send 64bit GPU counter value 170 * 4 - send 64bit sys counter value 171 */ 172 #define INT_SEL(x) ((x) << 24) 173 /* 0 - none 174 * 1 - interrupt only (DATA_SEL = 0) 175 * 2 - interrupt when data write is confirmed 176 */ 177 #define DST_SEL(x) ((x) << 16) 178 /* 0 - MC 179 * 1 - TC/L2 180 */ 181 182 183 184 #define PACKET3_PREAMBLE_CNTL 0x4A 185 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 186 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 187 #define PACKET3_DMA_DATA 0x50 188 /* 1. header 189 * 2. CONTROL 190 * 3. SRC_ADDR_LO or DATA [31:0] 191 * 4. SRC_ADDR_HI [31:0] 192 * 5. DST_ADDR_LO [31:0] 193 * 6. DST_ADDR_HI [7:0] 194 * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 195 */ 196 /* CONTROL */ 197 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 198 /* 0 - ME 199 * 1 - PFP 200 */ 201 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 202 /* 0 - LRU 203 * 1 - Stream 204 */ 205 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 206 /* 0 - DST_ADDR using DAS 207 * 1 - GDS 208 * 3 - DST_ADDR using L2 209 */ 210 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 211 /* 0 - LRU 212 * 1 - Stream 213 */ 214 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 215 /* 0 - SRC_ADDR using SAS 216 * 1 - GDS 217 * 2 - DATA 218 * 3 - SRC_ADDR using L2 219 */ 220 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 221 /* COMMAND */ 222 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 223 /* 0 - memory 224 * 1 - register 225 */ 226 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 227 /* 0 - memory 228 * 1 - register 229 */ 230 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 231 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 232 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 233 #define PACKET3_AQUIRE_MEM 0x58 234 #define PACKET3_REWIND 0x59 235 #define PACKET3_LOAD_UCONFIG_REG 0x5E 236 #define PACKET3_LOAD_SH_REG 0x5F 237 #define PACKET3_LOAD_CONFIG_REG 0x60 238 #define PACKET3_LOAD_CONTEXT_REG 0x61 239 #define PACKET3_SET_CONFIG_REG 0x68 240 #define PACKET3_SET_CONFIG_REG_START 0x00002000 241 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 242 #define PACKET3_SET_CONTEXT_REG 0x69 243 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 244 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 245 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 246 #define PACKET3_SET_SH_REG 0x76 247 #define PACKET3_SET_SH_REG_START 0x00002c00 248 #define PACKET3_SET_SH_REG_END 0x00003000 249 #define PACKET3_SET_SH_REG_OFFSET 0x77 250 #define PACKET3_SET_QUEUE_REG 0x78 251 #define PACKET3_SET_UCONFIG_REG 0x79 252 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 253 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 254 #define PACKET3_SET_UCONFIG_REG_INDEX_TYPE (2 << 28) 255 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 256 #define PACKET3_SCRATCH_RAM_READ 0x7E 257 #define PACKET3_LOAD_CONST_RAM 0x80 258 #define PACKET3_WRITE_CONST_RAM 0x81 259 #define PACKET3_DUMP_CONST_RAM 0x83 260 #define PACKET3_INCREMENT_CE_COUNTER 0x84 261 #define PACKET3_INCREMENT_DE_COUNTER 0x85 262 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 263 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 264 #define PACKET3_SWITCH_BUFFER 0x8B 265 #define PACKET3_FRAME_CONTROL 0x90 266 # define FRAME_CMD(x) ((x) << 28) 267 /* 268 * x=0: tmz_begin 269 * x=1: tmz_end 270 */ 271 272 #define PACKET3_INVALIDATE_TLBS 0x98 273 # define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) 274 # define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) 275 # define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) 276 # define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29) 277 #define PACKET3_SET_RESOURCES 0xA0 278 /* 1. header 279 * 2. CONTROL 280 * 3. QUEUE_MASK_LO [31:0] 281 * 4. QUEUE_MASK_HI [31:0] 282 * 5. GWS_MASK_LO [31:0] 283 * 6. GWS_MASK_HI [31:0] 284 * 7. OAC_MASK [15:0] 285 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] 286 */ 287 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 288 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 289 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 290 #define PACKET3_MAP_QUEUES 0xA2 291 /* 1. header 292 * 2. CONTROL 293 * 3. CONTROL2 294 * 4. MQD_ADDR_LO [31:0] 295 * 5. MQD_ADDR_HI [31:0] 296 * 6. WPTR_ADDR_LO [31:0] 297 * 7. WPTR_ADDR_HI [31:0] 298 */ 299 /* CONTROL */ 300 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 301 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) 302 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) 303 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) 304 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) 305 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 306 # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) 307 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 308 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 309 /* CONTROL2 */ 310 # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) 311 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 312 #define PACKET3_UNMAP_QUEUES 0xA3 313 /* 1. header 314 * 2. CONTROL 315 * 3. CONTROL2 316 * 4. CONTROL3 317 * 5. CONTROL4 318 * 6. CONTROL5 319 */ 320 /* CONTROL */ 321 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) 322 /* 0 - PREEMPT_QUEUES 323 * 1 - RESET_QUEUES 324 * 2 - DISABLE_PROCESS_QUEUES 325 * 3 - PREEMPT_QUEUES_NO_UNMAP 326 */ 327 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 328 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 329 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 330 /* CONTROL2a */ 331 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) 332 /* CONTROL2b */ 333 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) 334 /* CONTROL3a */ 335 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) 336 /* CONTROL3b */ 337 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) 338 /* CONTROL4 */ 339 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) 340 /* CONTROL5 */ 341 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) 342 #define PACKET3_QUERY_STATUS 0xA4 343 /* 1. header 344 * 2. CONTROL 345 * 3. CONTROL2 346 * 4. ADDR_LO [31:0] 347 * 5. ADDR_HI [31:0] 348 * 6. DATA_LO [31:0] 349 * 7. DATA_HI [31:0] 350 */ 351 /* CONTROL */ 352 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) 353 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) 354 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) 355 /* CONTROL2a */ 356 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 357 /* CONTROL2b */ 358 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 359 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) 360 361 362 #define VCE_CMD_NO_OP 0x00000000 363 #define VCE_CMD_END 0x00000001 364 #define VCE_CMD_IB 0x00000002 365 #define VCE_CMD_FENCE 0x00000003 366 #define VCE_CMD_TRAP 0x00000004 367 #define VCE_CMD_IB_AUTO 0x00000005 368 #define VCE_CMD_SEMAPHORE 0x00000006 369 370 #define VCE_CMD_IB_VM 0x00000102 371 #define VCE_CMD_WAIT_GE 0x00000106 372 #define VCE_CMD_UPDATE_PTB 0x00000107 373 #define VCE_CMD_FLUSH_TLB 0x00000108 374 #define VCE_CMD_REG_WRITE 0x00000109 375 #define VCE_CMD_REG_WAIT 0x0000010a 376 377 #define HEVC_ENC_CMD_NO_OP 0x00000000 378 #define HEVC_ENC_CMD_END 0x00000001 379 #define HEVC_ENC_CMD_FENCE 0x00000003 380 #define HEVC_ENC_CMD_TRAP 0x00000004 381 #define HEVC_ENC_CMD_IB_VM 0x00000102 382 #define HEVC_ENC_CMD_REG_WRITE 0x00000109 383 #define HEVC_ENC_CMD_REG_WAIT 0x0000010a 384 385 #endif 386