1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "atom.h" 36 #include "amd_pcie.h" 37 38 #include "uvd/uvd_7_0_offset.h" 39 #include "gc/gc_9_0_offset.h" 40 #include "gc/gc_9_0_sh_mask.h" 41 #include "sdma0/sdma0_4_0_offset.h" 42 #include "sdma1/sdma1_4_0_offset.h" 43 #include "hdp/hdp_4_0_offset.h" 44 #include "hdp/hdp_4_0_sh_mask.h" 45 #include "smuio/smuio_9_0_offset.h" 46 #include "smuio/smuio_9_0_sh_mask.h" 47 #include "nbio/nbio_7_0_default.h" 48 #include "nbio/nbio_7_0_offset.h" 49 #include "nbio/nbio_7_0_sh_mask.h" 50 #include "nbio/nbio_7_0_smn.h" 51 #include "mp/mp_9_0_offset.h" 52 53 #include "soc15.h" 54 #include "soc15_common.h" 55 #include "gfx_v9_0.h" 56 #include "gmc_v9_0.h" 57 #include "gfxhub_v1_0.h" 58 #include "mmhub_v1_0.h" 59 #include "df_v1_7.h" 60 #include "df_v3_6.h" 61 #include "nbio_v6_1.h" 62 #include "nbio_v7_0.h" 63 #include "nbio_v7_4.h" 64 #include "vega10_ih.h" 65 #include "sdma_v4_0.h" 66 #include "uvd_v7_0.h" 67 #include "vce_v4_0.h" 68 #include "vcn_v1_0.h" 69 #include "vcn_v2_0.h" 70 #include "jpeg_v2_0.h" 71 #include "vcn_v2_5.h" 72 #include "jpeg_v2_5.h" 73 #include "dce_virtual.h" 74 #include "mxgpu_ai.h" 75 #include "amdgpu_smu.h" 76 #include "amdgpu_ras.h" 77 #include "amdgpu_xgmi.h" 78 #include <uapi/linux/kfd_ioctl.h> 79 80 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 81 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 82 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 84 85 /* for Vega20 register name change */ 86 #define mmHDP_MEM_POWER_CTRL 0x00d4 87 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 89 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 91 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 92 /* 93 * Indirect registers accessor 94 */ 95 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 96 { 97 unsigned long flags, address, data; 98 u32 r; 99 address = adev->nbio.funcs->get_pcie_index_offset(adev); 100 data = adev->nbio.funcs->get_pcie_data_offset(adev); 101 102 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 103 WREG32(address, reg); 104 (void)RREG32(address); 105 r = RREG32(data); 106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 107 return r; 108 } 109 110 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 111 { 112 unsigned long flags, address, data; 113 114 address = adev->nbio.funcs->get_pcie_index_offset(adev); 115 data = adev->nbio.funcs->get_pcie_data_offset(adev); 116 117 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 118 WREG32(address, reg); 119 (void)RREG32(address); 120 WREG32(data, v); 121 (void)RREG32(data); 122 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 123 } 124 125 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 126 { 127 unsigned long flags, address, data; 128 u64 r; 129 address = adev->nbio.funcs->get_pcie_index_offset(adev); 130 data = adev->nbio.funcs->get_pcie_data_offset(adev); 131 132 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 133 /* read low 32 bit */ 134 WREG32(address, reg); 135 (void)RREG32(address); 136 r = RREG32(data); 137 138 /* read high 32 bit*/ 139 WREG32(address, reg + 4); 140 (void)RREG32(address); 141 r |= ((u64)RREG32(data) << 32); 142 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 143 return r; 144 } 145 146 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 147 { 148 unsigned long flags, address, data; 149 150 address = adev->nbio.funcs->get_pcie_index_offset(adev); 151 data = adev->nbio.funcs->get_pcie_data_offset(adev); 152 153 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 154 /* write low 32 bit */ 155 WREG32(address, reg); 156 (void)RREG32(address); 157 WREG32(data, (u32)(v & 0xffffffffULL)); 158 (void)RREG32(data); 159 160 /* write high 32 bit */ 161 WREG32(address, reg + 4); 162 (void)RREG32(address); 163 WREG32(data, (u32)(v >> 32)); 164 (void)RREG32(data); 165 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 166 } 167 168 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 169 { 170 unsigned long flags, address, data; 171 u32 r; 172 173 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 174 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 175 176 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 177 WREG32(address, ((reg) & 0x1ff)); 178 r = RREG32(data); 179 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 180 return r; 181 } 182 183 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 184 { 185 unsigned long flags, address, data; 186 187 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 188 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 189 190 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 191 WREG32(address, ((reg) & 0x1ff)); 192 WREG32(data, (v)); 193 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 194 } 195 196 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 197 { 198 unsigned long flags, address, data; 199 u32 r; 200 201 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 202 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 203 204 spin_lock_irqsave(&adev->didt_idx_lock, flags); 205 WREG32(address, (reg)); 206 r = RREG32(data); 207 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 208 return r; 209 } 210 211 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 212 { 213 unsigned long flags, address, data; 214 215 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 216 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 217 218 spin_lock_irqsave(&adev->didt_idx_lock, flags); 219 WREG32(address, (reg)); 220 WREG32(data, (v)); 221 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 222 } 223 224 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 225 { 226 unsigned long flags; 227 u32 r; 228 229 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 230 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 231 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 232 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 233 return r; 234 } 235 236 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 237 { 238 unsigned long flags; 239 240 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 241 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 242 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 243 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 244 } 245 246 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 247 { 248 unsigned long flags; 249 u32 r; 250 251 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 252 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 253 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 254 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 255 return r; 256 } 257 258 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 259 { 260 unsigned long flags; 261 262 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 263 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 264 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 265 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 266 } 267 268 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 269 { 270 return adev->nbio.funcs->get_memsize(adev); 271 } 272 273 static u32 soc15_get_xclk(struct amdgpu_device *adev) 274 { 275 return adev->clock.spll.reference_freq; 276 } 277 278 279 void soc15_grbm_select(struct amdgpu_device *adev, 280 u32 me, u32 pipe, u32 queue, u32 vmid) 281 { 282 u32 grbm_gfx_cntl = 0; 283 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 284 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 285 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 286 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 287 288 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 289 } 290 291 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 292 { 293 /* todo */ 294 } 295 296 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 297 { 298 /* todo */ 299 return false; 300 } 301 302 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 303 u8 *bios, u32 length_bytes) 304 { 305 u32 *dw_ptr; 306 u32 i, length_dw; 307 308 if (bios == NULL) 309 return false; 310 if (length_bytes == 0) 311 return false; 312 /* APU vbios image is part of sbios image */ 313 if (adev->flags & AMD_IS_APU) 314 return false; 315 316 dw_ptr = (u32 *)bios; 317 length_dw = ALIGN(length_bytes, 4) / 4; 318 319 /* set rom index to 0 */ 320 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 321 /* read out the rom data */ 322 for (i = 0; i < length_dw; i++) 323 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 324 325 return true; 326 } 327 328 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 329 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 330 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 331 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 332 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 333 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 334 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 335 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 336 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 337 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 338 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 339 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 340 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 341 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 342 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 343 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 344 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 345 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 346 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 347 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 348 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 349 }; 350 351 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 352 u32 sh_num, u32 reg_offset) 353 { 354 uint32_t val; 355 356 mutex_lock(&adev->grbm_idx_mutex); 357 if (se_num != 0xffffffff || sh_num != 0xffffffff) 358 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 359 360 val = RREG32(reg_offset); 361 362 if (se_num != 0xffffffff || sh_num != 0xffffffff) 363 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 364 mutex_unlock(&adev->grbm_idx_mutex); 365 return val; 366 } 367 368 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 369 bool indexed, u32 se_num, 370 u32 sh_num, u32 reg_offset) 371 { 372 if (indexed) { 373 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 374 } else { 375 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 376 return adev->gfx.config.gb_addr_config; 377 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 378 return adev->gfx.config.db_debug2; 379 return RREG32(reg_offset); 380 } 381 } 382 383 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 384 u32 sh_num, u32 reg_offset, u32 *value) 385 { 386 uint32_t i; 387 struct soc15_allowed_register_entry *en; 388 389 *value = 0; 390 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 391 en = &soc15_allowed_read_registers[i]; 392 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 393 + en->reg_offset)) 394 continue; 395 396 *value = soc15_get_register_value(adev, 397 soc15_allowed_read_registers[i].grbm_indexed, 398 se_num, sh_num, reg_offset); 399 return 0; 400 } 401 return -EINVAL; 402 } 403 404 405 /** 406 * soc15_program_register_sequence - program an array of registers. 407 * 408 * @adev: amdgpu_device pointer 409 * @regs: pointer to the register array 410 * @array_size: size of the register array 411 * 412 * Programs an array or registers with and and or masks. 413 * This is a helper for setting golden registers. 414 */ 415 416 void soc15_program_register_sequence(struct amdgpu_device *adev, 417 const struct soc15_reg_golden *regs, 418 const u32 array_size) 419 { 420 const struct soc15_reg_golden *entry; 421 u32 tmp, reg; 422 int i; 423 424 for (i = 0; i < array_size; ++i) { 425 entry = ®s[i]; 426 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 427 428 if (entry->and_mask == 0xffffffff) { 429 tmp = entry->or_mask; 430 } else { 431 tmp = RREG32(reg); 432 tmp &= ~(entry->and_mask); 433 tmp |= (entry->or_mask & entry->and_mask); 434 } 435 436 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 437 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 438 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 439 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 440 WREG32_RLC(reg, tmp); 441 else 442 WREG32(reg, tmp); 443 444 } 445 446 } 447 448 static int soc15_asic_mode1_reset(struct amdgpu_device *adev) 449 { 450 u32 i; 451 int ret = 0; 452 453 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 454 455 dev_info(adev->dev, "GPU mode1 reset\n"); 456 457 /* disable BM */ 458 pci_clear_master(adev->pdev); 459 460 pci_save_state(adev->pdev); 461 462 ret = psp_gpu_reset(adev); 463 if (ret) 464 dev_err(adev->dev, "GPU mode1 reset failed\n"); 465 466 pci_restore_state(adev->pdev); 467 468 /* wait for asic to come out of reset */ 469 for (i = 0; i < adev->usec_timeout; i++) { 470 u32 memsize = adev->nbio.funcs->get_memsize(adev); 471 472 if (memsize != 0xffffffff) 473 break; 474 udelay(1); 475 } 476 477 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 478 479 return ret; 480 } 481 482 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 483 { 484 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 485 int ret = 0; 486 487 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 488 if (ras && ras->supported) 489 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 490 491 ret = amdgpu_dpm_baco_reset(adev); 492 if (ret) 493 return ret; 494 495 /* re-enable doorbell interrupt after BACO exit */ 496 if (ras && ras->supported) 497 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 498 499 return 0; 500 } 501 502 static enum amd_reset_method 503 soc15_asic_reset_method(struct amdgpu_device *adev) 504 { 505 bool baco_reset = false; 506 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 507 508 switch (adev->asic_type) { 509 case CHIP_RAVEN: 510 case CHIP_RENOIR: 511 return AMD_RESET_METHOD_MODE2; 512 case CHIP_VEGA10: 513 case CHIP_VEGA12: 514 case CHIP_ARCTURUS: 515 baco_reset = amdgpu_dpm_is_baco_supported(adev); 516 break; 517 case CHIP_VEGA20: 518 if (adev->psp.sos_fw_version >= 0x80067) 519 baco_reset = amdgpu_dpm_is_baco_supported(adev); 520 521 /* 522 * 1. PMFW version > 0x284300: all cases use baco 523 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 524 */ 525 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400) 526 baco_reset = false; 527 break; 528 default: 529 break; 530 } 531 532 if (baco_reset) 533 return AMD_RESET_METHOD_BACO; 534 else 535 return AMD_RESET_METHOD_MODE1; 536 } 537 538 static int soc15_asic_reset(struct amdgpu_device *adev) 539 { 540 switch (soc15_asic_reset_method(adev)) { 541 case AMD_RESET_METHOD_BACO: 542 if (!adev->in_suspend) 543 amdgpu_inc_vram_lost(adev); 544 return soc15_asic_baco_reset(adev); 545 case AMD_RESET_METHOD_MODE2: 546 return amdgpu_dpm_mode2_reset(adev); 547 default: 548 if (!adev->in_suspend) 549 amdgpu_inc_vram_lost(adev); 550 return soc15_asic_mode1_reset(adev); 551 } 552 } 553 554 static bool soc15_supports_baco(struct amdgpu_device *adev) 555 { 556 switch (adev->asic_type) { 557 case CHIP_VEGA10: 558 case CHIP_VEGA12: 559 case CHIP_ARCTURUS: 560 return amdgpu_dpm_is_baco_supported(adev); 561 case CHIP_VEGA20: 562 if (adev->psp.sos_fw_version >= 0x80067) 563 return amdgpu_dpm_is_baco_supported(adev); 564 return false; 565 default: 566 return false; 567 } 568 } 569 570 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 571 u32 cntl_reg, u32 status_reg) 572 { 573 return 0; 574 }*/ 575 576 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 577 { 578 /*int r; 579 580 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 581 if (r) 582 return r; 583 584 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 585 */ 586 return 0; 587 } 588 589 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 590 { 591 /* todo */ 592 593 return 0; 594 } 595 596 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 597 { 598 if (pci_is_root_bus(adev->pdev->bus)) 599 return; 600 601 if (amdgpu_pcie_gen2 == 0) 602 return; 603 604 if (adev->flags & AMD_IS_APU) 605 return; 606 607 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 608 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 609 return; 610 611 /* todo */ 612 } 613 614 static void soc15_program_aspm(struct amdgpu_device *adev) 615 { 616 617 if (amdgpu_aspm == 0) 618 return; 619 620 /* todo */ 621 } 622 623 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 624 bool enable) 625 { 626 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 627 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 628 } 629 630 static const struct amdgpu_ip_block_version vega10_common_ip_block = 631 { 632 .type = AMD_IP_BLOCK_TYPE_COMMON, 633 .major = 2, 634 .minor = 0, 635 .rev = 0, 636 .funcs = &soc15_common_ip_funcs, 637 }; 638 639 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 640 { 641 return adev->nbio.funcs->get_rev_id(adev); 642 } 643 644 int soc15_set_ip_blocks(struct amdgpu_device *adev) 645 { 646 /* Set IP register base before any HW register access */ 647 switch (adev->asic_type) { 648 case CHIP_VEGA10: 649 case CHIP_VEGA12: 650 case CHIP_RAVEN: 651 case CHIP_RENOIR: 652 vega10_reg_base_init(adev); 653 break; 654 case CHIP_VEGA20: 655 vega20_reg_base_init(adev); 656 break; 657 case CHIP_ARCTURUS: 658 arct_reg_base_init(adev); 659 break; 660 default: 661 return -EINVAL; 662 } 663 664 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 665 adev->gmc.xgmi.supported = true; 666 667 if (adev->flags & AMD_IS_APU) { 668 adev->nbio.funcs = &nbio_v7_0_funcs; 669 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 670 } else if (adev->asic_type == CHIP_VEGA20 || 671 adev->asic_type == CHIP_ARCTURUS) { 672 adev->nbio.funcs = &nbio_v7_4_funcs; 673 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 674 } else { 675 adev->nbio.funcs = &nbio_v6_1_funcs; 676 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 677 } 678 679 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 680 adev->df.funcs = &df_v3_6_funcs; 681 else 682 adev->df.funcs = &df_v1_7_funcs; 683 684 adev->rev_id = soc15_get_rev_id(adev); 685 adev->nbio.funcs->detect_hw_virt(adev); 686 687 if (amdgpu_sriov_vf(adev)) 688 adev->virt.ops = &xgpu_ai_virt_ops; 689 690 switch (adev->asic_type) { 691 case CHIP_VEGA10: 692 case CHIP_VEGA12: 693 case CHIP_VEGA20: 694 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 695 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 696 697 /* For Vega10 SR-IOV, PSP need to be initialized before IH */ 698 if (amdgpu_sriov_vf(adev)) { 699 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 700 if (adev->asic_type == CHIP_VEGA20) 701 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 702 else 703 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 704 } 705 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 706 } else { 707 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 708 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 709 if (adev->asic_type == CHIP_VEGA20) 710 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 711 else 712 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 713 } 714 } 715 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 716 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 717 if (is_support_sw_smu(adev)) { 718 if (!amdgpu_sriov_vf(adev)) 719 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 720 } else { 721 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 722 } 723 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 724 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 725 #if defined(CONFIG_DRM_AMD_DC) 726 else if (amdgpu_device_has_dc_support(adev)) 727 amdgpu_device_ip_block_add(adev, &dm_ip_block); 728 #endif 729 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { 730 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 731 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 732 } 733 break; 734 case CHIP_RAVEN: 735 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 736 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 737 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 738 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 739 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 740 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 741 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 742 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 743 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 744 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 745 #if defined(CONFIG_DRM_AMD_DC) 746 else if (amdgpu_device_has_dc_support(adev)) 747 amdgpu_device_ip_block_add(adev, &dm_ip_block); 748 #endif 749 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 750 break; 751 case CHIP_ARCTURUS: 752 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 753 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 754 755 if (amdgpu_sriov_vf(adev)) { 756 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 757 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 758 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 759 } else { 760 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 761 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 762 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 763 } 764 765 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 766 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 767 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 768 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 769 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 770 771 if (amdgpu_sriov_vf(adev)) { 772 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 773 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 774 } else { 775 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 776 } 777 if (!amdgpu_sriov_vf(adev)) 778 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 779 break; 780 case CHIP_RENOIR: 781 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 782 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 783 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 784 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 785 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 786 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 787 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 788 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 789 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 790 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 791 #if defined(CONFIG_DRM_AMD_DC) 792 else if (amdgpu_device_has_dc_support(adev)) 793 amdgpu_device_ip_block_add(adev, &dm_ip_block); 794 #endif 795 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 796 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 797 break; 798 default: 799 return -EINVAL; 800 } 801 802 return 0; 803 } 804 805 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 806 { 807 adev->nbio.funcs->hdp_flush(adev, ring); 808 } 809 810 static void soc15_invalidate_hdp(struct amdgpu_device *adev, 811 struct amdgpu_ring *ring) 812 { 813 if (!ring || !ring->funcs->emit_wreg) 814 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 815 else 816 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 817 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 818 } 819 820 static bool soc15_need_full_reset(struct amdgpu_device *adev) 821 { 822 /* change this when we implement soft reset */ 823 return true; 824 } 825 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 826 uint64_t *count1) 827 { 828 uint32_t perfctr = 0; 829 uint64_t cnt0_of, cnt1_of; 830 int tmp; 831 832 /* This reports 0 on APUs, so return to avoid writing/reading registers 833 * that may or may not be different from their GPU counterparts 834 */ 835 if (adev->flags & AMD_IS_APU) 836 return; 837 838 /* Set the 2 events that we wish to watch, defined above */ 839 /* Reg 40 is # received msgs */ 840 /* Reg 104 is # of posted requests sent */ 841 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 842 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 843 844 /* Write to enable desired perf counters */ 845 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 846 /* Zero out and enable the perf counters 847 * Write 0x5: 848 * Bit 0 = Start all counters(1) 849 * Bit 2 = Global counter reset enable(1) 850 */ 851 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 852 853 msleep(1000); 854 855 /* Load the shadow and disable the perf counters 856 * Write 0x2: 857 * Bit 0 = Stop counters(0) 858 * Bit 1 = Load the shadow counters(1) 859 */ 860 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 861 862 /* Read register values to get any >32bit overflow */ 863 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 864 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 865 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 866 867 /* Get the values and add the overflow */ 868 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 869 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 870 } 871 872 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 873 uint64_t *count1) 874 { 875 uint32_t perfctr = 0; 876 uint64_t cnt0_of, cnt1_of; 877 int tmp; 878 879 /* This reports 0 on APUs, so return to avoid writing/reading registers 880 * that may or may not be different from their GPU counterparts 881 */ 882 if (adev->flags & AMD_IS_APU) 883 return; 884 885 /* Set the 2 events that we wish to watch, defined above */ 886 /* Reg 40 is # received msgs */ 887 /* Reg 108 is # of posted requests sent on VG20 */ 888 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 889 EVENT0_SEL, 40); 890 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 891 EVENT1_SEL, 108); 892 893 /* Write to enable desired perf counters */ 894 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 895 /* Zero out and enable the perf counters 896 * Write 0x5: 897 * Bit 0 = Start all counters(1) 898 * Bit 2 = Global counter reset enable(1) 899 */ 900 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 901 902 msleep(1000); 903 904 /* Load the shadow and disable the perf counters 905 * Write 0x2: 906 * Bit 0 = Stop counters(0) 907 * Bit 1 = Load the shadow counters(1) 908 */ 909 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 910 911 /* Read register values to get any >32bit overflow */ 912 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 913 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 914 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 915 916 /* Get the values and add the overflow */ 917 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 918 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 919 } 920 921 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 922 { 923 u32 sol_reg; 924 925 /* Just return false for soc15 GPUs. Reset does not seem to 926 * be necessary. 927 */ 928 if (!amdgpu_passthrough(adev)) 929 return false; 930 931 if (adev->flags & AMD_IS_APU) 932 return false; 933 934 /* Check sOS sign of life register to confirm sys driver and sOS 935 * are already been loaded. 936 */ 937 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 938 if (sol_reg) 939 return true; 940 941 return false; 942 } 943 944 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 945 { 946 uint64_t nak_r, nak_g; 947 948 /* Get the number of NAKs received and generated */ 949 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 950 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 951 952 /* Add the total number of NAKs, i.e the number of replays */ 953 return (nak_r + nak_g); 954 } 955 956 static const struct amdgpu_asic_funcs soc15_asic_funcs = 957 { 958 .read_disabled_bios = &soc15_read_disabled_bios, 959 .read_bios_from_rom = &soc15_read_bios_from_rom, 960 .read_register = &soc15_read_register, 961 .reset = &soc15_asic_reset, 962 .reset_method = &soc15_asic_reset_method, 963 .set_vga_state = &soc15_vga_set_state, 964 .get_xclk = &soc15_get_xclk, 965 .set_uvd_clocks = &soc15_set_uvd_clocks, 966 .set_vce_clocks = &soc15_set_vce_clocks, 967 .get_config_memsize = &soc15_get_config_memsize, 968 .flush_hdp = &soc15_flush_hdp, 969 .invalidate_hdp = &soc15_invalidate_hdp, 970 .need_full_reset = &soc15_need_full_reset, 971 .init_doorbell_index = &vega10_doorbell_index_init, 972 .get_pcie_usage = &soc15_get_pcie_usage, 973 .need_reset_on_init = &soc15_need_reset_on_init, 974 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 975 .supports_baco = &soc15_supports_baco, 976 }; 977 978 static const struct amdgpu_asic_funcs vega20_asic_funcs = 979 { 980 .read_disabled_bios = &soc15_read_disabled_bios, 981 .read_bios_from_rom = &soc15_read_bios_from_rom, 982 .read_register = &soc15_read_register, 983 .reset = &soc15_asic_reset, 984 .reset_method = &soc15_asic_reset_method, 985 .set_vga_state = &soc15_vga_set_state, 986 .get_xclk = &soc15_get_xclk, 987 .set_uvd_clocks = &soc15_set_uvd_clocks, 988 .set_vce_clocks = &soc15_set_vce_clocks, 989 .get_config_memsize = &soc15_get_config_memsize, 990 .flush_hdp = &soc15_flush_hdp, 991 .invalidate_hdp = &soc15_invalidate_hdp, 992 .need_full_reset = &soc15_need_full_reset, 993 .init_doorbell_index = &vega20_doorbell_index_init, 994 .get_pcie_usage = &vega20_get_pcie_usage, 995 .need_reset_on_init = &soc15_need_reset_on_init, 996 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 997 .supports_baco = &soc15_supports_baco, 998 }; 999 1000 static int soc15_common_early_init(void *handle) 1001 { 1002 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 1003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1004 1005 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 1006 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 1007 adev->smc_rreg = NULL; 1008 adev->smc_wreg = NULL; 1009 adev->pcie_rreg = &soc15_pcie_rreg; 1010 adev->pcie_wreg = &soc15_pcie_wreg; 1011 adev->pcie_rreg64 = &soc15_pcie_rreg64; 1012 adev->pcie_wreg64 = &soc15_pcie_wreg64; 1013 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 1014 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 1015 adev->didt_rreg = &soc15_didt_rreg; 1016 adev->didt_wreg = &soc15_didt_wreg; 1017 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 1018 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 1019 adev->se_cac_rreg = &soc15_se_cac_rreg; 1020 adev->se_cac_wreg = &soc15_se_cac_wreg; 1021 1022 1023 adev->external_rev_id = 0xFF; 1024 switch (adev->asic_type) { 1025 case CHIP_VEGA10: 1026 adev->asic_funcs = &soc15_asic_funcs; 1027 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1028 AMD_CG_SUPPORT_GFX_MGLS | 1029 AMD_CG_SUPPORT_GFX_RLC_LS | 1030 AMD_CG_SUPPORT_GFX_CP_LS | 1031 AMD_CG_SUPPORT_GFX_3D_CGCG | 1032 AMD_CG_SUPPORT_GFX_3D_CGLS | 1033 AMD_CG_SUPPORT_GFX_CGCG | 1034 AMD_CG_SUPPORT_GFX_CGLS | 1035 AMD_CG_SUPPORT_BIF_MGCG | 1036 AMD_CG_SUPPORT_BIF_LS | 1037 AMD_CG_SUPPORT_HDP_LS | 1038 AMD_CG_SUPPORT_DRM_MGCG | 1039 AMD_CG_SUPPORT_DRM_LS | 1040 AMD_CG_SUPPORT_ROM_MGCG | 1041 AMD_CG_SUPPORT_DF_MGCG | 1042 AMD_CG_SUPPORT_SDMA_MGCG | 1043 AMD_CG_SUPPORT_SDMA_LS | 1044 AMD_CG_SUPPORT_MC_MGCG | 1045 AMD_CG_SUPPORT_MC_LS; 1046 adev->pg_flags = 0; 1047 adev->external_rev_id = 0x1; 1048 break; 1049 case CHIP_VEGA12: 1050 adev->asic_funcs = &soc15_asic_funcs; 1051 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1052 AMD_CG_SUPPORT_GFX_MGLS | 1053 AMD_CG_SUPPORT_GFX_CGCG | 1054 AMD_CG_SUPPORT_GFX_CGLS | 1055 AMD_CG_SUPPORT_GFX_3D_CGCG | 1056 AMD_CG_SUPPORT_GFX_3D_CGLS | 1057 AMD_CG_SUPPORT_GFX_CP_LS | 1058 AMD_CG_SUPPORT_MC_LS | 1059 AMD_CG_SUPPORT_MC_MGCG | 1060 AMD_CG_SUPPORT_SDMA_MGCG | 1061 AMD_CG_SUPPORT_SDMA_LS | 1062 AMD_CG_SUPPORT_BIF_MGCG | 1063 AMD_CG_SUPPORT_BIF_LS | 1064 AMD_CG_SUPPORT_HDP_MGCG | 1065 AMD_CG_SUPPORT_HDP_LS | 1066 AMD_CG_SUPPORT_ROM_MGCG | 1067 AMD_CG_SUPPORT_VCE_MGCG | 1068 AMD_CG_SUPPORT_UVD_MGCG; 1069 adev->pg_flags = 0; 1070 adev->external_rev_id = adev->rev_id + 0x14; 1071 break; 1072 case CHIP_VEGA20: 1073 adev->asic_funcs = &vega20_asic_funcs; 1074 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1075 AMD_CG_SUPPORT_GFX_MGLS | 1076 AMD_CG_SUPPORT_GFX_CGCG | 1077 AMD_CG_SUPPORT_GFX_CGLS | 1078 AMD_CG_SUPPORT_GFX_3D_CGCG | 1079 AMD_CG_SUPPORT_GFX_3D_CGLS | 1080 AMD_CG_SUPPORT_GFX_CP_LS | 1081 AMD_CG_SUPPORT_MC_LS | 1082 AMD_CG_SUPPORT_MC_MGCG | 1083 AMD_CG_SUPPORT_SDMA_MGCG | 1084 AMD_CG_SUPPORT_SDMA_LS | 1085 AMD_CG_SUPPORT_BIF_MGCG | 1086 AMD_CG_SUPPORT_BIF_LS | 1087 AMD_CG_SUPPORT_HDP_MGCG | 1088 AMD_CG_SUPPORT_HDP_LS | 1089 AMD_CG_SUPPORT_ROM_MGCG | 1090 AMD_CG_SUPPORT_VCE_MGCG | 1091 AMD_CG_SUPPORT_UVD_MGCG; 1092 adev->pg_flags = 0; 1093 adev->external_rev_id = adev->rev_id + 0x28; 1094 break; 1095 case CHIP_RAVEN: 1096 adev->asic_funcs = &soc15_asic_funcs; 1097 if (adev->rev_id >= 0x8) 1098 adev->external_rev_id = adev->rev_id + 0x79; 1099 else if (adev->pdev->device == 0x15d8) 1100 adev->external_rev_id = adev->rev_id + 0x41; 1101 else if (adev->rev_id == 1) 1102 adev->external_rev_id = adev->rev_id + 0x20; 1103 else 1104 adev->external_rev_id = adev->rev_id + 0x01; 1105 1106 if (adev->rev_id >= 0x8) { 1107 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1108 AMD_CG_SUPPORT_GFX_MGLS | 1109 AMD_CG_SUPPORT_GFX_CP_LS | 1110 AMD_CG_SUPPORT_GFX_3D_CGCG | 1111 AMD_CG_SUPPORT_GFX_3D_CGLS | 1112 AMD_CG_SUPPORT_GFX_CGCG | 1113 AMD_CG_SUPPORT_GFX_CGLS | 1114 AMD_CG_SUPPORT_BIF_LS | 1115 AMD_CG_SUPPORT_HDP_LS | 1116 AMD_CG_SUPPORT_ROM_MGCG | 1117 AMD_CG_SUPPORT_MC_MGCG | 1118 AMD_CG_SUPPORT_MC_LS | 1119 AMD_CG_SUPPORT_SDMA_MGCG | 1120 AMD_CG_SUPPORT_SDMA_LS | 1121 AMD_CG_SUPPORT_VCN_MGCG; 1122 1123 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1124 } else if (adev->pdev->device == 0x15d8) { 1125 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1126 AMD_CG_SUPPORT_GFX_MGLS | 1127 AMD_CG_SUPPORT_GFX_CP_LS | 1128 AMD_CG_SUPPORT_GFX_3D_CGCG | 1129 AMD_CG_SUPPORT_GFX_3D_CGLS | 1130 AMD_CG_SUPPORT_GFX_CGCG | 1131 AMD_CG_SUPPORT_GFX_CGLS | 1132 AMD_CG_SUPPORT_BIF_LS | 1133 AMD_CG_SUPPORT_HDP_LS | 1134 AMD_CG_SUPPORT_ROM_MGCG | 1135 AMD_CG_SUPPORT_MC_MGCG | 1136 AMD_CG_SUPPORT_MC_LS | 1137 AMD_CG_SUPPORT_SDMA_MGCG | 1138 AMD_CG_SUPPORT_SDMA_LS; 1139 1140 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1141 AMD_PG_SUPPORT_MMHUB | 1142 AMD_PG_SUPPORT_VCN | 1143 AMD_PG_SUPPORT_VCN_DPG; 1144 } else { 1145 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1146 AMD_CG_SUPPORT_GFX_MGLS | 1147 AMD_CG_SUPPORT_GFX_RLC_LS | 1148 AMD_CG_SUPPORT_GFX_CP_LS | 1149 AMD_CG_SUPPORT_GFX_3D_CGCG | 1150 AMD_CG_SUPPORT_GFX_3D_CGLS | 1151 AMD_CG_SUPPORT_GFX_CGCG | 1152 AMD_CG_SUPPORT_GFX_CGLS | 1153 AMD_CG_SUPPORT_BIF_MGCG | 1154 AMD_CG_SUPPORT_BIF_LS | 1155 AMD_CG_SUPPORT_HDP_MGCG | 1156 AMD_CG_SUPPORT_HDP_LS | 1157 AMD_CG_SUPPORT_DRM_MGCG | 1158 AMD_CG_SUPPORT_DRM_LS | 1159 AMD_CG_SUPPORT_ROM_MGCG | 1160 AMD_CG_SUPPORT_MC_MGCG | 1161 AMD_CG_SUPPORT_MC_LS | 1162 AMD_CG_SUPPORT_SDMA_MGCG | 1163 AMD_CG_SUPPORT_SDMA_LS | 1164 AMD_CG_SUPPORT_VCN_MGCG; 1165 1166 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1167 } 1168 break; 1169 case CHIP_ARCTURUS: 1170 adev->asic_funcs = &vega20_asic_funcs; 1171 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1172 AMD_CG_SUPPORT_GFX_MGLS | 1173 AMD_CG_SUPPORT_GFX_CGCG | 1174 AMD_CG_SUPPORT_GFX_CGLS | 1175 AMD_CG_SUPPORT_GFX_CP_LS | 1176 AMD_CG_SUPPORT_HDP_MGCG | 1177 AMD_CG_SUPPORT_HDP_LS | 1178 AMD_CG_SUPPORT_SDMA_MGCG | 1179 AMD_CG_SUPPORT_SDMA_LS | 1180 AMD_CG_SUPPORT_MC_MGCG | 1181 AMD_CG_SUPPORT_MC_LS | 1182 AMD_CG_SUPPORT_IH_CG | 1183 AMD_CG_SUPPORT_VCN_MGCG | 1184 AMD_CG_SUPPORT_JPEG_MGCG; 1185 adev->pg_flags = 0; 1186 adev->external_rev_id = adev->rev_id + 0x32; 1187 break; 1188 case CHIP_RENOIR: 1189 adev->asic_funcs = &soc15_asic_funcs; 1190 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1191 AMD_CG_SUPPORT_GFX_MGLS | 1192 AMD_CG_SUPPORT_GFX_3D_CGCG | 1193 AMD_CG_SUPPORT_GFX_3D_CGLS | 1194 AMD_CG_SUPPORT_GFX_CGCG | 1195 AMD_CG_SUPPORT_GFX_CGLS | 1196 AMD_CG_SUPPORT_GFX_CP_LS | 1197 AMD_CG_SUPPORT_MC_MGCG | 1198 AMD_CG_SUPPORT_MC_LS | 1199 AMD_CG_SUPPORT_SDMA_MGCG | 1200 AMD_CG_SUPPORT_SDMA_LS | 1201 AMD_CG_SUPPORT_BIF_LS | 1202 AMD_CG_SUPPORT_HDP_LS | 1203 AMD_CG_SUPPORT_ROM_MGCG | 1204 AMD_CG_SUPPORT_VCN_MGCG | 1205 AMD_CG_SUPPORT_JPEG_MGCG | 1206 AMD_CG_SUPPORT_IH_CG | 1207 AMD_CG_SUPPORT_ATHUB_LS | 1208 AMD_CG_SUPPORT_ATHUB_MGCG | 1209 AMD_CG_SUPPORT_DF_MGCG; 1210 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1211 AMD_PG_SUPPORT_VCN | 1212 AMD_PG_SUPPORT_JPEG | 1213 AMD_PG_SUPPORT_VCN_DPG; 1214 adev->external_rev_id = adev->rev_id + 0x91; 1215 break; 1216 default: 1217 /* FIXME: not supported yet */ 1218 return -EINVAL; 1219 } 1220 1221 if (amdgpu_sriov_vf(adev)) { 1222 amdgpu_virt_init_setting(adev); 1223 xgpu_ai_mailbox_set_irq_funcs(adev); 1224 } 1225 1226 return 0; 1227 } 1228 1229 static int soc15_common_late_init(void *handle) 1230 { 1231 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1232 int r = 0; 1233 1234 if (amdgpu_sriov_vf(adev)) 1235 xgpu_ai_mailbox_get_irq(adev); 1236 1237 if (adev->nbio.funcs->ras_late_init) 1238 r = adev->nbio.funcs->ras_late_init(adev); 1239 1240 return r; 1241 } 1242 1243 static int soc15_common_sw_init(void *handle) 1244 { 1245 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1246 1247 if (amdgpu_sriov_vf(adev)) 1248 xgpu_ai_mailbox_add_irq_id(adev); 1249 1250 adev->df.funcs->sw_init(adev); 1251 1252 return 0; 1253 } 1254 1255 static int soc15_common_sw_fini(void *handle) 1256 { 1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1258 1259 amdgpu_nbio_ras_fini(adev); 1260 adev->df.funcs->sw_fini(adev); 1261 return 0; 1262 } 1263 1264 static void soc15_doorbell_range_init(struct amdgpu_device *adev) 1265 { 1266 int i; 1267 struct amdgpu_ring *ring; 1268 1269 /* sdma/ih doorbell range are programed by hypervisor */ 1270 if (!amdgpu_sriov_vf(adev)) { 1271 for (i = 0; i < adev->sdma.num_instances; i++) { 1272 ring = &adev->sdma.instance[i].ring; 1273 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1274 ring->use_doorbell, ring->doorbell_index, 1275 adev->doorbell_index.sdma_doorbell_range); 1276 } 1277 1278 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 1279 adev->irq.ih.doorbell_index); 1280 } 1281 } 1282 1283 static int soc15_common_hw_init(void *handle) 1284 { 1285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1286 1287 /* enable pcie gen2/3 link */ 1288 soc15_pcie_gen3_enable(adev); 1289 /* enable aspm */ 1290 soc15_program_aspm(adev); 1291 /* setup nbio registers */ 1292 adev->nbio.funcs->init_registers(adev); 1293 /* remap HDP registers to a hole in mmio space, 1294 * for the purpose of expose those registers 1295 * to process space 1296 */ 1297 if (adev->nbio.funcs->remap_hdp_registers) 1298 adev->nbio.funcs->remap_hdp_registers(adev); 1299 1300 /* enable the doorbell aperture */ 1301 soc15_enable_doorbell_aperture(adev, true); 1302 /* HW doorbell routing policy: doorbell writing not 1303 * in SDMA/IH/MM/ACV range will be routed to CP. So 1304 * we need to init SDMA/IH/MM/ACV doorbell range prior 1305 * to CP ip block init and ring test. 1306 */ 1307 soc15_doorbell_range_init(adev); 1308 1309 return 0; 1310 } 1311 1312 static int soc15_common_hw_fini(void *handle) 1313 { 1314 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1315 1316 /* disable the doorbell aperture */ 1317 soc15_enable_doorbell_aperture(adev, false); 1318 if (amdgpu_sriov_vf(adev)) 1319 xgpu_ai_mailbox_put_irq(adev); 1320 1321 if (adev->nbio.ras_if && 1322 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1323 if (adev->nbio.funcs->init_ras_controller_interrupt) 1324 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1325 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) 1326 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1327 } 1328 1329 return 0; 1330 } 1331 1332 static int soc15_common_suspend(void *handle) 1333 { 1334 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1335 1336 return soc15_common_hw_fini(adev); 1337 } 1338 1339 static int soc15_common_resume(void *handle) 1340 { 1341 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1342 1343 return soc15_common_hw_init(adev); 1344 } 1345 1346 static bool soc15_common_is_idle(void *handle) 1347 { 1348 return true; 1349 } 1350 1351 static int soc15_common_wait_for_idle(void *handle) 1352 { 1353 return 0; 1354 } 1355 1356 static int soc15_common_soft_reset(void *handle) 1357 { 1358 return 0; 1359 } 1360 1361 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) 1362 { 1363 uint32_t def, data; 1364 1365 if (adev->asic_type == CHIP_VEGA20 || 1366 adev->asic_type == CHIP_ARCTURUS) { 1367 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); 1368 1369 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1370 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1371 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1372 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1373 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; 1374 else 1375 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1376 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1377 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1378 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); 1379 1380 if (def != data) 1381 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); 1382 } else { 1383 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1384 1385 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1386 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1387 else 1388 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1389 1390 if (def != data) 1391 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 1392 } 1393 } 1394 1395 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1396 { 1397 uint32_t def, data; 1398 1399 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1400 1401 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1402 data &= ~(0x01000000 | 1403 0x02000000 | 1404 0x04000000 | 1405 0x08000000 | 1406 0x10000000 | 1407 0x20000000 | 1408 0x40000000 | 1409 0x80000000); 1410 else 1411 data |= (0x01000000 | 1412 0x02000000 | 1413 0x04000000 | 1414 0x08000000 | 1415 0x10000000 | 1416 0x20000000 | 1417 0x40000000 | 1418 0x80000000); 1419 1420 if (def != data) 1421 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1422 } 1423 1424 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1425 { 1426 uint32_t def, data; 1427 1428 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1429 1430 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1431 data |= 1; 1432 else 1433 data &= ~1; 1434 1435 if (def != data) 1436 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1437 } 1438 1439 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1440 bool enable) 1441 { 1442 uint32_t def, data; 1443 1444 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1445 1446 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1447 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1448 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1449 else 1450 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1451 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1452 1453 if (def != data) 1454 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); 1455 } 1456 1457 static int soc15_common_set_clockgating_state(void *handle, 1458 enum amd_clockgating_state state) 1459 { 1460 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1461 1462 if (amdgpu_sriov_vf(adev)) 1463 return 0; 1464 1465 switch (adev->asic_type) { 1466 case CHIP_VEGA10: 1467 case CHIP_VEGA12: 1468 case CHIP_VEGA20: 1469 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1470 state == AMD_CG_STATE_GATE ? true : false); 1471 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1472 state == AMD_CG_STATE_GATE ? true : false); 1473 soc15_update_hdp_light_sleep(adev, 1474 state == AMD_CG_STATE_GATE ? true : false); 1475 soc15_update_drm_clock_gating(adev, 1476 state == AMD_CG_STATE_GATE ? true : false); 1477 soc15_update_drm_light_sleep(adev, 1478 state == AMD_CG_STATE_GATE ? true : false); 1479 soc15_update_rom_medium_grain_clock_gating(adev, 1480 state == AMD_CG_STATE_GATE ? true : false); 1481 adev->df.funcs->update_medium_grain_clock_gating(adev, 1482 state == AMD_CG_STATE_GATE ? true : false); 1483 break; 1484 case CHIP_RAVEN: 1485 case CHIP_RENOIR: 1486 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1487 state == AMD_CG_STATE_GATE ? true : false); 1488 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1489 state == AMD_CG_STATE_GATE ? true : false); 1490 soc15_update_hdp_light_sleep(adev, 1491 state == AMD_CG_STATE_GATE ? true : false); 1492 soc15_update_drm_clock_gating(adev, 1493 state == AMD_CG_STATE_GATE ? true : false); 1494 soc15_update_drm_light_sleep(adev, 1495 state == AMD_CG_STATE_GATE ? true : false); 1496 soc15_update_rom_medium_grain_clock_gating(adev, 1497 state == AMD_CG_STATE_GATE ? true : false); 1498 break; 1499 case CHIP_ARCTURUS: 1500 soc15_update_hdp_light_sleep(adev, 1501 state == AMD_CG_STATE_GATE ? true : false); 1502 break; 1503 default: 1504 break; 1505 } 1506 return 0; 1507 } 1508 1509 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1510 { 1511 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1512 int data; 1513 1514 if (amdgpu_sriov_vf(adev)) 1515 *flags = 0; 1516 1517 adev->nbio.funcs->get_clockgating_state(adev, flags); 1518 1519 /* AMD_CG_SUPPORT_HDP_LS */ 1520 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1521 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 1522 *flags |= AMD_CG_SUPPORT_HDP_LS; 1523 1524 /* AMD_CG_SUPPORT_DRM_MGCG */ 1525 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1526 if (!(data & 0x01000000)) 1527 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1528 1529 /* AMD_CG_SUPPORT_DRM_LS */ 1530 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1531 if (data & 0x1) 1532 *flags |= AMD_CG_SUPPORT_DRM_LS; 1533 1534 /* AMD_CG_SUPPORT_ROM_MGCG */ 1535 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1536 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 1537 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 1538 1539 adev->df.funcs->get_clockgating_state(adev, flags); 1540 } 1541 1542 static int soc15_common_set_powergating_state(void *handle, 1543 enum amd_powergating_state state) 1544 { 1545 /* todo */ 1546 return 0; 1547 } 1548 1549 const struct amd_ip_funcs soc15_common_ip_funcs = { 1550 .name = "soc15_common", 1551 .early_init = soc15_common_early_init, 1552 .late_init = soc15_common_late_init, 1553 .sw_init = soc15_common_sw_init, 1554 .sw_fini = soc15_common_sw_fini, 1555 .hw_init = soc15_common_hw_init, 1556 .hw_fini = soc15_common_hw_fini, 1557 .suspend = soc15_common_suspend, 1558 .resume = soc15_common_resume, 1559 .is_idle = soc15_common_is_idle, 1560 .wait_for_idle = soc15_common_wait_for_idle, 1561 .soft_reset = soc15_common_soft_reset, 1562 .set_clockgating_state = soc15_common_set_clockgating_state, 1563 .set_powergating_state = soc15_common_set_powergating_state, 1564 .get_clockgating_state= soc15_common_get_clockgating_state, 1565 }; 1566