1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "atom.h" 36 #include "amd_pcie.h" 37 38 #include "uvd/uvd_7_0_offset.h" 39 #include "gc/gc_9_0_offset.h" 40 #include "gc/gc_9_0_sh_mask.h" 41 #include "sdma0/sdma0_4_0_offset.h" 42 #include "sdma1/sdma1_4_0_offset.h" 43 #include "hdp/hdp_4_0_offset.h" 44 #include "hdp/hdp_4_0_sh_mask.h" 45 #include "smuio/smuio_9_0_offset.h" 46 #include "smuio/smuio_9_0_sh_mask.h" 47 #include "nbio/nbio_7_0_default.h" 48 #include "nbio/nbio_7_0_offset.h" 49 #include "nbio/nbio_7_0_sh_mask.h" 50 #include "nbio/nbio_7_0_smn.h" 51 #include "mp/mp_9_0_offset.h" 52 53 #include "soc15.h" 54 #include "soc15_common.h" 55 #include "gfx_v9_0.h" 56 #include "gmc_v9_0.h" 57 #include "gfxhub_v1_0.h" 58 #include "mmhub_v1_0.h" 59 #include "df_v1_7.h" 60 #include "df_v3_6.h" 61 #include "nbio_v6_1.h" 62 #include "nbio_v7_0.h" 63 #include "nbio_v7_4.h" 64 #include "vega10_ih.h" 65 #include "sdma_v4_0.h" 66 #include "uvd_v7_0.h" 67 #include "vce_v4_0.h" 68 #include "vcn_v1_0.h" 69 #include "vcn_v2_0.h" 70 #include "jpeg_v2_0.h" 71 #include "vcn_v2_5.h" 72 #include "jpeg_v2_5.h" 73 #include "dce_virtual.h" 74 #include "mxgpu_ai.h" 75 #include "amdgpu_smu.h" 76 #include "amdgpu_ras.h" 77 #include "amdgpu_xgmi.h" 78 #include <uapi/linux/kfd_ioctl.h> 79 80 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 81 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 82 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 84 85 /* for Vega20 register name change */ 86 #define mmHDP_MEM_POWER_CTRL 0x00d4 87 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 89 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 91 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 92 /* 93 * Indirect registers accessor 94 */ 95 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 96 { 97 unsigned long flags, address, data; 98 u32 r; 99 address = adev->nbio.funcs->get_pcie_index_offset(adev); 100 data = adev->nbio.funcs->get_pcie_data_offset(adev); 101 102 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 103 WREG32(address, reg); 104 (void)RREG32(address); 105 r = RREG32(data); 106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 107 return r; 108 } 109 110 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 111 { 112 unsigned long flags, address, data; 113 114 address = adev->nbio.funcs->get_pcie_index_offset(adev); 115 data = adev->nbio.funcs->get_pcie_data_offset(adev); 116 117 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 118 WREG32(address, reg); 119 (void)RREG32(address); 120 WREG32(data, v); 121 (void)RREG32(data); 122 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 123 } 124 125 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 126 { 127 unsigned long flags, address, data; 128 u64 r; 129 address = adev->nbio.funcs->get_pcie_index_offset(adev); 130 data = adev->nbio.funcs->get_pcie_data_offset(adev); 131 132 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 133 /* read low 32 bit */ 134 WREG32(address, reg); 135 (void)RREG32(address); 136 r = RREG32(data); 137 138 /* read high 32 bit*/ 139 WREG32(address, reg + 4); 140 (void)RREG32(address); 141 r |= ((u64)RREG32(data) << 32); 142 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 143 return r; 144 } 145 146 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 147 { 148 unsigned long flags, address, data; 149 150 address = adev->nbio.funcs->get_pcie_index_offset(adev); 151 data = adev->nbio.funcs->get_pcie_data_offset(adev); 152 153 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 154 /* write low 32 bit */ 155 WREG32(address, reg); 156 (void)RREG32(address); 157 WREG32(data, (u32)(v & 0xffffffffULL)); 158 (void)RREG32(data); 159 160 /* write high 32 bit */ 161 WREG32(address, reg + 4); 162 (void)RREG32(address); 163 WREG32(data, (u32)(v >> 32)); 164 (void)RREG32(data); 165 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 166 } 167 168 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 169 { 170 unsigned long flags, address, data; 171 u32 r; 172 173 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 174 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 175 176 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 177 WREG32(address, ((reg) & 0x1ff)); 178 r = RREG32(data); 179 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 180 return r; 181 } 182 183 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 184 { 185 unsigned long flags, address, data; 186 187 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 188 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 189 190 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 191 WREG32(address, ((reg) & 0x1ff)); 192 WREG32(data, (v)); 193 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 194 } 195 196 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 197 { 198 unsigned long flags, address, data; 199 u32 r; 200 201 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 202 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 203 204 spin_lock_irqsave(&adev->didt_idx_lock, flags); 205 WREG32(address, (reg)); 206 r = RREG32(data); 207 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 208 return r; 209 } 210 211 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 212 { 213 unsigned long flags, address, data; 214 215 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 216 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 217 218 spin_lock_irqsave(&adev->didt_idx_lock, flags); 219 WREG32(address, (reg)); 220 WREG32(data, (v)); 221 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 222 } 223 224 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 225 { 226 unsigned long flags; 227 u32 r; 228 229 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 230 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 231 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 232 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 233 return r; 234 } 235 236 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 237 { 238 unsigned long flags; 239 240 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 241 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 242 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 243 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 244 } 245 246 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 247 { 248 unsigned long flags; 249 u32 r; 250 251 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 252 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 253 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 254 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 255 return r; 256 } 257 258 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 259 { 260 unsigned long flags; 261 262 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 263 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 264 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 265 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 266 } 267 268 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 269 { 270 return adev->nbio.funcs->get_memsize(adev); 271 } 272 273 static u32 soc15_get_xclk(struct amdgpu_device *adev) 274 { 275 return adev->clock.spll.reference_freq; 276 } 277 278 279 void soc15_grbm_select(struct amdgpu_device *adev, 280 u32 me, u32 pipe, u32 queue, u32 vmid) 281 { 282 u32 grbm_gfx_cntl = 0; 283 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 284 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 285 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 286 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 287 288 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 289 } 290 291 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 292 { 293 /* todo */ 294 } 295 296 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 297 { 298 /* todo */ 299 return false; 300 } 301 302 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 303 u8 *bios, u32 length_bytes) 304 { 305 u32 *dw_ptr; 306 u32 i, length_dw; 307 308 if (bios == NULL) 309 return false; 310 if (length_bytes == 0) 311 return false; 312 /* APU vbios image is part of sbios image */ 313 if (adev->flags & AMD_IS_APU) 314 return false; 315 316 dw_ptr = (u32 *)bios; 317 length_dw = ALIGN(length_bytes, 4) / 4; 318 319 /* set rom index to 0 */ 320 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 321 /* read out the rom data */ 322 for (i = 0; i < length_dw; i++) 323 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 324 325 return true; 326 } 327 328 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 329 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 330 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 331 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 332 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 333 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 334 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 335 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 336 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 337 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 338 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 339 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 340 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 341 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 342 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 343 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 344 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 345 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 346 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 347 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 348 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 349 }; 350 351 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 352 u32 sh_num, u32 reg_offset) 353 { 354 uint32_t val; 355 356 mutex_lock(&adev->grbm_idx_mutex); 357 if (se_num != 0xffffffff || sh_num != 0xffffffff) 358 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 359 360 val = RREG32(reg_offset); 361 362 if (se_num != 0xffffffff || sh_num != 0xffffffff) 363 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 364 mutex_unlock(&adev->grbm_idx_mutex); 365 return val; 366 } 367 368 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 369 bool indexed, u32 se_num, 370 u32 sh_num, u32 reg_offset) 371 { 372 if (indexed) { 373 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 374 } else { 375 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 376 return adev->gfx.config.gb_addr_config; 377 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 378 return adev->gfx.config.db_debug2; 379 return RREG32(reg_offset); 380 } 381 } 382 383 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 384 u32 sh_num, u32 reg_offset, u32 *value) 385 { 386 uint32_t i; 387 struct soc15_allowed_register_entry *en; 388 389 *value = 0; 390 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 391 en = &soc15_allowed_read_registers[i]; 392 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 393 + en->reg_offset)) 394 continue; 395 396 *value = soc15_get_register_value(adev, 397 soc15_allowed_read_registers[i].grbm_indexed, 398 se_num, sh_num, reg_offset); 399 return 0; 400 } 401 return -EINVAL; 402 } 403 404 405 /** 406 * soc15_program_register_sequence - program an array of registers. 407 * 408 * @adev: amdgpu_device pointer 409 * @regs: pointer to the register array 410 * @array_size: size of the register array 411 * 412 * Programs an array or registers with and and or masks. 413 * This is a helper for setting golden registers. 414 */ 415 416 void soc15_program_register_sequence(struct amdgpu_device *adev, 417 const struct soc15_reg_golden *regs, 418 const u32 array_size) 419 { 420 const struct soc15_reg_golden *entry; 421 u32 tmp, reg; 422 int i; 423 424 for (i = 0; i < array_size; ++i) { 425 entry = ®s[i]; 426 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 427 428 if (entry->and_mask == 0xffffffff) { 429 tmp = entry->or_mask; 430 } else { 431 tmp = RREG32(reg); 432 tmp &= ~(entry->and_mask); 433 tmp |= (entry->or_mask & entry->and_mask); 434 } 435 436 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 437 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 438 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 439 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 440 WREG32_RLC(reg, tmp); 441 else 442 WREG32(reg, tmp); 443 444 } 445 446 } 447 448 static int soc15_asic_mode1_reset(struct amdgpu_device *adev) 449 { 450 u32 i; 451 int ret = 0; 452 453 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 454 455 dev_info(adev->dev, "GPU mode1 reset\n"); 456 457 /* disable BM */ 458 pci_clear_master(adev->pdev); 459 460 pci_save_state(adev->pdev); 461 462 ret = psp_gpu_reset(adev); 463 if (ret) 464 dev_err(adev->dev, "GPU mode1 reset failed\n"); 465 466 pci_restore_state(adev->pdev); 467 468 /* wait for asic to come out of reset */ 469 for (i = 0; i < adev->usec_timeout; i++) { 470 u32 memsize = adev->nbio.funcs->get_memsize(adev); 471 472 if (memsize != 0xffffffff) 473 break; 474 udelay(1); 475 } 476 477 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 478 479 return ret; 480 } 481 482 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap) 483 { 484 if (is_support_sw_smu(adev)) { 485 struct smu_context *smu = &adev->smu; 486 487 *cap = smu_baco_is_support(smu); 488 return 0; 489 } else { 490 void *pp_handle = adev->powerplay.pp_handle; 491 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 492 493 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) { 494 *cap = false; 495 return -ENOENT; 496 } 497 498 return pp_funcs->get_asic_baco_capability(pp_handle, cap); 499 } 500 } 501 502 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 503 { 504 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 505 506 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 507 if (ras && ras->supported) 508 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 509 510 dev_info(adev->dev, "GPU BACO reset\n"); 511 512 if (is_support_sw_smu(adev)) { 513 struct smu_context *smu = &adev->smu; 514 515 if (smu_baco_reset(smu)) 516 return -EIO; 517 } else { 518 void *pp_handle = adev->powerplay.pp_handle; 519 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 520 521 if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state) 522 return -ENOENT; 523 524 /* enter BACO state */ 525 if (pp_funcs->set_asic_baco_state(pp_handle, 1)) 526 return -EIO; 527 528 /* exit BACO state */ 529 if (pp_funcs->set_asic_baco_state(pp_handle, 0)) 530 return -EIO; 531 } 532 533 /* re-enable doorbell interrupt after BACO exit */ 534 if (ras && ras->supported) 535 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 536 537 return 0; 538 } 539 540 static int soc15_mode2_reset(struct amdgpu_device *adev) 541 { 542 if (is_support_sw_smu(adev)) 543 return smu_mode2_reset(&adev->smu); 544 if (!adev->powerplay.pp_funcs || 545 !adev->powerplay.pp_funcs->asic_reset_mode_2) 546 return -ENOENT; 547 548 return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle); 549 } 550 551 static enum amd_reset_method 552 soc15_asic_reset_method(struct amdgpu_device *adev) 553 { 554 bool baco_reset; 555 556 switch (adev->asic_type) { 557 case CHIP_RAVEN: 558 case CHIP_RENOIR: 559 return AMD_RESET_METHOD_MODE2; 560 case CHIP_VEGA10: 561 case CHIP_VEGA12: 562 soc15_asic_get_baco_capability(adev, &baco_reset); 563 break; 564 case CHIP_VEGA20: 565 if (adev->psp.sos_fw_version >= 0x80067) 566 soc15_asic_get_baco_capability(adev, &baco_reset); 567 else 568 baco_reset = false; 569 if (baco_reset) { 570 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0); 571 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 572 573 if (hive || (ras && ras->supported)) 574 baco_reset = false; 575 } 576 break; 577 default: 578 baco_reset = false; 579 break; 580 } 581 582 if (baco_reset) 583 return AMD_RESET_METHOD_BACO; 584 else 585 return AMD_RESET_METHOD_MODE1; 586 } 587 588 static int soc15_asic_reset(struct amdgpu_device *adev) 589 { 590 switch (soc15_asic_reset_method(adev)) { 591 case AMD_RESET_METHOD_BACO: 592 if (!adev->in_suspend) 593 amdgpu_inc_vram_lost(adev); 594 return soc15_asic_baco_reset(adev); 595 case AMD_RESET_METHOD_MODE2: 596 return soc15_mode2_reset(adev); 597 default: 598 if (!adev->in_suspend) 599 amdgpu_inc_vram_lost(adev); 600 return soc15_asic_mode1_reset(adev); 601 } 602 } 603 604 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 605 u32 cntl_reg, u32 status_reg) 606 { 607 return 0; 608 }*/ 609 610 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 611 { 612 /*int r; 613 614 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 615 if (r) 616 return r; 617 618 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 619 */ 620 return 0; 621 } 622 623 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 624 { 625 /* todo */ 626 627 return 0; 628 } 629 630 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 631 { 632 if (pci_is_root_bus(adev->pdev->bus)) 633 return; 634 635 if (amdgpu_pcie_gen2 == 0) 636 return; 637 638 if (adev->flags & AMD_IS_APU) 639 return; 640 641 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 642 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 643 return; 644 645 /* todo */ 646 } 647 648 static void soc15_program_aspm(struct amdgpu_device *adev) 649 { 650 651 if (amdgpu_aspm == 0) 652 return; 653 654 /* todo */ 655 } 656 657 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 658 bool enable) 659 { 660 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 661 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 662 } 663 664 static const struct amdgpu_ip_block_version vega10_common_ip_block = 665 { 666 .type = AMD_IP_BLOCK_TYPE_COMMON, 667 .major = 2, 668 .minor = 0, 669 .rev = 0, 670 .funcs = &soc15_common_ip_funcs, 671 }; 672 673 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 674 { 675 return adev->nbio.funcs->get_rev_id(adev); 676 } 677 678 int soc15_set_ip_blocks(struct amdgpu_device *adev) 679 { 680 /* Set IP register base before any HW register access */ 681 switch (adev->asic_type) { 682 case CHIP_VEGA10: 683 case CHIP_VEGA12: 684 case CHIP_RAVEN: 685 case CHIP_RENOIR: 686 vega10_reg_base_init(adev); 687 break; 688 case CHIP_VEGA20: 689 vega20_reg_base_init(adev); 690 break; 691 case CHIP_ARCTURUS: 692 arct_reg_base_init(adev); 693 break; 694 default: 695 return -EINVAL; 696 } 697 698 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 699 adev->gmc.xgmi.supported = true; 700 701 if (adev->flags & AMD_IS_APU) { 702 adev->nbio.funcs = &nbio_v7_0_funcs; 703 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 704 } else if (adev->asic_type == CHIP_VEGA20 || 705 adev->asic_type == CHIP_ARCTURUS) { 706 adev->nbio.funcs = &nbio_v7_4_funcs; 707 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 708 } else { 709 adev->nbio.funcs = &nbio_v6_1_funcs; 710 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 711 } 712 713 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 714 adev->df_funcs = &df_v3_6_funcs; 715 else 716 adev->df_funcs = &df_v1_7_funcs; 717 718 adev->rev_id = soc15_get_rev_id(adev); 719 adev->nbio.funcs->detect_hw_virt(adev); 720 721 if (amdgpu_sriov_vf(adev)) 722 adev->virt.ops = &xgpu_ai_virt_ops; 723 724 switch (adev->asic_type) { 725 case CHIP_VEGA10: 726 case CHIP_VEGA12: 727 case CHIP_VEGA20: 728 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 729 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 730 731 /* For Vega10 SR-IOV, PSP need to be initialized before IH */ 732 if (amdgpu_sriov_vf(adev)) { 733 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 734 if (adev->asic_type == CHIP_VEGA20) 735 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 736 else 737 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 738 } 739 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 740 } else { 741 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 742 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 743 if (adev->asic_type == CHIP_VEGA20) 744 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 745 else 746 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 747 } 748 } 749 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 750 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 751 if (!amdgpu_sriov_vf(adev)) { 752 if (is_support_sw_smu(adev)) 753 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 754 else 755 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 756 } 757 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 758 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 759 #if defined(CONFIG_DRM_AMD_DC) 760 else if (amdgpu_device_has_dc_support(adev)) 761 amdgpu_device_ip_block_add(adev, &dm_ip_block); 762 #endif 763 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { 764 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 765 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 766 } 767 break; 768 case CHIP_RAVEN: 769 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 770 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 771 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 772 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 773 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 774 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 775 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 776 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 777 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 778 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 779 #if defined(CONFIG_DRM_AMD_DC) 780 else if (amdgpu_device_has_dc_support(adev)) 781 amdgpu_device_ip_block_add(adev, &dm_ip_block); 782 #endif 783 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 784 break; 785 case CHIP_ARCTURUS: 786 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 787 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 788 789 if (amdgpu_sriov_vf(adev)) { 790 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 791 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 792 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 793 } else { 794 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 795 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 796 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 797 } 798 799 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 800 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 801 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 802 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 803 if (!amdgpu_sriov_vf(adev)) 804 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 805 806 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) 807 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 808 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 809 break; 810 case CHIP_RENOIR: 811 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 812 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 813 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 814 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 815 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 816 if (is_support_sw_smu(adev)) 817 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 818 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 819 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 820 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 821 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 822 #if defined(CONFIG_DRM_AMD_DC) 823 else if (amdgpu_device_has_dc_support(adev)) 824 amdgpu_device_ip_block_add(adev, &dm_ip_block); 825 #endif 826 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 827 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 828 break; 829 default: 830 return -EINVAL; 831 } 832 833 return 0; 834 } 835 836 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 837 { 838 adev->nbio.funcs->hdp_flush(adev, ring); 839 } 840 841 static void soc15_invalidate_hdp(struct amdgpu_device *adev, 842 struct amdgpu_ring *ring) 843 { 844 if (!ring || !ring->funcs->emit_wreg) 845 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 846 else 847 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 848 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 849 } 850 851 static bool soc15_need_full_reset(struct amdgpu_device *adev) 852 { 853 /* change this when we implement soft reset */ 854 return true; 855 } 856 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 857 uint64_t *count1) 858 { 859 uint32_t perfctr = 0; 860 uint64_t cnt0_of, cnt1_of; 861 int tmp; 862 863 /* This reports 0 on APUs, so return to avoid writing/reading registers 864 * that may or may not be different from their GPU counterparts 865 */ 866 if (adev->flags & AMD_IS_APU) 867 return; 868 869 /* Set the 2 events that we wish to watch, defined above */ 870 /* Reg 40 is # received msgs */ 871 /* Reg 104 is # of posted requests sent */ 872 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 873 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 874 875 /* Write to enable desired perf counters */ 876 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 877 /* Zero out and enable the perf counters 878 * Write 0x5: 879 * Bit 0 = Start all counters(1) 880 * Bit 2 = Global counter reset enable(1) 881 */ 882 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 883 884 msleep(1000); 885 886 /* Load the shadow and disable the perf counters 887 * Write 0x2: 888 * Bit 0 = Stop counters(0) 889 * Bit 1 = Load the shadow counters(1) 890 */ 891 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 892 893 /* Read register values to get any >32bit overflow */ 894 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 895 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 896 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 897 898 /* Get the values and add the overflow */ 899 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 900 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 901 } 902 903 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 904 uint64_t *count1) 905 { 906 uint32_t perfctr = 0; 907 uint64_t cnt0_of, cnt1_of; 908 int tmp; 909 910 /* This reports 0 on APUs, so return to avoid writing/reading registers 911 * that may or may not be different from their GPU counterparts 912 */ 913 if (adev->flags & AMD_IS_APU) 914 return; 915 916 /* Set the 2 events that we wish to watch, defined above */ 917 /* Reg 40 is # received msgs */ 918 /* Reg 108 is # of posted requests sent on VG20 */ 919 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 920 EVENT0_SEL, 40); 921 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 922 EVENT1_SEL, 108); 923 924 /* Write to enable desired perf counters */ 925 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 926 /* Zero out and enable the perf counters 927 * Write 0x5: 928 * Bit 0 = Start all counters(1) 929 * Bit 2 = Global counter reset enable(1) 930 */ 931 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 932 933 msleep(1000); 934 935 /* Load the shadow and disable the perf counters 936 * Write 0x2: 937 * Bit 0 = Stop counters(0) 938 * Bit 1 = Load the shadow counters(1) 939 */ 940 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 941 942 /* Read register values to get any >32bit overflow */ 943 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 944 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 945 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 946 947 /* Get the values and add the overflow */ 948 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 949 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 950 } 951 952 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 953 { 954 u32 sol_reg; 955 956 /* Just return false for soc15 GPUs. Reset does not seem to 957 * be necessary. 958 */ 959 if (!amdgpu_passthrough(adev)) 960 return false; 961 962 if (adev->flags & AMD_IS_APU) 963 return false; 964 965 /* Check sOS sign of life register to confirm sys driver and sOS 966 * are already been loaded. 967 */ 968 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 969 if (sol_reg) 970 return true; 971 972 return false; 973 } 974 975 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 976 { 977 uint64_t nak_r, nak_g; 978 979 /* Get the number of NAKs received and generated */ 980 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 981 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 982 983 /* Add the total number of NAKs, i.e the number of replays */ 984 return (nak_r + nak_g); 985 } 986 987 static const struct amdgpu_asic_funcs soc15_asic_funcs = 988 { 989 .read_disabled_bios = &soc15_read_disabled_bios, 990 .read_bios_from_rom = &soc15_read_bios_from_rom, 991 .read_register = &soc15_read_register, 992 .reset = &soc15_asic_reset, 993 .reset_method = &soc15_asic_reset_method, 994 .set_vga_state = &soc15_vga_set_state, 995 .get_xclk = &soc15_get_xclk, 996 .set_uvd_clocks = &soc15_set_uvd_clocks, 997 .set_vce_clocks = &soc15_set_vce_clocks, 998 .get_config_memsize = &soc15_get_config_memsize, 999 .flush_hdp = &soc15_flush_hdp, 1000 .invalidate_hdp = &soc15_invalidate_hdp, 1001 .need_full_reset = &soc15_need_full_reset, 1002 .init_doorbell_index = &vega10_doorbell_index_init, 1003 .get_pcie_usage = &soc15_get_pcie_usage, 1004 .need_reset_on_init = &soc15_need_reset_on_init, 1005 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1006 }; 1007 1008 static const struct amdgpu_asic_funcs vega20_asic_funcs = 1009 { 1010 .read_disabled_bios = &soc15_read_disabled_bios, 1011 .read_bios_from_rom = &soc15_read_bios_from_rom, 1012 .read_register = &soc15_read_register, 1013 .reset = &soc15_asic_reset, 1014 .reset_method = &soc15_asic_reset_method, 1015 .set_vga_state = &soc15_vga_set_state, 1016 .get_xclk = &soc15_get_xclk, 1017 .set_uvd_clocks = &soc15_set_uvd_clocks, 1018 .set_vce_clocks = &soc15_set_vce_clocks, 1019 .get_config_memsize = &soc15_get_config_memsize, 1020 .flush_hdp = &soc15_flush_hdp, 1021 .invalidate_hdp = &soc15_invalidate_hdp, 1022 .need_full_reset = &soc15_need_full_reset, 1023 .init_doorbell_index = &vega20_doorbell_index_init, 1024 .get_pcie_usage = &vega20_get_pcie_usage, 1025 .need_reset_on_init = &soc15_need_reset_on_init, 1026 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1027 }; 1028 1029 static int soc15_common_early_init(void *handle) 1030 { 1031 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 1032 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1033 1034 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 1035 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 1036 adev->smc_rreg = NULL; 1037 adev->smc_wreg = NULL; 1038 adev->pcie_rreg = &soc15_pcie_rreg; 1039 adev->pcie_wreg = &soc15_pcie_wreg; 1040 adev->pcie_rreg64 = &soc15_pcie_rreg64; 1041 adev->pcie_wreg64 = &soc15_pcie_wreg64; 1042 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 1043 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 1044 adev->didt_rreg = &soc15_didt_rreg; 1045 adev->didt_wreg = &soc15_didt_wreg; 1046 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 1047 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 1048 adev->se_cac_rreg = &soc15_se_cac_rreg; 1049 adev->se_cac_wreg = &soc15_se_cac_wreg; 1050 1051 1052 adev->external_rev_id = 0xFF; 1053 switch (adev->asic_type) { 1054 case CHIP_VEGA10: 1055 adev->asic_funcs = &soc15_asic_funcs; 1056 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1057 AMD_CG_SUPPORT_GFX_MGLS | 1058 AMD_CG_SUPPORT_GFX_RLC_LS | 1059 AMD_CG_SUPPORT_GFX_CP_LS | 1060 AMD_CG_SUPPORT_GFX_3D_CGCG | 1061 AMD_CG_SUPPORT_GFX_3D_CGLS | 1062 AMD_CG_SUPPORT_GFX_CGCG | 1063 AMD_CG_SUPPORT_GFX_CGLS | 1064 AMD_CG_SUPPORT_BIF_MGCG | 1065 AMD_CG_SUPPORT_BIF_LS | 1066 AMD_CG_SUPPORT_HDP_LS | 1067 AMD_CG_SUPPORT_DRM_MGCG | 1068 AMD_CG_SUPPORT_DRM_LS | 1069 AMD_CG_SUPPORT_ROM_MGCG | 1070 AMD_CG_SUPPORT_DF_MGCG | 1071 AMD_CG_SUPPORT_SDMA_MGCG | 1072 AMD_CG_SUPPORT_SDMA_LS | 1073 AMD_CG_SUPPORT_MC_MGCG | 1074 AMD_CG_SUPPORT_MC_LS; 1075 adev->pg_flags = 0; 1076 adev->external_rev_id = 0x1; 1077 break; 1078 case CHIP_VEGA12: 1079 adev->asic_funcs = &soc15_asic_funcs; 1080 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1081 AMD_CG_SUPPORT_GFX_MGLS | 1082 AMD_CG_SUPPORT_GFX_CGCG | 1083 AMD_CG_SUPPORT_GFX_CGLS | 1084 AMD_CG_SUPPORT_GFX_3D_CGCG | 1085 AMD_CG_SUPPORT_GFX_3D_CGLS | 1086 AMD_CG_SUPPORT_GFX_CP_LS | 1087 AMD_CG_SUPPORT_MC_LS | 1088 AMD_CG_SUPPORT_MC_MGCG | 1089 AMD_CG_SUPPORT_SDMA_MGCG | 1090 AMD_CG_SUPPORT_SDMA_LS | 1091 AMD_CG_SUPPORT_BIF_MGCG | 1092 AMD_CG_SUPPORT_BIF_LS | 1093 AMD_CG_SUPPORT_HDP_MGCG | 1094 AMD_CG_SUPPORT_HDP_LS | 1095 AMD_CG_SUPPORT_ROM_MGCG | 1096 AMD_CG_SUPPORT_VCE_MGCG | 1097 AMD_CG_SUPPORT_UVD_MGCG; 1098 adev->pg_flags = 0; 1099 adev->external_rev_id = adev->rev_id + 0x14; 1100 break; 1101 case CHIP_VEGA20: 1102 adev->asic_funcs = &vega20_asic_funcs; 1103 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1104 AMD_CG_SUPPORT_GFX_MGLS | 1105 AMD_CG_SUPPORT_GFX_CGCG | 1106 AMD_CG_SUPPORT_GFX_CGLS | 1107 AMD_CG_SUPPORT_GFX_3D_CGCG | 1108 AMD_CG_SUPPORT_GFX_3D_CGLS | 1109 AMD_CG_SUPPORT_GFX_CP_LS | 1110 AMD_CG_SUPPORT_MC_LS | 1111 AMD_CG_SUPPORT_MC_MGCG | 1112 AMD_CG_SUPPORT_SDMA_MGCG | 1113 AMD_CG_SUPPORT_SDMA_LS | 1114 AMD_CG_SUPPORT_BIF_MGCG | 1115 AMD_CG_SUPPORT_BIF_LS | 1116 AMD_CG_SUPPORT_HDP_MGCG | 1117 AMD_CG_SUPPORT_HDP_LS | 1118 AMD_CG_SUPPORT_ROM_MGCG | 1119 AMD_CG_SUPPORT_VCE_MGCG | 1120 AMD_CG_SUPPORT_UVD_MGCG; 1121 adev->pg_flags = 0; 1122 adev->external_rev_id = adev->rev_id + 0x28; 1123 break; 1124 case CHIP_RAVEN: 1125 adev->asic_funcs = &soc15_asic_funcs; 1126 if (adev->rev_id >= 0x8) 1127 adev->external_rev_id = adev->rev_id + 0x79; 1128 else if (adev->pdev->device == 0x15d8) 1129 adev->external_rev_id = adev->rev_id + 0x41; 1130 else if (adev->rev_id == 1) 1131 adev->external_rev_id = adev->rev_id + 0x20; 1132 else 1133 adev->external_rev_id = adev->rev_id + 0x01; 1134 1135 if (adev->rev_id >= 0x8) { 1136 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1137 AMD_CG_SUPPORT_GFX_MGLS | 1138 AMD_CG_SUPPORT_GFX_CP_LS | 1139 AMD_CG_SUPPORT_GFX_3D_CGCG | 1140 AMD_CG_SUPPORT_GFX_3D_CGLS | 1141 AMD_CG_SUPPORT_GFX_CGCG | 1142 AMD_CG_SUPPORT_GFX_CGLS | 1143 AMD_CG_SUPPORT_BIF_LS | 1144 AMD_CG_SUPPORT_HDP_LS | 1145 AMD_CG_SUPPORT_ROM_MGCG | 1146 AMD_CG_SUPPORT_MC_MGCG | 1147 AMD_CG_SUPPORT_MC_LS | 1148 AMD_CG_SUPPORT_SDMA_MGCG | 1149 AMD_CG_SUPPORT_SDMA_LS | 1150 AMD_CG_SUPPORT_VCN_MGCG; 1151 1152 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1153 AMD_PG_SUPPORT_VCN | 1154 AMD_PG_SUPPORT_VCN_DPG; 1155 } else if (adev->pdev->device == 0x15d8) { 1156 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1157 AMD_CG_SUPPORT_GFX_MGLS | 1158 AMD_CG_SUPPORT_GFX_CP_LS | 1159 AMD_CG_SUPPORT_GFX_3D_CGCG | 1160 AMD_CG_SUPPORT_GFX_3D_CGLS | 1161 AMD_CG_SUPPORT_GFX_CGCG | 1162 AMD_CG_SUPPORT_GFX_CGLS | 1163 AMD_CG_SUPPORT_BIF_LS | 1164 AMD_CG_SUPPORT_HDP_LS | 1165 AMD_CG_SUPPORT_ROM_MGCG | 1166 AMD_CG_SUPPORT_MC_MGCG | 1167 AMD_CG_SUPPORT_MC_LS | 1168 AMD_CG_SUPPORT_SDMA_MGCG | 1169 AMD_CG_SUPPORT_SDMA_LS; 1170 1171 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1172 AMD_PG_SUPPORT_MMHUB | 1173 AMD_PG_SUPPORT_VCN | 1174 AMD_PG_SUPPORT_VCN_DPG; 1175 } else { 1176 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1177 AMD_CG_SUPPORT_GFX_MGLS | 1178 AMD_CG_SUPPORT_GFX_RLC_LS | 1179 AMD_CG_SUPPORT_GFX_CP_LS | 1180 AMD_CG_SUPPORT_GFX_3D_CGCG | 1181 AMD_CG_SUPPORT_GFX_3D_CGLS | 1182 AMD_CG_SUPPORT_GFX_CGCG | 1183 AMD_CG_SUPPORT_GFX_CGLS | 1184 AMD_CG_SUPPORT_BIF_MGCG | 1185 AMD_CG_SUPPORT_BIF_LS | 1186 AMD_CG_SUPPORT_HDP_MGCG | 1187 AMD_CG_SUPPORT_HDP_LS | 1188 AMD_CG_SUPPORT_DRM_MGCG | 1189 AMD_CG_SUPPORT_DRM_LS | 1190 AMD_CG_SUPPORT_ROM_MGCG | 1191 AMD_CG_SUPPORT_MC_MGCG | 1192 AMD_CG_SUPPORT_MC_LS | 1193 AMD_CG_SUPPORT_SDMA_MGCG | 1194 AMD_CG_SUPPORT_SDMA_LS | 1195 AMD_CG_SUPPORT_VCN_MGCG; 1196 1197 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1198 AMD_PG_SUPPORT_VCN | 1199 AMD_PG_SUPPORT_VCN_DPG; 1200 } 1201 break; 1202 case CHIP_ARCTURUS: 1203 adev->asic_funcs = &vega20_asic_funcs; 1204 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1205 AMD_CG_SUPPORT_GFX_MGLS | 1206 AMD_CG_SUPPORT_GFX_CGCG | 1207 AMD_CG_SUPPORT_GFX_CGLS | 1208 AMD_CG_SUPPORT_GFX_CP_LS | 1209 AMD_CG_SUPPORT_HDP_MGCG | 1210 AMD_CG_SUPPORT_HDP_LS | 1211 AMD_CG_SUPPORT_SDMA_MGCG | 1212 AMD_CG_SUPPORT_SDMA_LS | 1213 AMD_CG_SUPPORT_MC_MGCG | 1214 AMD_CG_SUPPORT_MC_LS | 1215 AMD_CG_SUPPORT_IH_CG | 1216 AMD_CG_SUPPORT_VCN_MGCG | 1217 AMD_CG_SUPPORT_JPEG_MGCG; 1218 adev->pg_flags = 0; 1219 adev->external_rev_id = adev->rev_id + 0x32; 1220 break; 1221 case CHIP_RENOIR: 1222 adev->asic_funcs = &soc15_asic_funcs; 1223 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1224 AMD_CG_SUPPORT_GFX_MGLS | 1225 AMD_CG_SUPPORT_GFX_3D_CGCG | 1226 AMD_CG_SUPPORT_GFX_3D_CGLS | 1227 AMD_CG_SUPPORT_GFX_CGCG | 1228 AMD_CG_SUPPORT_GFX_CGLS | 1229 AMD_CG_SUPPORT_GFX_CP_LS | 1230 AMD_CG_SUPPORT_MC_MGCG | 1231 AMD_CG_SUPPORT_MC_LS | 1232 AMD_CG_SUPPORT_SDMA_MGCG | 1233 AMD_CG_SUPPORT_SDMA_LS | 1234 AMD_CG_SUPPORT_BIF_LS | 1235 AMD_CG_SUPPORT_HDP_LS | 1236 AMD_CG_SUPPORT_ROM_MGCG | 1237 AMD_CG_SUPPORT_VCN_MGCG | 1238 AMD_CG_SUPPORT_JPEG_MGCG | 1239 AMD_CG_SUPPORT_IH_CG | 1240 AMD_CG_SUPPORT_ATHUB_LS | 1241 AMD_CG_SUPPORT_ATHUB_MGCG | 1242 AMD_CG_SUPPORT_DF_MGCG; 1243 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1244 AMD_PG_SUPPORT_VCN | 1245 AMD_PG_SUPPORT_JPEG | 1246 AMD_PG_SUPPORT_VCN_DPG; 1247 adev->external_rev_id = adev->rev_id + 0x91; 1248 break; 1249 default: 1250 /* FIXME: not supported yet */ 1251 return -EINVAL; 1252 } 1253 1254 if (amdgpu_sriov_vf(adev)) { 1255 amdgpu_virt_init_setting(adev); 1256 xgpu_ai_mailbox_set_irq_funcs(adev); 1257 } 1258 1259 return 0; 1260 } 1261 1262 static int soc15_common_late_init(void *handle) 1263 { 1264 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1265 int r = 0; 1266 1267 if (amdgpu_sriov_vf(adev)) 1268 xgpu_ai_mailbox_get_irq(adev); 1269 1270 if (adev->nbio.funcs->ras_late_init) 1271 r = adev->nbio.funcs->ras_late_init(adev); 1272 1273 return r; 1274 } 1275 1276 static int soc15_common_sw_init(void *handle) 1277 { 1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1279 1280 if (amdgpu_sriov_vf(adev)) 1281 xgpu_ai_mailbox_add_irq_id(adev); 1282 1283 adev->df_funcs->sw_init(adev); 1284 1285 return 0; 1286 } 1287 1288 static int soc15_common_sw_fini(void *handle) 1289 { 1290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1291 1292 amdgpu_nbio_ras_fini(adev); 1293 adev->df_funcs->sw_fini(adev); 1294 return 0; 1295 } 1296 1297 static void soc15_doorbell_range_init(struct amdgpu_device *adev) 1298 { 1299 int i; 1300 struct amdgpu_ring *ring; 1301 1302 /* sdma/ih doorbell range are programed by hypervisor */ 1303 if (!amdgpu_sriov_vf(adev)) { 1304 for (i = 0; i < adev->sdma.num_instances; i++) { 1305 ring = &adev->sdma.instance[i].ring; 1306 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1307 ring->use_doorbell, ring->doorbell_index, 1308 adev->doorbell_index.sdma_doorbell_range); 1309 } 1310 1311 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 1312 adev->irq.ih.doorbell_index); 1313 } 1314 } 1315 1316 static int soc15_common_hw_init(void *handle) 1317 { 1318 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1319 1320 /* enable pcie gen2/3 link */ 1321 soc15_pcie_gen3_enable(adev); 1322 /* enable aspm */ 1323 soc15_program_aspm(adev); 1324 /* setup nbio registers */ 1325 adev->nbio.funcs->init_registers(adev); 1326 /* remap HDP registers to a hole in mmio space, 1327 * for the purpose of expose those registers 1328 * to process space 1329 */ 1330 if (adev->nbio.funcs->remap_hdp_registers) 1331 adev->nbio.funcs->remap_hdp_registers(adev); 1332 1333 /* enable the doorbell aperture */ 1334 soc15_enable_doorbell_aperture(adev, true); 1335 /* HW doorbell routing policy: doorbell writing not 1336 * in SDMA/IH/MM/ACV range will be routed to CP. So 1337 * we need to init SDMA/IH/MM/ACV doorbell range prior 1338 * to CP ip block init and ring test. 1339 */ 1340 soc15_doorbell_range_init(adev); 1341 1342 return 0; 1343 } 1344 1345 static int soc15_common_hw_fini(void *handle) 1346 { 1347 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1348 1349 /* disable the doorbell aperture */ 1350 soc15_enable_doorbell_aperture(adev, false); 1351 if (amdgpu_sriov_vf(adev)) 1352 xgpu_ai_mailbox_put_irq(adev); 1353 1354 if (adev->nbio.ras_if && 1355 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1356 if (adev->nbio.funcs->init_ras_controller_interrupt) 1357 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1358 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) 1359 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1360 } 1361 1362 return 0; 1363 } 1364 1365 static int soc15_common_suspend(void *handle) 1366 { 1367 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1368 1369 return soc15_common_hw_fini(adev); 1370 } 1371 1372 static int soc15_common_resume(void *handle) 1373 { 1374 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1375 1376 return soc15_common_hw_init(adev); 1377 } 1378 1379 static bool soc15_common_is_idle(void *handle) 1380 { 1381 return true; 1382 } 1383 1384 static int soc15_common_wait_for_idle(void *handle) 1385 { 1386 return 0; 1387 } 1388 1389 static int soc15_common_soft_reset(void *handle) 1390 { 1391 return 0; 1392 } 1393 1394 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) 1395 { 1396 uint32_t def, data; 1397 1398 if (adev->asic_type == CHIP_VEGA20 || 1399 adev->asic_type == CHIP_ARCTURUS) { 1400 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); 1401 1402 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1403 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1404 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1405 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1406 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; 1407 else 1408 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1409 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1410 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1411 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); 1412 1413 if (def != data) 1414 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); 1415 } else { 1416 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1417 1418 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1419 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1420 else 1421 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1422 1423 if (def != data) 1424 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 1425 } 1426 } 1427 1428 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1429 { 1430 uint32_t def, data; 1431 1432 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1433 1434 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1435 data &= ~(0x01000000 | 1436 0x02000000 | 1437 0x04000000 | 1438 0x08000000 | 1439 0x10000000 | 1440 0x20000000 | 1441 0x40000000 | 1442 0x80000000); 1443 else 1444 data |= (0x01000000 | 1445 0x02000000 | 1446 0x04000000 | 1447 0x08000000 | 1448 0x10000000 | 1449 0x20000000 | 1450 0x40000000 | 1451 0x80000000); 1452 1453 if (def != data) 1454 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1455 } 1456 1457 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1458 { 1459 uint32_t def, data; 1460 1461 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1462 1463 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1464 data |= 1; 1465 else 1466 data &= ~1; 1467 1468 if (def != data) 1469 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1470 } 1471 1472 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1473 bool enable) 1474 { 1475 uint32_t def, data; 1476 1477 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1478 1479 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1480 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1481 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1482 else 1483 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1484 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1485 1486 if (def != data) 1487 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); 1488 } 1489 1490 static int soc15_common_set_clockgating_state(void *handle, 1491 enum amd_clockgating_state state) 1492 { 1493 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1494 1495 if (amdgpu_sriov_vf(adev)) 1496 return 0; 1497 1498 switch (adev->asic_type) { 1499 case CHIP_VEGA10: 1500 case CHIP_VEGA12: 1501 case CHIP_VEGA20: 1502 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1503 state == AMD_CG_STATE_GATE ? true : false); 1504 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1505 state == AMD_CG_STATE_GATE ? true : false); 1506 soc15_update_hdp_light_sleep(adev, 1507 state == AMD_CG_STATE_GATE ? true : false); 1508 soc15_update_drm_clock_gating(adev, 1509 state == AMD_CG_STATE_GATE ? true : false); 1510 soc15_update_drm_light_sleep(adev, 1511 state == AMD_CG_STATE_GATE ? true : false); 1512 soc15_update_rom_medium_grain_clock_gating(adev, 1513 state == AMD_CG_STATE_GATE ? true : false); 1514 adev->df_funcs->update_medium_grain_clock_gating(adev, 1515 state == AMD_CG_STATE_GATE ? true : false); 1516 break; 1517 case CHIP_RAVEN: 1518 case CHIP_RENOIR: 1519 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1520 state == AMD_CG_STATE_GATE ? true : false); 1521 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1522 state == AMD_CG_STATE_GATE ? true : false); 1523 soc15_update_hdp_light_sleep(adev, 1524 state == AMD_CG_STATE_GATE ? true : false); 1525 soc15_update_drm_clock_gating(adev, 1526 state == AMD_CG_STATE_GATE ? true : false); 1527 soc15_update_drm_light_sleep(adev, 1528 state == AMD_CG_STATE_GATE ? true : false); 1529 soc15_update_rom_medium_grain_clock_gating(adev, 1530 state == AMD_CG_STATE_GATE ? true : false); 1531 break; 1532 case CHIP_ARCTURUS: 1533 soc15_update_hdp_light_sleep(adev, 1534 state == AMD_CG_STATE_GATE ? true : false); 1535 break; 1536 default: 1537 break; 1538 } 1539 return 0; 1540 } 1541 1542 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1543 { 1544 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1545 int data; 1546 1547 if (amdgpu_sriov_vf(adev)) 1548 *flags = 0; 1549 1550 adev->nbio.funcs->get_clockgating_state(adev, flags); 1551 1552 /* AMD_CG_SUPPORT_HDP_LS */ 1553 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1554 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 1555 *flags |= AMD_CG_SUPPORT_HDP_LS; 1556 1557 /* AMD_CG_SUPPORT_DRM_MGCG */ 1558 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1559 if (!(data & 0x01000000)) 1560 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1561 1562 /* AMD_CG_SUPPORT_DRM_LS */ 1563 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1564 if (data & 0x1) 1565 *flags |= AMD_CG_SUPPORT_DRM_LS; 1566 1567 /* AMD_CG_SUPPORT_ROM_MGCG */ 1568 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1569 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 1570 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 1571 1572 adev->df_funcs->get_clockgating_state(adev, flags); 1573 } 1574 1575 static int soc15_common_set_powergating_state(void *handle, 1576 enum amd_powergating_state state) 1577 { 1578 /* todo */ 1579 return 0; 1580 } 1581 1582 const struct amd_ip_funcs soc15_common_ip_funcs = { 1583 .name = "soc15_common", 1584 .early_init = soc15_common_early_init, 1585 .late_init = soc15_common_late_init, 1586 .sw_init = soc15_common_sw_init, 1587 .sw_fini = soc15_common_sw_fini, 1588 .hw_init = soc15_common_hw_init, 1589 .hw_fini = soc15_common_hw_fini, 1590 .suspend = soc15_common_suspend, 1591 .resume = soc15_common_resume, 1592 .is_idle = soc15_common_is_idle, 1593 .wait_for_idle = soc15_common_wait_for_idle, 1594 .soft_reset = soc15_common_soft_reset, 1595 .set_clockgating_state = soc15_common_set_clockgating_state, 1596 .set_powergating_state = soc15_common_set_powergating_state, 1597 .get_clockgating_state= soc15_common_get_clockgating_state, 1598 }; 1599