1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_atombios.h" 29 #include "amdgpu_ih.h" 30 #include "amdgpu_uvd.h" 31 #include "amdgpu_vce.h" 32 #include "amdgpu_ucode.h" 33 #include "amdgpu_psp.h" 34 #include "atom.h" 35 #include "amd_pcie.h" 36 37 #include "uvd/uvd_7_0_offset.h" 38 #include "gc/gc_9_0_offset.h" 39 #include "gc/gc_9_0_sh_mask.h" 40 #include "sdma0/sdma0_4_0_offset.h" 41 #include "sdma1/sdma1_4_0_offset.h" 42 #include "hdp/hdp_4_0_offset.h" 43 #include "hdp/hdp_4_0_sh_mask.h" 44 #include "smuio/smuio_9_0_offset.h" 45 #include "smuio/smuio_9_0_sh_mask.h" 46 47 #include "soc15.h" 48 #include "soc15_common.h" 49 #include "gfx_v9_0.h" 50 #include "gmc_v9_0.h" 51 #include "gfxhub_v1_0.h" 52 #include "mmhub_v1_0.h" 53 #include "df_v1_7.h" 54 #include "df_v3_6.h" 55 #include "vega10_ih.h" 56 #include "sdma_v4_0.h" 57 #include "uvd_v7_0.h" 58 #include "vce_v4_0.h" 59 #include "vcn_v1_0.h" 60 #include "dce_virtual.h" 61 #include "mxgpu_ai.h" 62 63 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 64 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 65 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 66 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 67 68 /* 69 * Indirect registers accessor 70 */ 71 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 72 { 73 unsigned long flags, address, data; 74 u32 r; 75 address = adev->nbio_funcs->get_pcie_index_offset(adev); 76 data = adev->nbio_funcs->get_pcie_data_offset(adev); 77 78 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 79 WREG32(address, reg); 80 (void)RREG32(address); 81 r = RREG32(data); 82 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 83 return r; 84 } 85 86 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 87 { 88 unsigned long flags, address, data; 89 90 address = adev->nbio_funcs->get_pcie_index_offset(adev); 91 data = adev->nbio_funcs->get_pcie_data_offset(adev); 92 93 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 94 WREG32(address, reg); 95 (void)RREG32(address); 96 WREG32(data, v); 97 (void)RREG32(data); 98 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 99 } 100 101 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 102 { 103 unsigned long flags, address, data; 104 u32 r; 105 106 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 107 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 108 109 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 110 WREG32(address, ((reg) & 0x1ff)); 111 r = RREG32(data); 112 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 113 return r; 114 } 115 116 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 117 { 118 unsigned long flags, address, data; 119 120 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 121 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 122 123 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 124 WREG32(address, ((reg) & 0x1ff)); 125 WREG32(data, (v)); 126 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 127 } 128 129 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 130 { 131 unsigned long flags, address, data; 132 u32 r; 133 134 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 135 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 136 137 spin_lock_irqsave(&adev->didt_idx_lock, flags); 138 WREG32(address, (reg)); 139 r = RREG32(data); 140 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 141 return r; 142 } 143 144 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 145 { 146 unsigned long flags, address, data; 147 148 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 149 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 150 151 spin_lock_irqsave(&adev->didt_idx_lock, flags); 152 WREG32(address, (reg)); 153 WREG32(data, (v)); 154 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 155 } 156 157 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 158 { 159 unsigned long flags; 160 u32 r; 161 162 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 163 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 164 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 165 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 166 return r; 167 } 168 169 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 170 { 171 unsigned long flags; 172 173 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 174 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 175 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 176 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 177 } 178 179 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 180 { 181 unsigned long flags; 182 u32 r; 183 184 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 185 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 186 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 187 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 188 return r; 189 } 190 191 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 192 { 193 unsigned long flags; 194 195 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 196 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 197 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 198 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 199 } 200 201 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 202 { 203 return adev->nbio_funcs->get_memsize(adev); 204 } 205 206 static u32 soc15_get_xclk(struct amdgpu_device *adev) 207 { 208 return adev->clock.spll.reference_freq; 209 } 210 211 212 void soc15_grbm_select(struct amdgpu_device *adev, 213 u32 me, u32 pipe, u32 queue, u32 vmid) 214 { 215 u32 grbm_gfx_cntl = 0; 216 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 217 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 218 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 219 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 220 221 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 222 } 223 224 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 225 { 226 /* todo */ 227 } 228 229 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 230 { 231 /* todo */ 232 return false; 233 } 234 235 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 236 u8 *bios, u32 length_bytes) 237 { 238 u32 *dw_ptr; 239 u32 i, length_dw; 240 241 if (bios == NULL) 242 return false; 243 if (length_bytes == 0) 244 return false; 245 /* APU vbios image is part of sbios image */ 246 if (adev->flags & AMD_IS_APU) 247 return false; 248 249 dw_ptr = (u32 *)bios; 250 length_dw = ALIGN(length_bytes, 4) / 4; 251 252 /* set rom index to 0 */ 253 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 254 /* read out the rom data */ 255 for (i = 0; i < length_dw; i++) 256 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 257 258 return true; 259 } 260 261 struct soc15_allowed_register_entry { 262 uint32_t hwip; 263 uint32_t inst; 264 uint32_t seg; 265 uint32_t reg_offset; 266 bool grbm_indexed; 267 }; 268 269 270 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 271 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 272 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 273 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 274 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 275 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 276 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 277 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 278 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 279 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 280 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 281 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 282 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 283 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 284 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 285 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 286 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 287 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 288 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 289 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 290 }; 291 292 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 293 u32 sh_num, u32 reg_offset) 294 { 295 uint32_t val; 296 297 mutex_lock(&adev->grbm_idx_mutex); 298 if (se_num != 0xffffffff || sh_num != 0xffffffff) 299 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 300 301 val = RREG32(reg_offset); 302 303 if (se_num != 0xffffffff || sh_num != 0xffffffff) 304 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 305 mutex_unlock(&adev->grbm_idx_mutex); 306 return val; 307 } 308 309 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 310 bool indexed, u32 se_num, 311 u32 sh_num, u32 reg_offset) 312 { 313 if (indexed) { 314 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 315 } else { 316 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 317 return adev->gfx.config.gb_addr_config; 318 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 319 return adev->gfx.config.db_debug2; 320 return RREG32(reg_offset); 321 } 322 } 323 324 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 325 u32 sh_num, u32 reg_offset, u32 *value) 326 { 327 uint32_t i; 328 struct soc15_allowed_register_entry *en; 329 330 *value = 0; 331 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 332 en = &soc15_allowed_read_registers[i]; 333 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 334 + en->reg_offset)) 335 continue; 336 337 *value = soc15_get_register_value(adev, 338 soc15_allowed_read_registers[i].grbm_indexed, 339 se_num, sh_num, reg_offset); 340 return 0; 341 } 342 return -EINVAL; 343 } 344 345 346 /** 347 * soc15_program_register_sequence - program an array of registers. 348 * 349 * @adev: amdgpu_device pointer 350 * @regs: pointer to the register array 351 * @array_size: size of the register array 352 * 353 * Programs an array or registers with and and or masks. 354 * This is a helper for setting golden registers. 355 */ 356 357 void soc15_program_register_sequence(struct amdgpu_device *adev, 358 const struct soc15_reg_golden *regs, 359 const u32 array_size) 360 { 361 const struct soc15_reg_golden *entry; 362 u32 tmp, reg; 363 int i; 364 365 for (i = 0; i < array_size; ++i) { 366 entry = ®s[i]; 367 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 368 369 if (entry->and_mask == 0xffffffff) { 370 tmp = entry->or_mask; 371 } else { 372 tmp = RREG32(reg); 373 tmp &= ~(entry->and_mask); 374 tmp |= entry->or_mask; 375 } 376 WREG32(reg, tmp); 377 } 378 379 } 380 381 382 static int soc15_asic_reset(struct amdgpu_device *adev) 383 { 384 u32 i; 385 386 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 387 388 dev_info(adev->dev, "GPU reset\n"); 389 390 /* disable BM */ 391 pci_clear_master(adev->pdev); 392 393 pci_save_state(adev->pdev); 394 395 psp_gpu_reset(adev); 396 397 pci_restore_state(adev->pdev); 398 399 /* wait for asic to come out of reset */ 400 for (i = 0; i < adev->usec_timeout; i++) { 401 u32 memsize = adev->nbio_funcs->get_memsize(adev); 402 403 if (memsize != 0xffffffff) 404 break; 405 udelay(1); 406 } 407 408 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 409 410 return 0; 411 } 412 413 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 414 u32 cntl_reg, u32 status_reg) 415 { 416 return 0; 417 }*/ 418 419 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 420 { 421 /*int r; 422 423 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 424 if (r) 425 return r; 426 427 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 428 */ 429 return 0; 430 } 431 432 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 433 { 434 /* todo */ 435 436 return 0; 437 } 438 439 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 440 { 441 if (pci_is_root_bus(adev->pdev->bus)) 442 return; 443 444 if (amdgpu_pcie_gen2 == 0) 445 return; 446 447 if (adev->flags & AMD_IS_APU) 448 return; 449 450 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 451 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 452 return; 453 454 /* todo */ 455 } 456 457 static void soc15_program_aspm(struct amdgpu_device *adev) 458 { 459 460 if (amdgpu_aspm == 0) 461 return; 462 463 /* todo */ 464 } 465 466 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 467 bool enable) 468 { 469 adev->nbio_funcs->enable_doorbell_aperture(adev, enable); 470 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable); 471 } 472 473 static const struct amdgpu_ip_block_version vega10_common_ip_block = 474 { 475 .type = AMD_IP_BLOCK_TYPE_COMMON, 476 .major = 2, 477 .minor = 0, 478 .rev = 0, 479 .funcs = &soc15_common_ip_funcs, 480 }; 481 482 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 483 { 484 return adev->nbio_funcs->get_rev_id(adev); 485 } 486 487 int soc15_set_ip_blocks(struct amdgpu_device *adev) 488 { 489 /* Set IP register base before any HW register access */ 490 switch (adev->asic_type) { 491 case CHIP_VEGA10: 492 case CHIP_VEGA12: 493 case CHIP_RAVEN: 494 vega10_reg_base_init(adev); 495 break; 496 case CHIP_VEGA20: 497 vega20_reg_base_init(adev); 498 break; 499 default: 500 return -EINVAL; 501 } 502 503 if (adev->asic_type == CHIP_VEGA20) 504 adev->gmc.xgmi.supported = true; 505 506 if (adev->flags & AMD_IS_APU) 507 adev->nbio_funcs = &nbio_v7_0_funcs; 508 else if (adev->asic_type == CHIP_VEGA20) 509 adev->nbio_funcs = &nbio_v7_4_funcs; 510 else 511 adev->nbio_funcs = &nbio_v6_1_funcs; 512 513 if (adev->asic_type == CHIP_VEGA20) 514 adev->df_funcs = &df_v3_6_funcs; 515 else 516 adev->df_funcs = &df_v1_7_funcs; 517 518 adev->rev_id = soc15_get_rev_id(adev); 519 adev->nbio_funcs->detect_hw_virt(adev); 520 521 if (amdgpu_sriov_vf(adev)) 522 adev->virt.ops = &xgpu_ai_virt_ops; 523 524 switch (adev->asic_type) { 525 case CHIP_VEGA10: 526 case CHIP_VEGA12: 527 case CHIP_VEGA20: 528 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 529 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 530 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 531 if (adev->asic_type == CHIP_VEGA20) 532 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 533 else 534 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 535 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 536 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 537 if (!amdgpu_sriov_vf(adev)) 538 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 539 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 540 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 541 #if defined(CONFIG_DRM_AMD_DC) 542 else if (amdgpu_device_has_dc_support(adev)) 543 amdgpu_device_ip_block_add(adev, &dm_ip_block); 544 #else 545 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." 546 #endif 547 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { 548 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 549 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 550 } 551 break; 552 case CHIP_RAVEN: 553 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 554 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 555 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 556 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 557 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 558 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 559 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 560 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 561 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 562 #if defined(CONFIG_DRM_AMD_DC) 563 else if (amdgpu_device_has_dc_support(adev)) 564 amdgpu_device_ip_block_add(adev, &dm_ip_block); 565 #else 566 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." 567 #endif 568 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 569 break; 570 default: 571 return -EINVAL; 572 } 573 574 return 0; 575 } 576 577 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 578 { 579 adev->nbio_funcs->hdp_flush(adev, ring); 580 } 581 582 static void soc15_invalidate_hdp(struct amdgpu_device *adev, 583 struct amdgpu_ring *ring) 584 { 585 if (!ring || !ring->funcs->emit_wreg) 586 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 587 else 588 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 589 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 590 } 591 592 static bool soc15_need_full_reset(struct amdgpu_device *adev) 593 { 594 /* change this when we implement soft reset */ 595 return true; 596 } 597 598 static const struct amdgpu_asic_funcs soc15_asic_funcs = 599 { 600 .read_disabled_bios = &soc15_read_disabled_bios, 601 .read_bios_from_rom = &soc15_read_bios_from_rom, 602 .read_register = &soc15_read_register, 603 .reset = &soc15_asic_reset, 604 .set_vga_state = &soc15_vga_set_state, 605 .get_xclk = &soc15_get_xclk, 606 .set_uvd_clocks = &soc15_set_uvd_clocks, 607 .set_vce_clocks = &soc15_set_vce_clocks, 608 .get_config_memsize = &soc15_get_config_memsize, 609 .flush_hdp = &soc15_flush_hdp, 610 .invalidate_hdp = &soc15_invalidate_hdp, 611 .need_full_reset = &soc15_need_full_reset, 612 .init_doorbell_index = &vega10_doorbell_index_init, 613 }; 614 615 static const struct amdgpu_asic_funcs vega20_asic_funcs = 616 { 617 .read_disabled_bios = &soc15_read_disabled_bios, 618 .read_bios_from_rom = &soc15_read_bios_from_rom, 619 .read_register = &soc15_read_register, 620 .reset = &soc15_asic_reset, 621 .set_vga_state = &soc15_vga_set_state, 622 .get_xclk = &soc15_get_xclk, 623 .set_uvd_clocks = &soc15_set_uvd_clocks, 624 .set_vce_clocks = &soc15_set_vce_clocks, 625 .get_config_memsize = &soc15_get_config_memsize, 626 .flush_hdp = &soc15_flush_hdp, 627 .invalidate_hdp = &soc15_invalidate_hdp, 628 .need_full_reset = &soc15_need_full_reset, 629 .init_doorbell_index = &vega20_doorbell_index_init, 630 }; 631 632 static int soc15_common_early_init(void *handle) 633 { 634 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 635 636 adev->smc_rreg = NULL; 637 adev->smc_wreg = NULL; 638 adev->pcie_rreg = &soc15_pcie_rreg; 639 adev->pcie_wreg = &soc15_pcie_wreg; 640 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 641 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 642 adev->didt_rreg = &soc15_didt_rreg; 643 adev->didt_wreg = &soc15_didt_wreg; 644 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 645 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 646 adev->se_cac_rreg = &soc15_se_cac_rreg; 647 adev->se_cac_wreg = &soc15_se_cac_wreg; 648 649 650 adev->external_rev_id = 0xFF; 651 switch (adev->asic_type) { 652 case CHIP_VEGA10: 653 adev->asic_funcs = &soc15_asic_funcs; 654 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 655 AMD_CG_SUPPORT_GFX_MGLS | 656 AMD_CG_SUPPORT_GFX_RLC_LS | 657 AMD_CG_SUPPORT_GFX_CP_LS | 658 AMD_CG_SUPPORT_GFX_3D_CGCG | 659 AMD_CG_SUPPORT_GFX_3D_CGLS | 660 AMD_CG_SUPPORT_GFX_CGCG | 661 AMD_CG_SUPPORT_GFX_CGLS | 662 AMD_CG_SUPPORT_BIF_MGCG | 663 AMD_CG_SUPPORT_BIF_LS | 664 AMD_CG_SUPPORT_HDP_LS | 665 AMD_CG_SUPPORT_DRM_MGCG | 666 AMD_CG_SUPPORT_DRM_LS | 667 AMD_CG_SUPPORT_ROM_MGCG | 668 AMD_CG_SUPPORT_DF_MGCG | 669 AMD_CG_SUPPORT_SDMA_MGCG | 670 AMD_CG_SUPPORT_SDMA_LS | 671 AMD_CG_SUPPORT_MC_MGCG | 672 AMD_CG_SUPPORT_MC_LS; 673 adev->pg_flags = 0; 674 adev->external_rev_id = 0x1; 675 break; 676 case CHIP_VEGA12: 677 adev->asic_funcs = &soc15_asic_funcs; 678 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 679 AMD_CG_SUPPORT_GFX_MGLS | 680 AMD_CG_SUPPORT_GFX_CGCG | 681 AMD_CG_SUPPORT_GFX_CGLS | 682 AMD_CG_SUPPORT_GFX_3D_CGCG | 683 AMD_CG_SUPPORT_GFX_3D_CGLS | 684 AMD_CG_SUPPORT_GFX_CP_LS | 685 AMD_CG_SUPPORT_MC_LS | 686 AMD_CG_SUPPORT_MC_MGCG | 687 AMD_CG_SUPPORT_SDMA_MGCG | 688 AMD_CG_SUPPORT_SDMA_LS | 689 AMD_CG_SUPPORT_BIF_MGCG | 690 AMD_CG_SUPPORT_BIF_LS | 691 AMD_CG_SUPPORT_HDP_MGCG | 692 AMD_CG_SUPPORT_HDP_LS | 693 AMD_CG_SUPPORT_ROM_MGCG | 694 AMD_CG_SUPPORT_VCE_MGCG | 695 AMD_CG_SUPPORT_UVD_MGCG; 696 adev->pg_flags = 0; 697 adev->external_rev_id = adev->rev_id + 0x14; 698 break; 699 case CHIP_VEGA20: 700 adev->asic_funcs = &vega20_asic_funcs; 701 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 702 AMD_CG_SUPPORT_GFX_MGLS | 703 AMD_CG_SUPPORT_GFX_CGCG | 704 AMD_CG_SUPPORT_GFX_CGLS | 705 AMD_CG_SUPPORT_GFX_3D_CGCG | 706 AMD_CG_SUPPORT_GFX_3D_CGLS | 707 AMD_CG_SUPPORT_GFX_CP_LS | 708 AMD_CG_SUPPORT_MC_LS | 709 AMD_CG_SUPPORT_MC_MGCG | 710 AMD_CG_SUPPORT_SDMA_MGCG | 711 AMD_CG_SUPPORT_SDMA_LS | 712 AMD_CG_SUPPORT_BIF_MGCG | 713 AMD_CG_SUPPORT_BIF_LS | 714 AMD_CG_SUPPORT_HDP_MGCG | 715 AMD_CG_SUPPORT_HDP_LS | 716 AMD_CG_SUPPORT_ROM_MGCG | 717 AMD_CG_SUPPORT_VCE_MGCG | 718 AMD_CG_SUPPORT_UVD_MGCG; 719 adev->pg_flags = 0; 720 adev->external_rev_id = adev->rev_id + 0x28; 721 break; 722 case CHIP_RAVEN: 723 adev->asic_funcs = &soc15_asic_funcs; 724 if (adev->rev_id >= 0x8) 725 adev->external_rev_id = adev->rev_id + 0x81; 726 else if (adev->pdev->device == 0x15d8) 727 adev->external_rev_id = adev->rev_id + 0x41; 728 else 729 adev->external_rev_id = 0x1; 730 731 if (adev->rev_id >= 0x8) { 732 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 733 AMD_CG_SUPPORT_GFX_MGLS | 734 AMD_CG_SUPPORT_GFX_CP_LS | 735 AMD_CG_SUPPORT_GFX_3D_CGCG | 736 AMD_CG_SUPPORT_GFX_3D_CGLS | 737 AMD_CG_SUPPORT_GFX_CGCG | 738 AMD_CG_SUPPORT_GFX_CGLS | 739 AMD_CG_SUPPORT_BIF_LS | 740 AMD_CG_SUPPORT_HDP_LS | 741 AMD_CG_SUPPORT_ROM_MGCG | 742 AMD_CG_SUPPORT_MC_MGCG | 743 AMD_CG_SUPPORT_MC_LS | 744 AMD_CG_SUPPORT_SDMA_MGCG | 745 AMD_CG_SUPPORT_SDMA_LS | 746 AMD_CG_SUPPORT_VCN_MGCG; 747 748 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 749 } else if (adev->pdev->device == 0x15d8) { 750 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS | 751 AMD_CG_SUPPORT_GFX_CP_LS | 752 AMD_CG_SUPPORT_GFX_3D_CGCG | 753 AMD_CG_SUPPORT_GFX_3D_CGLS | 754 AMD_CG_SUPPORT_GFX_CGCG | 755 AMD_CG_SUPPORT_GFX_CGLS | 756 AMD_CG_SUPPORT_BIF_LS | 757 AMD_CG_SUPPORT_HDP_LS | 758 AMD_CG_SUPPORT_ROM_MGCG | 759 AMD_CG_SUPPORT_MC_MGCG | 760 AMD_CG_SUPPORT_MC_LS | 761 AMD_CG_SUPPORT_SDMA_MGCG | 762 AMD_CG_SUPPORT_SDMA_LS; 763 764 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 765 AMD_PG_SUPPORT_MMHUB | 766 AMD_PG_SUPPORT_VCN | 767 AMD_PG_SUPPORT_VCN_DPG; 768 } else { 769 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 770 AMD_CG_SUPPORT_GFX_MGLS | 771 AMD_CG_SUPPORT_GFX_RLC_LS | 772 AMD_CG_SUPPORT_GFX_CP_LS | 773 AMD_CG_SUPPORT_GFX_3D_CGCG | 774 AMD_CG_SUPPORT_GFX_3D_CGLS | 775 AMD_CG_SUPPORT_GFX_CGCG | 776 AMD_CG_SUPPORT_GFX_CGLS | 777 AMD_CG_SUPPORT_BIF_MGCG | 778 AMD_CG_SUPPORT_BIF_LS | 779 AMD_CG_SUPPORT_HDP_MGCG | 780 AMD_CG_SUPPORT_HDP_LS | 781 AMD_CG_SUPPORT_DRM_MGCG | 782 AMD_CG_SUPPORT_DRM_LS | 783 AMD_CG_SUPPORT_ROM_MGCG | 784 AMD_CG_SUPPORT_MC_MGCG | 785 AMD_CG_SUPPORT_MC_LS | 786 AMD_CG_SUPPORT_SDMA_MGCG | 787 AMD_CG_SUPPORT_SDMA_LS | 788 AMD_CG_SUPPORT_VCN_MGCG; 789 790 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 791 } 792 793 if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) 794 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 795 AMD_PG_SUPPORT_CP | 796 AMD_PG_SUPPORT_RLC_SMU_HS; 797 break; 798 default: 799 /* FIXME: not supported yet */ 800 return -EINVAL; 801 } 802 803 if (amdgpu_sriov_vf(adev)) { 804 amdgpu_virt_init_setting(adev); 805 xgpu_ai_mailbox_set_irq_funcs(adev); 806 } 807 808 return 0; 809 } 810 811 static int soc15_common_late_init(void *handle) 812 { 813 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 814 815 if (amdgpu_sriov_vf(adev)) 816 xgpu_ai_mailbox_get_irq(adev); 817 818 return 0; 819 } 820 821 static int soc15_common_sw_init(void *handle) 822 { 823 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 824 825 if (amdgpu_sriov_vf(adev)) 826 xgpu_ai_mailbox_add_irq_id(adev); 827 828 return 0; 829 } 830 831 static int soc15_common_sw_fini(void *handle) 832 { 833 return 0; 834 } 835 836 static int soc15_common_hw_init(void *handle) 837 { 838 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 839 840 /* enable pcie gen2/3 link */ 841 soc15_pcie_gen3_enable(adev); 842 /* enable aspm */ 843 soc15_program_aspm(adev); 844 /* setup nbio registers */ 845 adev->nbio_funcs->init_registers(adev); 846 /* enable the doorbell aperture */ 847 soc15_enable_doorbell_aperture(adev, true); 848 849 return 0; 850 } 851 852 static int soc15_common_hw_fini(void *handle) 853 { 854 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 855 856 /* disable the doorbell aperture */ 857 soc15_enable_doorbell_aperture(adev, false); 858 if (amdgpu_sriov_vf(adev)) 859 xgpu_ai_mailbox_put_irq(adev); 860 861 return 0; 862 } 863 864 static int soc15_common_suspend(void *handle) 865 { 866 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 867 868 return soc15_common_hw_fini(adev); 869 } 870 871 static int soc15_common_resume(void *handle) 872 { 873 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 874 875 return soc15_common_hw_init(adev); 876 } 877 878 static bool soc15_common_is_idle(void *handle) 879 { 880 return true; 881 } 882 883 static int soc15_common_wait_for_idle(void *handle) 884 { 885 return 0; 886 } 887 888 static int soc15_common_soft_reset(void *handle) 889 { 890 return 0; 891 } 892 893 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) 894 { 895 uint32_t def, data; 896 897 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 898 899 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 900 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 901 else 902 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 903 904 if (def != data) 905 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 906 } 907 908 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 909 { 910 uint32_t def, data; 911 912 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 913 914 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 915 data &= ~(0x01000000 | 916 0x02000000 | 917 0x04000000 | 918 0x08000000 | 919 0x10000000 | 920 0x20000000 | 921 0x40000000 | 922 0x80000000); 923 else 924 data |= (0x01000000 | 925 0x02000000 | 926 0x04000000 | 927 0x08000000 | 928 0x10000000 | 929 0x20000000 | 930 0x40000000 | 931 0x80000000); 932 933 if (def != data) 934 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 935 } 936 937 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 938 { 939 uint32_t def, data; 940 941 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 942 943 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 944 data |= 1; 945 else 946 data &= ~1; 947 948 if (def != data) 949 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 950 } 951 952 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 953 bool enable) 954 { 955 uint32_t def, data; 956 957 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 958 959 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 960 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 961 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 962 else 963 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 964 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 965 966 if (def != data) 967 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); 968 } 969 970 static int soc15_common_set_clockgating_state(void *handle, 971 enum amd_clockgating_state state) 972 { 973 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 974 975 if (amdgpu_sriov_vf(adev)) 976 return 0; 977 978 switch (adev->asic_type) { 979 case CHIP_VEGA10: 980 case CHIP_VEGA12: 981 case CHIP_VEGA20: 982 adev->nbio_funcs->update_medium_grain_clock_gating(adev, 983 state == AMD_CG_STATE_GATE ? true : false); 984 adev->nbio_funcs->update_medium_grain_light_sleep(adev, 985 state == AMD_CG_STATE_GATE ? true : false); 986 soc15_update_hdp_light_sleep(adev, 987 state == AMD_CG_STATE_GATE ? true : false); 988 soc15_update_drm_clock_gating(adev, 989 state == AMD_CG_STATE_GATE ? true : false); 990 soc15_update_drm_light_sleep(adev, 991 state == AMD_CG_STATE_GATE ? true : false); 992 soc15_update_rom_medium_grain_clock_gating(adev, 993 state == AMD_CG_STATE_GATE ? true : false); 994 adev->df_funcs->update_medium_grain_clock_gating(adev, 995 state == AMD_CG_STATE_GATE ? true : false); 996 break; 997 case CHIP_RAVEN: 998 adev->nbio_funcs->update_medium_grain_clock_gating(adev, 999 state == AMD_CG_STATE_GATE ? true : false); 1000 adev->nbio_funcs->update_medium_grain_light_sleep(adev, 1001 state == AMD_CG_STATE_GATE ? true : false); 1002 soc15_update_hdp_light_sleep(adev, 1003 state == AMD_CG_STATE_GATE ? true : false); 1004 soc15_update_drm_clock_gating(adev, 1005 state == AMD_CG_STATE_GATE ? true : false); 1006 soc15_update_drm_light_sleep(adev, 1007 state == AMD_CG_STATE_GATE ? true : false); 1008 soc15_update_rom_medium_grain_clock_gating(adev, 1009 state == AMD_CG_STATE_GATE ? true : false); 1010 break; 1011 default: 1012 break; 1013 } 1014 return 0; 1015 } 1016 1017 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1018 { 1019 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1020 int data; 1021 1022 if (amdgpu_sriov_vf(adev)) 1023 *flags = 0; 1024 1025 adev->nbio_funcs->get_clockgating_state(adev, flags); 1026 1027 /* AMD_CG_SUPPORT_HDP_LS */ 1028 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1029 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 1030 *flags |= AMD_CG_SUPPORT_HDP_LS; 1031 1032 /* AMD_CG_SUPPORT_DRM_MGCG */ 1033 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1034 if (!(data & 0x01000000)) 1035 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1036 1037 /* AMD_CG_SUPPORT_DRM_LS */ 1038 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1039 if (data & 0x1) 1040 *flags |= AMD_CG_SUPPORT_DRM_LS; 1041 1042 /* AMD_CG_SUPPORT_ROM_MGCG */ 1043 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1044 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 1045 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 1046 1047 adev->df_funcs->get_clockgating_state(adev, flags); 1048 } 1049 1050 static int soc15_common_set_powergating_state(void *handle, 1051 enum amd_powergating_state state) 1052 { 1053 /* todo */ 1054 return 0; 1055 } 1056 1057 const struct amd_ip_funcs soc15_common_ip_funcs = { 1058 .name = "soc15_common", 1059 .early_init = soc15_common_early_init, 1060 .late_init = soc15_common_late_init, 1061 .sw_init = soc15_common_sw_init, 1062 .sw_fini = soc15_common_sw_fini, 1063 .hw_init = soc15_common_hw_init, 1064 .hw_fini = soc15_common_hw_fini, 1065 .suspend = soc15_common_suspend, 1066 .resume = soc15_common_resume, 1067 .is_idle = soc15_common_is_idle, 1068 .wait_for_idle = soc15_common_wait_for_idle, 1069 .soft_reset = soc15_common_soft_reset, 1070 .set_clockgating_state = soc15_common_set_clockgating_state, 1071 .set_powergating_state = soc15_common_set_powergating_state, 1072 .get_clockgating_state= soc15_common_get_clockgating_state, 1073 }; 1074