1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "uvd/uvd_7_0_offset.h" 41 #include "gc/gc_9_0_offset.h" 42 #include "gc/gc_9_0_sh_mask.h" 43 #include "sdma0/sdma0_4_0_offset.h" 44 #include "sdma1/sdma1_4_0_offset.h" 45 #include "nbio/nbio_7_0_default.h" 46 #include "nbio/nbio_7_0_offset.h" 47 #include "nbio/nbio_7_0_sh_mask.h" 48 #include "nbio/nbio_7_0_smn.h" 49 #include "mp/mp_9_0_offset.h" 50 51 #include "soc15.h" 52 #include "soc15_common.h" 53 #include "gfx_v9_0.h" 54 #include "gmc_v9_0.h" 55 #include "gfxhub_v1_0.h" 56 #include "mmhub_v1_0.h" 57 #include "df_v1_7.h" 58 #include "df_v3_6.h" 59 #include "nbio_v6_1.h" 60 #include "nbio_v7_0.h" 61 #include "nbio_v7_4.h" 62 #include "hdp_v4_0.h" 63 #include "vega10_ih.h" 64 #include "vega20_ih.h" 65 #include "navi10_ih.h" 66 #include "sdma_v4_0.h" 67 #include "uvd_v7_0.h" 68 #include "vce_v4_0.h" 69 #include "vcn_v1_0.h" 70 #include "vcn_v2_0.h" 71 #include "jpeg_v2_0.h" 72 #include "vcn_v2_5.h" 73 #include "jpeg_v2_5.h" 74 #include "smuio_v9_0.h" 75 #include "smuio_v11_0.h" 76 #include "smuio_v13_0.h" 77 #include "amdgpu_vkms.h" 78 #include "mxgpu_ai.h" 79 #include "amdgpu_ras.h" 80 #include "amdgpu_xgmi.h" 81 #include <uapi/linux/kfd_ioctl.h> 82 83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 87 88 static const struct amd_ip_funcs soc15_common_ip_funcs; 89 90 /* Vega, Raven, Arcturus */ 91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = 92 { 93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 94 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 95 }; 96 97 static const struct amdgpu_video_codecs vega_video_codecs_encode = 98 { 99 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), 100 .codec_array = vega_video_codecs_encode_array, 101 }; 102 103 /* Vega */ 104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = 105 { 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 112 }; 113 114 static const struct amdgpu_video_codecs vega_video_codecs_decode = 115 { 116 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), 117 .codec_array = vega_video_codecs_decode_array, 118 }; 119 120 /* Raven */ 121 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = 122 { 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)}, 130 }; 131 132 static const struct amdgpu_video_codecs rv_video_codecs_decode = 133 { 134 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), 135 .codec_array = rv_video_codecs_decode_array, 136 }; 137 138 /* Renoir, Arcturus */ 139 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = 140 { 141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 148 }; 149 150 static const struct amdgpu_video_codecs rn_video_codecs_decode = 151 { 152 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), 153 .codec_array = rn_video_codecs_decode_array, 154 }; 155 156 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, 157 const struct amdgpu_video_codecs **codecs) 158 { 159 if (adev->ip_versions[VCE_HWIP][0]) { 160 switch (adev->ip_versions[VCE_HWIP][0]) { 161 case IP_VERSION(4, 0, 0): 162 case IP_VERSION(4, 1, 0): 163 if (encode) 164 *codecs = &vega_video_codecs_encode; 165 else 166 *codecs = &vega_video_codecs_decode; 167 return 0; 168 default: 169 return -EINVAL; 170 } 171 } else { 172 switch (adev->ip_versions[UVD_HWIP][0]) { 173 case IP_VERSION(1, 0, 0): 174 case IP_VERSION(1, 0, 1): 175 if (encode) 176 *codecs = &vega_video_codecs_encode; 177 else 178 *codecs = &rv_video_codecs_decode; 179 return 0; 180 case IP_VERSION(2, 5, 0): 181 case IP_VERSION(2, 6, 0): 182 case IP_VERSION(2, 2, 0): 183 if (encode) 184 *codecs = &vega_video_codecs_encode; 185 else 186 *codecs = &rn_video_codecs_decode; 187 return 0; 188 default: 189 return -EINVAL; 190 } 191 } 192 } 193 194 /* 195 * Indirect registers accessor 196 */ 197 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 198 { 199 unsigned long address, data; 200 address = adev->nbio.funcs->get_pcie_index_offset(adev); 201 data = adev->nbio.funcs->get_pcie_data_offset(adev); 202 203 return amdgpu_device_indirect_rreg(adev, address, data, reg); 204 } 205 206 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 207 { 208 unsigned long address, data; 209 210 address = adev->nbio.funcs->get_pcie_index_offset(adev); 211 data = adev->nbio.funcs->get_pcie_data_offset(adev); 212 213 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 214 } 215 216 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 217 { 218 unsigned long address, data; 219 address = adev->nbio.funcs->get_pcie_index_offset(adev); 220 data = adev->nbio.funcs->get_pcie_data_offset(adev); 221 222 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 223 } 224 225 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 226 { 227 unsigned long address, data; 228 229 address = adev->nbio.funcs->get_pcie_index_offset(adev); 230 data = adev->nbio.funcs->get_pcie_data_offset(adev); 231 232 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 233 } 234 235 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 236 { 237 unsigned long flags, address, data; 238 u32 r; 239 240 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 241 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 242 243 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 244 WREG32(address, ((reg) & 0x1ff)); 245 r = RREG32(data); 246 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 247 return r; 248 } 249 250 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 251 { 252 unsigned long flags, address, data; 253 254 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 255 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 256 257 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 258 WREG32(address, ((reg) & 0x1ff)); 259 WREG32(data, (v)); 260 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 261 } 262 263 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 264 { 265 unsigned long flags, address, data; 266 u32 r; 267 268 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 269 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 270 271 spin_lock_irqsave(&adev->didt_idx_lock, flags); 272 WREG32(address, (reg)); 273 r = RREG32(data); 274 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 275 return r; 276 } 277 278 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 279 { 280 unsigned long flags, address, data; 281 282 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 283 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 284 285 spin_lock_irqsave(&adev->didt_idx_lock, flags); 286 WREG32(address, (reg)); 287 WREG32(data, (v)); 288 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 289 } 290 291 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 292 { 293 unsigned long flags; 294 u32 r; 295 296 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 297 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 298 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 299 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 300 return r; 301 } 302 303 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 304 { 305 unsigned long flags; 306 307 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 308 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 309 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 310 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 311 } 312 313 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 314 { 315 unsigned long flags; 316 u32 r; 317 318 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 319 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 320 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 321 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 322 return r; 323 } 324 325 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 326 { 327 unsigned long flags; 328 329 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 330 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 331 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 332 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 333 } 334 335 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 336 { 337 return adev->nbio.funcs->get_memsize(adev); 338 } 339 340 static u32 soc15_get_xclk(struct amdgpu_device *adev) 341 { 342 u32 reference_clock = adev->clock.spll.reference_freq; 343 344 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) || 345 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1)) 346 return 10000; 347 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) || 348 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1)) 349 return reference_clock / 4; 350 351 return reference_clock; 352 } 353 354 355 void soc15_grbm_select(struct amdgpu_device *adev, 356 u32 me, u32 pipe, u32 queue, u32 vmid) 357 { 358 u32 grbm_gfx_cntl = 0; 359 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 360 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 361 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 362 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 363 364 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 365 } 366 367 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 368 { 369 /* todo */ 370 } 371 372 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 373 { 374 /* todo */ 375 return false; 376 } 377 378 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 379 u8 *bios, u32 length_bytes) 380 { 381 u32 *dw_ptr; 382 u32 i, length_dw; 383 uint32_t rom_index_offset; 384 uint32_t rom_data_offset; 385 386 if (bios == NULL) 387 return false; 388 if (length_bytes == 0) 389 return false; 390 /* APU vbios image is part of sbios image */ 391 if (adev->flags & AMD_IS_APU) 392 return false; 393 394 dw_ptr = (u32 *)bios; 395 length_dw = ALIGN(length_bytes, 4) / 4; 396 397 rom_index_offset = 398 adev->smuio.funcs->get_rom_index_offset(adev); 399 rom_data_offset = 400 adev->smuio.funcs->get_rom_data_offset(adev); 401 402 /* set rom index to 0 */ 403 WREG32(rom_index_offset, 0); 404 /* read out the rom data */ 405 for (i = 0; i < length_dw; i++) 406 dw_ptr[i] = RREG32(rom_data_offset); 407 408 return true; 409 } 410 411 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 412 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 413 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 414 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 415 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 416 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 417 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 418 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 419 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 420 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 421 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 422 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 423 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 424 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 425 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 426 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 427 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 428 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 429 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 430 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 431 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 432 }; 433 434 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 435 u32 sh_num, u32 reg_offset) 436 { 437 uint32_t val; 438 439 mutex_lock(&adev->grbm_idx_mutex); 440 if (se_num != 0xffffffff || sh_num != 0xffffffff) 441 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 442 443 val = RREG32(reg_offset); 444 445 if (se_num != 0xffffffff || sh_num != 0xffffffff) 446 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 447 mutex_unlock(&adev->grbm_idx_mutex); 448 return val; 449 } 450 451 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 452 bool indexed, u32 se_num, 453 u32 sh_num, u32 reg_offset) 454 { 455 if (indexed) { 456 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 457 } else { 458 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 459 return adev->gfx.config.gb_addr_config; 460 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 461 return adev->gfx.config.db_debug2; 462 return RREG32(reg_offset); 463 } 464 } 465 466 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 467 u32 sh_num, u32 reg_offset, u32 *value) 468 { 469 uint32_t i; 470 struct soc15_allowed_register_entry *en; 471 472 *value = 0; 473 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 474 en = &soc15_allowed_read_registers[i]; 475 if (adev->reg_offset[en->hwip][en->inst] && 476 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 477 + en->reg_offset)) 478 continue; 479 480 *value = soc15_get_register_value(adev, 481 soc15_allowed_read_registers[i].grbm_indexed, 482 se_num, sh_num, reg_offset); 483 return 0; 484 } 485 return -EINVAL; 486 } 487 488 489 /** 490 * soc15_program_register_sequence - program an array of registers. 491 * 492 * @adev: amdgpu_device pointer 493 * @regs: pointer to the register array 494 * @array_size: size of the register array 495 * 496 * Programs an array or registers with and and or masks. 497 * This is a helper for setting golden registers. 498 */ 499 500 void soc15_program_register_sequence(struct amdgpu_device *adev, 501 const struct soc15_reg_golden *regs, 502 const u32 array_size) 503 { 504 const struct soc15_reg_golden *entry; 505 u32 tmp, reg; 506 int i; 507 508 for (i = 0; i < array_size; ++i) { 509 entry = ®s[i]; 510 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 511 512 if (entry->and_mask == 0xffffffff) { 513 tmp = entry->or_mask; 514 } else { 515 tmp = (entry->hwip == GC_HWIP) ? 516 RREG32_SOC15_IP(GC, reg) : RREG32(reg); 517 518 tmp &= ~(entry->and_mask); 519 tmp |= (entry->or_mask & entry->and_mask); 520 } 521 522 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 523 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 524 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 525 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 526 WREG32_RLC(reg, tmp); 527 else 528 (entry->hwip == GC_HWIP) ? 529 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); 530 531 } 532 533 } 534 535 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 536 { 537 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 538 int ret = 0; 539 540 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 541 if (ras && adev->ras_enabled) 542 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 543 544 ret = amdgpu_dpm_baco_reset(adev); 545 if (ret) 546 return ret; 547 548 /* re-enable doorbell interrupt after BACO exit */ 549 if (ras && adev->ras_enabled) 550 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 551 552 return 0; 553 } 554 555 static enum amd_reset_method 556 soc15_asic_reset_method(struct amdgpu_device *adev) 557 { 558 bool baco_reset = false; 559 bool connected_to_cpu = false; 560 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 561 562 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) 563 connected_to_cpu = true; 564 565 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 566 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 567 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 568 amdgpu_reset_method == AMD_RESET_METHOD_PCI) { 569 /* If connected to cpu, driver only support mode2 */ 570 if (connected_to_cpu) 571 return AMD_RESET_METHOD_MODE2; 572 return amdgpu_reset_method; 573 } 574 575 if (amdgpu_reset_method != -1) 576 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 577 amdgpu_reset_method); 578 579 switch (adev->ip_versions[MP1_HWIP][0]) { 580 case IP_VERSION(10, 0, 0): 581 case IP_VERSION(10, 0, 1): 582 case IP_VERSION(12, 0, 0): 583 case IP_VERSION(12, 0, 1): 584 return AMD_RESET_METHOD_MODE2; 585 case IP_VERSION(9, 0, 0): 586 case IP_VERSION(11, 0, 2): 587 if (adev->asic_type == CHIP_VEGA20) { 588 if (adev->psp.sos.fw_version >= 0x80067) 589 baco_reset = amdgpu_dpm_is_baco_supported(adev); 590 /* 591 * 1. PMFW version > 0x284300: all cases use baco 592 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 593 */ 594 if (ras && adev->ras_enabled && 595 adev->pm.fw_version <= 0x283400) 596 baco_reset = false; 597 } else { 598 baco_reset = amdgpu_dpm_is_baco_supported(adev); 599 } 600 break; 601 case IP_VERSION(13, 0, 2): 602 /* 603 * 1.connected to cpu: driver issue mode2 reset 604 * 2.discret gpu: driver issue mode1 reset 605 */ 606 if (connected_to_cpu) 607 return AMD_RESET_METHOD_MODE2; 608 break; 609 default: 610 break; 611 } 612 613 if (baco_reset) 614 return AMD_RESET_METHOD_BACO; 615 else 616 return AMD_RESET_METHOD_MODE1; 617 } 618 619 static int soc15_asic_reset(struct amdgpu_device *adev) 620 { 621 /* original raven doesn't have full asic reset */ 622 if ((adev->apu_flags & AMD_APU_IS_RAVEN) && 623 !(adev->apu_flags & AMD_APU_IS_RAVEN2)) 624 return 0; 625 626 switch (soc15_asic_reset_method(adev)) { 627 case AMD_RESET_METHOD_PCI: 628 dev_info(adev->dev, "PCI reset\n"); 629 return amdgpu_device_pci_reset(adev); 630 case AMD_RESET_METHOD_BACO: 631 dev_info(adev->dev, "BACO reset\n"); 632 return soc15_asic_baco_reset(adev); 633 case AMD_RESET_METHOD_MODE2: 634 dev_info(adev->dev, "MODE2 reset\n"); 635 return amdgpu_dpm_mode2_reset(adev); 636 default: 637 dev_info(adev->dev, "MODE1 reset\n"); 638 return amdgpu_device_mode1_reset(adev); 639 } 640 } 641 642 static bool soc15_supports_baco(struct amdgpu_device *adev) 643 { 644 switch (adev->ip_versions[MP1_HWIP][0]) { 645 case IP_VERSION(9, 0, 0): 646 case IP_VERSION(11, 0, 2): 647 if (adev->asic_type == CHIP_VEGA20) { 648 if (adev->psp.sos.fw_version >= 0x80067) 649 return amdgpu_dpm_is_baco_supported(adev); 650 return false; 651 } else { 652 return amdgpu_dpm_is_baco_supported(adev); 653 } 654 break; 655 default: 656 return false; 657 } 658 } 659 660 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 661 u32 cntl_reg, u32 status_reg) 662 { 663 return 0; 664 }*/ 665 666 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 667 { 668 /*int r; 669 670 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 671 if (r) 672 return r; 673 674 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 675 */ 676 return 0; 677 } 678 679 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 680 { 681 /* todo */ 682 683 return 0; 684 } 685 686 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 687 { 688 if (pci_is_root_bus(adev->pdev->bus)) 689 return; 690 691 if (amdgpu_pcie_gen2 == 0) 692 return; 693 694 if (adev->flags & AMD_IS_APU) 695 return; 696 697 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 698 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 699 return; 700 701 /* todo */ 702 } 703 704 static void soc15_program_aspm(struct amdgpu_device *adev) 705 { 706 if (!amdgpu_aspm) 707 return; 708 709 if (!(adev->flags & AMD_IS_APU) && 710 (adev->nbio.funcs->program_aspm)) 711 adev->nbio.funcs->program_aspm(adev); 712 } 713 714 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 715 bool enable) 716 { 717 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 718 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 719 } 720 721 const struct amdgpu_ip_block_version vega10_common_ip_block = 722 { 723 .type = AMD_IP_BLOCK_TYPE_COMMON, 724 .major = 2, 725 .minor = 0, 726 .rev = 0, 727 .funcs = &soc15_common_ip_funcs, 728 }; 729 730 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 731 { 732 return adev->nbio.funcs->get_rev_id(adev); 733 } 734 735 static void soc15_reg_base_init(struct amdgpu_device *adev) 736 { 737 int r; 738 739 /* Set IP register base before any HW register access */ 740 switch (adev->asic_type) { 741 case CHIP_VEGA10: 742 case CHIP_VEGA12: 743 case CHIP_RAVEN: 744 vega10_reg_base_init(adev); 745 break; 746 case CHIP_RENOIR: 747 /* It's safe to do ip discovery here for Renior, 748 * it doesn't support SRIOV. */ 749 if (amdgpu_discovery) { 750 r = amdgpu_discovery_reg_base_init(adev); 751 if (r == 0) 752 break; 753 DRM_WARN("failed to init reg base from ip discovery table, " 754 "fallback to legacy init method\n"); 755 } 756 vega10_reg_base_init(adev); 757 break; 758 case CHIP_VEGA20: 759 vega20_reg_base_init(adev); 760 break; 761 case CHIP_ARCTURUS: 762 arct_reg_base_init(adev); 763 break; 764 case CHIP_ALDEBARAN: 765 aldebaran_reg_base_init(adev); 766 break; 767 default: 768 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); 769 break; 770 } 771 } 772 773 void soc15_set_virt_ops(struct amdgpu_device *adev) 774 { 775 adev->virt.ops = &xgpu_ai_virt_ops; 776 777 /* init soc15 reg base early enough so we can 778 * request request full access for sriov before 779 * set_ip_blocks. */ 780 soc15_reg_base_init(adev); 781 } 782 783 static bool soc15_need_full_reset(struct amdgpu_device *adev) 784 { 785 /* change this when we implement soft reset */ 786 return true; 787 } 788 789 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 790 uint64_t *count1) 791 { 792 uint32_t perfctr = 0; 793 uint64_t cnt0_of, cnt1_of; 794 int tmp; 795 796 /* This reports 0 on APUs, so return to avoid writing/reading registers 797 * that may or may not be different from their GPU counterparts 798 */ 799 if (adev->flags & AMD_IS_APU) 800 return; 801 802 /* Set the 2 events that we wish to watch, defined above */ 803 /* Reg 40 is # received msgs */ 804 /* Reg 104 is # of posted requests sent */ 805 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 806 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 807 808 /* Write to enable desired perf counters */ 809 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 810 /* Zero out and enable the perf counters 811 * Write 0x5: 812 * Bit 0 = Start all counters(1) 813 * Bit 2 = Global counter reset enable(1) 814 */ 815 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 816 817 msleep(1000); 818 819 /* Load the shadow and disable the perf counters 820 * Write 0x2: 821 * Bit 0 = Stop counters(0) 822 * Bit 1 = Load the shadow counters(1) 823 */ 824 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 825 826 /* Read register values to get any >32bit overflow */ 827 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 828 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 829 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 830 831 /* Get the values and add the overflow */ 832 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 833 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 834 } 835 836 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 837 uint64_t *count1) 838 { 839 uint32_t perfctr = 0; 840 uint64_t cnt0_of, cnt1_of; 841 int tmp; 842 843 /* This reports 0 on APUs, so return to avoid writing/reading registers 844 * that may or may not be different from their GPU counterparts 845 */ 846 if (adev->flags & AMD_IS_APU) 847 return; 848 849 /* Set the 2 events that we wish to watch, defined above */ 850 /* Reg 40 is # received msgs */ 851 /* Reg 108 is # of posted requests sent on VG20 */ 852 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 853 EVENT0_SEL, 40); 854 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 855 EVENT1_SEL, 108); 856 857 /* Write to enable desired perf counters */ 858 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 859 /* Zero out and enable the perf counters 860 * Write 0x5: 861 * Bit 0 = Start all counters(1) 862 * Bit 2 = Global counter reset enable(1) 863 */ 864 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 865 866 msleep(1000); 867 868 /* Load the shadow and disable the perf counters 869 * Write 0x2: 870 * Bit 0 = Stop counters(0) 871 * Bit 1 = Load the shadow counters(1) 872 */ 873 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 874 875 /* Read register values to get any >32bit overflow */ 876 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 877 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 878 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 879 880 /* Get the values and add the overflow */ 881 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 882 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 883 } 884 885 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 886 { 887 u32 sol_reg; 888 889 /* Just return false for soc15 GPUs. Reset does not seem to 890 * be necessary. 891 */ 892 if (!amdgpu_passthrough(adev)) 893 return false; 894 895 if (adev->flags & AMD_IS_APU) 896 return false; 897 898 /* Check sOS sign of life register to confirm sys driver and sOS 899 * are already been loaded. 900 */ 901 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 902 if (sol_reg) 903 return true; 904 905 return false; 906 } 907 908 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 909 { 910 uint64_t nak_r, nak_g; 911 912 /* Get the number of NAKs received and generated */ 913 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 914 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 915 916 /* Add the total number of NAKs, i.e the number of replays */ 917 return (nak_r + nak_g); 918 } 919 920 static void soc15_pre_asic_init(struct amdgpu_device *adev) 921 { 922 gmc_v9_0_restore_registers(adev); 923 } 924 925 static const struct amdgpu_asic_funcs soc15_asic_funcs = 926 { 927 .read_disabled_bios = &soc15_read_disabled_bios, 928 .read_bios_from_rom = &soc15_read_bios_from_rom, 929 .read_register = &soc15_read_register, 930 .reset = &soc15_asic_reset, 931 .reset_method = &soc15_asic_reset_method, 932 .set_vga_state = &soc15_vga_set_state, 933 .get_xclk = &soc15_get_xclk, 934 .set_uvd_clocks = &soc15_set_uvd_clocks, 935 .set_vce_clocks = &soc15_set_vce_clocks, 936 .get_config_memsize = &soc15_get_config_memsize, 937 .need_full_reset = &soc15_need_full_reset, 938 .init_doorbell_index = &vega10_doorbell_index_init, 939 .get_pcie_usage = &soc15_get_pcie_usage, 940 .need_reset_on_init = &soc15_need_reset_on_init, 941 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 942 .supports_baco = &soc15_supports_baco, 943 .pre_asic_init = &soc15_pre_asic_init, 944 .query_video_codecs = &soc15_query_video_codecs, 945 }; 946 947 static const struct amdgpu_asic_funcs vega20_asic_funcs = 948 { 949 .read_disabled_bios = &soc15_read_disabled_bios, 950 .read_bios_from_rom = &soc15_read_bios_from_rom, 951 .read_register = &soc15_read_register, 952 .reset = &soc15_asic_reset, 953 .reset_method = &soc15_asic_reset_method, 954 .set_vga_state = &soc15_vga_set_state, 955 .get_xclk = &soc15_get_xclk, 956 .set_uvd_clocks = &soc15_set_uvd_clocks, 957 .set_vce_clocks = &soc15_set_vce_clocks, 958 .get_config_memsize = &soc15_get_config_memsize, 959 .need_full_reset = &soc15_need_full_reset, 960 .init_doorbell_index = &vega20_doorbell_index_init, 961 .get_pcie_usage = &vega20_get_pcie_usage, 962 .need_reset_on_init = &soc15_need_reset_on_init, 963 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 964 .supports_baco = &soc15_supports_baco, 965 .pre_asic_init = &soc15_pre_asic_init, 966 .query_video_codecs = &soc15_query_video_codecs, 967 }; 968 969 static int soc15_common_early_init(void *handle) 970 { 971 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 972 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 973 974 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 975 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 976 adev->smc_rreg = NULL; 977 adev->smc_wreg = NULL; 978 adev->pcie_rreg = &soc15_pcie_rreg; 979 adev->pcie_wreg = &soc15_pcie_wreg; 980 adev->pcie_rreg64 = &soc15_pcie_rreg64; 981 adev->pcie_wreg64 = &soc15_pcie_wreg64; 982 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 983 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 984 adev->didt_rreg = &soc15_didt_rreg; 985 adev->didt_wreg = &soc15_didt_wreg; 986 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 987 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 988 adev->se_cac_rreg = &soc15_se_cac_rreg; 989 adev->se_cac_wreg = &soc15_se_cac_wreg; 990 991 adev->rev_id = soc15_get_rev_id(adev); 992 adev->external_rev_id = 0xFF; 993 /* TODO: split the GC and PG flags based on the relevant IP version for which 994 * they are relevant. 995 */ 996 switch (adev->ip_versions[GC_HWIP][0]) { 997 case IP_VERSION(9, 0, 1): 998 adev->asic_funcs = &soc15_asic_funcs; 999 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1000 AMD_CG_SUPPORT_GFX_MGLS | 1001 AMD_CG_SUPPORT_GFX_RLC_LS | 1002 AMD_CG_SUPPORT_GFX_CP_LS | 1003 AMD_CG_SUPPORT_GFX_3D_CGCG | 1004 AMD_CG_SUPPORT_GFX_3D_CGLS | 1005 AMD_CG_SUPPORT_GFX_CGCG | 1006 AMD_CG_SUPPORT_GFX_CGLS | 1007 AMD_CG_SUPPORT_BIF_MGCG | 1008 AMD_CG_SUPPORT_BIF_LS | 1009 AMD_CG_SUPPORT_HDP_LS | 1010 AMD_CG_SUPPORT_DRM_MGCG | 1011 AMD_CG_SUPPORT_DRM_LS | 1012 AMD_CG_SUPPORT_ROM_MGCG | 1013 AMD_CG_SUPPORT_DF_MGCG | 1014 AMD_CG_SUPPORT_SDMA_MGCG | 1015 AMD_CG_SUPPORT_SDMA_LS | 1016 AMD_CG_SUPPORT_MC_MGCG | 1017 AMD_CG_SUPPORT_MC_LS; 1018 adev->pg_flags = 0; 1019 adev->external_rev_id = 0x1; 1020 break; 1021 case IP_VERSION(9, 2, 1): 1022 adev->asic_funcs = &soc15_asic_funcs; 1023 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1024 AMD_CG_SUPPORT_GFX_MGLS | 1025 AMD_CG_SUPPORT_GFX_CGCG | 1026 AMD_CG_SUPPORT_GFX_CGLS | 1027 AMD_CG_SUPPORT_GFX_3D_CGCG | 1028 AMD_CG_SUPPORT_GFX_3D_CGLS | 1029 AMD_CG_SUPPORT_GFX_CP_LS | 1030 AMD_CG_SUPPORT_MC_LS | 1031 AMD_CG_SUPPORT_MC_MGCG | 1032 AMD_CG_SUPPORT_SDMA_MGCG | 1033 AMD_CG_SUPPORT_SDMA_LS | 1034 AMD_CG_SUPPORT_BIF_MGCG | 1035 AMD_CG_SUPPORT_BIF_LS | 1036 AMD_CG_SUPPORT_HDP_MGCG | 1037 AMD_CG_SUPPORT_HDP_LS | 1038 AMD_CG_SUPPORT_ROM_MGCG | 1039 AMD_CG_SUPPORT_VCE_MGCG | 1040 AMD_CG_SUPPORT_UVD_MGCG; 1041 adev->pg_flags = 0; 1042 adev->external_rev_id = adev->rev_id + 0x14; 1043 break; 1044 case IP_VERSION(9, 4, 0): 1045 adev->asic_funcs = &vega20_asic_funcs; 1046 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1047 AMD_CG_SUPPORT_GFX_MGLS | 1048 AMD_CG_SUPPORT_GFX_CGCG | 1049 AMD_CG_SUPPORT_GFX_CGLS | 1050 AMD_CG_SUPPORT_GFX_3D_CGCG | 1051 AMD_CG_SUPPORT_GFX_3D_CGLS | 1052 AMD_CG_SUPPORT_GFX_CP_LS | 1053 AMD_CG_SUPPORT_MC_LS | 1054 AMD_CG_SUPPORT_MC_MGCG | 1055 AMD_CG_SUPPORT_SDMA_MGCG | 1056 AMD_CG_SUPPORT_SDMA_LS | 1057 AMD_CG_SUPPORT_BIF_MGCG | 1058 AMD_CG_SUPPORT_BIF_LS | 1059 AMD_CG_SUPPORT_HDP_MGCG | 1060 AMD_CG_SUPPORT_HDP_LS | 1061 AMD_CG_SUPPORT_ROM_MGCG | 1062 AMD_CG_SUPPORT_VCE_MGCG | 1063 AMD_CG_SUPPORT_UVD_MGCG; 1064 adev->pg_flags = 0; 1065 adev->external_rev_id = adev->rev_id + 0x28; 1066 break; 1067 case IP_VERSION(9, 1, 0): 1068 case IP_VERSION(9, 2, 2): 1069 adev->asic_funcs = &soc15_asic_funcs; 1070 1071 if (adev->rev_id >= 0x8) 1072 adev->apu_flags |= AMD_APU_IS_RAVEN2; 1073 1074 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1075 adev->external_rev_id = adev->rev_id + 0x79; 1076 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1077 adev->external_rev_id = adev->rev_id + 0x41; 1078 else if (adev->rev_id == 1) 1079 adev->external_rev_id = adev->rev_id + 0x20; 1080 else 1081 adev->external_rev_id = adev->rev_id + 0x01; 1082 1083 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1084 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1085 AMD_CG_SUPPORT_GFX_MGLS | 1086 AMD_CG_SUPPORT_GFX_CP_LS | 1087 AMD_CG_SUPPORT_GFX_3D_CGCG | 1088 AMD_CG_SUPPORT_GFX_3D_CGLS | 1089 AMD_CG_SUPPORT_GFX_CGCG | 1090 AMD_CG_SUPPORT_GFX_CGLS | 1091 AMD_CG_SUPPORT_BIF_LS | 1092 AMD_CG_SUPPORT_HDP_LS | 1093 AMD_CG_SUPPORT_MC_MGCG | 1094 AMD_CG_SUPPORT_MC_LS | 1095 AMD_CG_SUPPORT_SDMA_MGCG | 1096 AMD_CG_SUPPORT_SDMA_LS | 1097 AMD_CG_SUPPORT_VCN_MGCG; 1098 1099 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1100 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { 1101 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1102 AMD_CG_SUPPORT_GFX_MGLS | 1103 AMD_CG_SUPPORT_GFX_CP_LS | 1104 AMD_CG_SUPPORT_GFX_3D_CGLS | 1105 AMD_CG_SUPPORT_GFX_CGCG | 1106 AMD_CG_SUPPORT_GFX_CGLS | 1107 AMD_CG_SUPPORT_BIF_LS | 1108 AMD_CG_SUPPORT_HDP_LS | 1109 AMD_CG_SUPPORT_MC_MGCG | 1110 AMD_CG_SUPPORT_MC_LS | 1111 AMD_CG_SUPPORT_SDMA_MGCG | 1112 AMD_CG_SUPPORT_SDMA_LS | 1113 AMD_CG_SUPPORT_VCN_MGCG; 1114 1115 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1116 AMD_PG_SUPPORT_MMHUB | 1117 AMD_PG_SUPPORT_VCN; 1118 } else { 1119 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1120 AMD_CG_SUPPORT_GFX_MGLS | 1121 AMD_CG_SUPPORT_GFX_RLC_LS | 1122 AMD_CG_SUPPORT_GFX_CP_LS | 1123 AMD_CG_SUPPORT_GFX_3D_CGLS | 1124 AMD_CG_SUPPORT_GFX_CGCG | 1125 AMD_CG_SUPPORT_GFX_CGLS | 1126 AMD_CG_SUPPORT_BIF_MGCG | 1127 AMD_CG_SUPPORT_BIF_LS | 1128 AMD_CG_SUPPORT_HDP_MGCG | 1129 AMD_CG_SUPPORT_HDP_LS | 1130 AMD_CG_SUPPORT_DRM_MGCG | 1131 AMD_CG_SUPPORT_DRM_LS | 1132 AMD_CG_SUPPORT_MC_MGCG | 1133 AMD_CG_SUPPORT_MC_LS | 1134 AMD_CG_SUPPORT_SDMA_MGCG | 1135 AMD_CG_SUPPORT_SDMA_LS | 1136 AMD_CG_SUPPORT_VCN_MGCG; 1137 1138 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1139 } 1140 break; 1141 case IP_VERSION(9, 4, 1): 1142 adev->asic_funcs = &vega20_asic_funcs; 1143 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1144 AMD_CG_SUPPORT_GFX_MGLS | 1145 AMD_CG_SUPPORT_GFX_CGCG | 1146 AMD_CG_SUPPORT_GFX_CGLS | 1147 AMD_CG_SUPPORT_GFX_CP_LS | 1148 AMD_CG_SUPPORT_HDP_MGCG | 1149 AMD_CG_SUPPORT_HDP_LS | 1150 AMD_CG_SUPPORT_SDMA_MGCG | 1151 AMD_CG_SUPPORT_SDMA_LS | 1152 AMD_CG_SUPPORT_MC_MGCG | 1153 AMD_CG_SUPPORT_MC_LS | 1154 AMD_CG_SUPPORT_IH_CG | 1155 AMD_CG_SUPPORT_VCN_MGCG | 1156 AMD_CG_SUPPORT_JPEG_MGCG; 1157 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; 1158 adev->external_rev_id = adev->rev_id + 0x32; 1159 break; 1160 case IP_VERSION(9, 3, 0): 1161 adev->asic_funcs = &soc15_asic_funcs; 1162 1163 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1164 adev->external_rev_id = adev->rev_id + 0x91; 1165 else 1166 adev->external_rev_id = adev->rev_id + 0xa1; 1167 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1168 AMD_CG_SUPPORT_GFX_MGLS | 1169 AMD_CG_SUPPORT_GFX_3D_CGCG | 1170 AMD_CG_SUPPORT_GFX_3D_CGLS | 1171 AMD_CG_SUPPORT_GFX_CGCG | 1172 AMD_CG_SUPPORT_GFX_CGLS | 1173 AMD_CG_SUPPORT_GFX_CP_LS | 1174 AMD_CG_SUPPORT_MC_MGCG | 1175 AMD_CG_SUPPORT_MC_LS | 1176 AMD_CG_SUPPORT_SDMA_MGCG | 1177 AMD_CG_SUPPORT_SDMA_LS | 1178 AMD_CG_SUPPORT_BIF_LS | 1179 AMD_CG_SUPPORT_HDP_LS | 1180 AMD_CG_SUPPORT_VCN_MGCG | 1181 AMD_CG_SUPPORT_JPEG_MGCG | 1182 AMD_CG_SUPPORT_IH_CG | 1183 AMD_CG_SUPPORT_ATHUB_LS | 1184 AMD_CG_SUPPORT_ATHUB_MGCG | 1185 AMD_CG_SUPPORT_DF_MGCG; 1186 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1187 AMD_PG_SUPPORT_VCN | 1188 AMD_PG_SUPPORT_JPEG | 1189 AMD_PG_SUPPORT_VCN_DPG; 1190 break; 1191 case IP_VERSION(9, 4, 2): 1192 adev->asic_funcs = &vega20_asic_funcs; 1193 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1194 AMD_CG_SUPPORT_GFX_MGLS | 1195 AMD_CG_SUPPORT_GFX_CP_LS | 1196 AMD_CG_SUPPORT_HDP_LS | 1197 AMD_CG_SUPPORT_SDMA_MGCG | 1198 AMD_CG_SUPPORT_SDMA_LS | 1199 AMD_CG_SUPPORT_IH_CG | 1200 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; 1201 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 1202 adev->external_rev_id = adev->rev_id + 0x3c; 1203 break; 1204 default: 1205 /* FIXME: not supported yet */ 1206 return -EINVAL; 1207 } 1208 1209 if (amdgpu_sriov_vf(adev)) { 1210 amdgpu_virt_init_setting(adev); 1211 xgpu_ai_mailbox_set_irq_funcs(adev); 1212 } 1213 1214 return 0; 1215 } 1216 1217 static int soc15_common_late_init(void *handle) 1218 { 1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1220 int r = 0; 1221 1222 if (amdgpu_sriov_vf(adev)) 1223 xgpu_ai_mailbox_get_irq(adev); 1224 1225 if (adev->nbio.ras_funcs && 1226 adev->nbio.ras_funcs->ras_late_init) 1227 r = adev->nbio.ras_funcs->ras_late_init(adev); 1228 1229 return r; 1230 } 1231 1232 static int soc15_common_sw_init(void *handle) 1233 { 1234 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1235 1236 if (amdgpu_sriov_vf(adev)) 1237 xgpu_ai_mailbox_add_irq_id(adev); 1238 1239 adev->df.funcs->sw_init(adev); 1240 1241 return 0; 1242 } 1243 1244 static int soc15_common_sw_fini(void *handle) 1245 { 1246 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1247 1248 if (adev->nbio.ras_funcs && 1249 adev->nbio.ras_funcs->ras_fini) 1250 adev->nbio.ras_funcs->ras_fini(adev); 1251 adev->df.funcs->sw_fini(adev); 1252 return 0; 1253 } 1254 1255 static void soc15_doorbell_range_init(struct amdgpu_device *adev) 1256 { 1257 int i; 1258 struct amdgpu_ring *ring; 1259 1260 /* sdma/ih doorbell range are programed by hypervisor */ 1261 if (!amdgpu_sriov_vf(adev)) { 1262 for (i = 0; i < adev->sdma.num_instances; i++) { 1263 ring = &adev->sdma.instance[i].ring; 1264 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1265 ring->use_doorbell, ring->doorbell_index, 1266 adev->doorbell_index.sdma_doorbell_range); 1267 } 1268 1269 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 1270 adev->irq.ih.doorbell_index); 1271 } 1272 } 1273 1274 static int soc15_common_hw_init(void *handle) 1275 { 1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1277 1278 /* enable pcie gen2/3 link */ 1279 soc15_pcie_gen3_enable(adev); 1280 /* enable aspm */ 1281 soc15_program_aspm(adev); 1282 /* setup nbio registers */ 1283 adev->nbio.funcs->init_registers(adev); 1284 /* remap HDP registers to a hole in mmio space, 1285 * for the purpose of expose those registers 1286 * to process space 1287 */ 1288 if (adev->nbio.funcs->remap_hdp_registers) 1289 adev->nbio.funcs->remap_hdp_registers(adev); 1290 1291 /* enable the doorbell aperture */ 1292 soc15_enable_doorbell_aperture(adev, true); 1293 /* HW doorbell routing policy: doorbell writing not 1294 * in SDMA/IH/MM/ACV range will be routed to CP. So 1295 * we need to init SDMA/IH/MM/ACV doorbell range prior 1296 * to CP ip block init and ring test. 1297 */ 1298 soc15_doorbell_range_init(adev); 1299 1300 return 0; 1301 } 1302 1303 static int soc15_common_hw_fini(void *handle) 1304 { 1305 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1306 1307 /* disable the doorbell aperture */ 1308 soc15_enable_doorbell_aperture(adev, false); 1309 if (amdgpu_sriov_vf(adev)) 1310 xgpu_ai_mailbox_put_irq(adev); 1311 1312 if (adev->nbio.ras_if && 1313 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1314 if (adev->nbio.ras_funcs && 1315 adev->nbio.ras_funcs->init_ras_controller_interrupt) 1316 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1317 if (adev->nbio.ras_funcs && 1318 adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) 1319 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1320 } 1321 1322 return 0; 1323 } 1324 1325 static int soc15_common_suspend(void *handle) 1326 { 1327 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1328 1329 return soc15_common_hw_fini(adev); 1330 } 1331 1332 static int soc15_common_resume(void *handle) 1333 { 1334 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1335 1336 return soc15_common_hw_init(adev); 1337 } 1338 1339 static bool soc15_common_is_idle(void *handle) 1340 { 1341 return true; 1342 } 1343 1344 static int soc15_common_wait_for_idle(void *handle) 1345 { 1346 return 0; 1347 } 1348 1349 static int soc15_common_soft_reset(void *handle) 1350 { 1351 return 0; 1352 } 1353 1354 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1355 { 1356 uint32_t def, data; 1357 1358 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1359 1360 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1361 data &= ~(0x01000000 | 1362 0x02000000 | 1363 0x04000000 | 1364 0x08000000 | 1365 0x10000000 | 1366 0x20000000 | 1367 0x40000000 | 1368 0x80000000); 1369 else 1370 data |= (0x01000000 | 1371 0x02000000 | 1372 0x04000000 | 1373 0x08000000 | 1374 0x10000000 | 1375 0x20000000 | 1376 0x40000000 | 1377 0x80000000); 1378 1379 if (def != data) 1380 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1381 } 1382 1383 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1384 { 1385 uint32_t def, data; 1386 1387 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1388 1389 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1390 data |= 1; 1391 else 1392 data &= ~1; 1393 1394 if (def != data) 1395 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1396 } 1397 1398 static int soc15_common_set_clockgating_state(void *handle, 1399 enum amd_clockgating_state state) 1400 { 1401 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1402 1403 if (amdgpu_sriov_vf(adev)) 1404 return 0; 1405 1406 switch (adev->ip_versions[NBIO_HWIP][0]) { 1407 case IP_VERSION(6, 1, 0): 1408 case IP_VERSION(6, 2, 0): 1409 case IP_VERSION(7, 4, 0): 1410 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1411 state == AMD_CG_STATE_GATE); 1412 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1413 state == AMD_CG_STATE_GATE); 1414 adev->hdp.funcs->update_clock_gating(adev, 1415 state == AMD_CG_STATE_GATE); 1416 soc15_update_drm_clock_gating(adev, 1417 state == AMD_CG_STATE_GATE); 1418 soc15_update_drm_light_sleep(adev, 1419 state == AMD_CG_STATE_GATE); 1420 adev->smuio.funcs->update_rom_clock_gating(adev, 1421 state == AMD_CG_STATE_GATE); 1422 adev->df.funcs->update_medium_grain_clock_gating(adev, 1423 state == AMD_CG_STATE_GATE); 1424 break; 1425 case IP_VERSION(7, 0, 0): 1426 case IP_VERSION(7, 0, 1): 1427 case IP_VERSION(2, 5, 0): 1428 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1429 state == AMD_CG_STATE_GATE); 1430 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1431 state == AMD_CG_STATE_GATE); 1432 adev->hdp.funcs->update_clock_gating(adev, 1433 state == AMD_CG_STATE_GATE); 1434 soc15_update_drm_clock_gating(adev, 1435 state == AMD_CG_STATE_GATE); 1436 soc15_update_drm_light_sleep(adev, 1437 state == AMD_CG_STATE_GATE); 1438 break; 1439 case IP_VERSION(7, 4, 1): 1440 case IP_VERSION(7, 4, 4): 1441 adev->hdp.funcs->update_clock_gating(adev, 1442 state == AMD_CG_STATE_GATE); 1443 break; 1444 default: 1445 break; 1446 } 1447 return 0; 1448 } 1449 1450 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1451 { 1452 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1453 int data; 1454 1455 if (amdgpu_sriov_vf(adev)) 1456 *flags = 0; 1457 1458 adev->nbio.funcs->get_clockgating_state(adev, flags); 1459 1460 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1461 1462 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) { 1463 1464 /* AMD_CG_SUPPORT_DRM_MGCG */ 1465 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1466 if (!(data & 0x01000000)) 1467 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1468 1469 /* AMD_CG_SUPPORT_DRM_LS */ 1470 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1471 if (data & 0x1) 1472 *flags |= AMD_CG_SUPPORT_DRM_LS; 1473 } 1474 1475 /* AMD_CG_SUPPORT_ROM_MGCG */ 1476 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1477 1478 adev->df.funcs->get_clockgating_state(adev, flags); 1479 } 1480 1481 static int soc15_common_set_powergating_state(void *handle, 1482 enum amd_powergating_state state) 1483 { 1484 /* todo */ 1485 return 0; 1486 } 1487 1488 static const struct amd_ip_funcs soc15_common_ip_funcs = { 1489 .name = "soc15_common", 1490 .early_init = soc15_common_early_init, 1491 .late_init = soc15_common_late_init, 1492 .sw_init = soc15_common_sw_init, 1493 .sw_fini = soc15_common_sw_fini, 1494 .hw_init = soc15_common_hw_init, 1495 .hw_fini = soc15_common_hw_fini, 1496 .suspend = soc15_common_suspend, 1497 .resume = soc15_common_resume, 1498 .is_idle = soc15_common_is_idle, 1499 .wait_for_idle = soc15_common_wait_for_idle, 1500 .soft_reset = soc15_common_soft_reset, 1501 .set_clockgating_state = soc15_common_set_clockgating_state, 1502 .set_powergating_state = soc15_common_set_powergating_state, 1503 .get_clockgating_state= soc15_common_get_clockgating_state, 1504 }; 1505