1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_atombios.h" 29 #include "amdgpu_ih.h" 30 #include "amdgpu_uvd.h" 31 #include "amdgpu_vce.h" 32 #include "amdgpu_ucode.h" 33 #include "amdgpu_psp.h" 34 #include "atom.h" 35 #include "amd_pcie.h" 36 37 #include "vega10/soc15ip.h" 38 #include "vega10/UVD/uvd_7_0_offset.h" 39 #include "vega10/GC/gc_9_0_offset.h" 40 #include "vega10/GC/gc_9_0_sh_mask.h" 41 #include "vega10/SDMA0/sdma0_4_0_offset.h" 42 #include "vega10/SDMA1/sdma1_4_0_offset.h" 43 #include "vega10/HDP/hdp_4_0_offset.h" 44 #include "vega10/HDP/hdp_4_0_sh_mask.h" 45 #include "vega10/MP/mp_9_0_offset.h" 46 #include "vega10/MP/mp_9_0_sh_mask.h" 47 #include "vega10/SMUIO/smuio_9_0_offset.h" 48 #include "vega10/SMUIO/smuio_9_0_sh_mask.h" 49 50 #include "soc15.h" 51 #include "soc15_common.h" 52 #include "gfx_v9_0.h" 53 #include "gmc_v9_0.h" 54 #include "gfxhub_v1_0.h" 55 #include "mmhub_v1_0.h" 56 #include "vega10_ih.h" 57 #include "sdma_v4_0.h" 58 #include "uvd_v7_0.h" 59 #include "vce_v4_0.h" 60 #include "vcn_v1_0.h" 61 #include "amdgpu_powerplay.h" 62 #include "dce_virtual.h" 63 #include "mxgpu_ai.h" 64 65 #define mmFabricConfigAccessControl 0x0410 66 #define mmFabricConfigAccessControl_BASE_IDX 0 67 #define mmFabricConfigAccessControl_DEFAULT 0x00000000 68 //FabricConfigAccessControl 69 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0 70 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1 71 #define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10 72 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L 73 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L 74 #define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L 75 76 77 #define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc 78 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0 79 //DF_PIE_AON0_DfGlobalClkGater 80 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0 81 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL 82 83 enum { 84 DF_MGCG_DISABLE = 0, 85 DF_MGCG_ENABLE_00_CYCLE_DELAY =1, 86 DF_MGCG_ENABLE_01_CYCLE_DELAY =2, 87 DF_MGCG_ENABLE_15_CYCLE_DELAY =13, 88 DF_MGCG_ENABLE_31_CYCLE_DELAY =14, 89 DF_MGCG_ENABLE_63_CYCLE_DELAY =15 90 }; 91 92 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 93 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 94 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 95 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 96 97 /* 98 * Indirect registers accessor 99 */ 100 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 101 { 102 unsigned long flags, address, data; 103 u32 r; 104 const struct nbio_pcie_index_data *nbio_pcie_id; 105 106 if (adev->flags & AMD_IS_APU) 107 nbio_pcie_id = &nbio_v7_0_pcie_index_data; 108 else 109 nbio_pcie_id = &nbio_v6_1_pcie_index_data; 110 111 address = nbio_pcie_id->index_offset; 112 data = nbio_pcie_id->data_offset; 113 114 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 115 WREG32(address, reg); 116 (void)RREG32(address); 117 r = RREG32(data); 118 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 119 return r; 120 } 121 122 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 123 { 124 unsigned long flags, address, data; 125 const struct nbio_pcie_index_data *nbio_pcie_id; 126 127 if (adev->flags & AMD_IS_APU) 128 nbio_pcie_id = &nbio_v7_0_pcie_index_data; 129 else 130 nbio_pcie_id = &nbio_v6_1_pcie_index_data; 131 132 address = nbio_pcie_id->index_offset; 133 data = nbio_pcie_id->data_offset; 134 135 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 136 WREG32(address, reg); 137 (void)RREG32(address); 138 WREG32(data, v); 139 (void)RREG32(data); 140 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 141 } 142 143 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 144 { 145 unsigned long flags, address, data; 146 u32 r; 147 148 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 149 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 150 151 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 152 WREG32(address, ((reg) & 0x1ff)); 153 r = RREG32(data); 154 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 155 return r; 156 } 157 158 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 159 { 160 unsigned long flags, address, data; 161 162 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 163 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 164 165 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 166 WREG32(address, ((reg) & 0x1ff)); 167 WREG32(data, (v)); 168 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 169 } 170 171 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 172 { 173 unsigned long flags, address, data; 174 u32 r; 175 176 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 177 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 178 179 spin_lock_irqsave(&adev->didt_idx_lock, flags); 180 WREG32(address, (reg)); 181 r = RREG32(data); 182 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 183 return r; 184 } 185 186 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 187 { 188 unsigned long flags, address, data; 189 190 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 191 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 192 193 spin_lock_irqsave(&adev->didt_idx_lock, flags); 194 WREG32(address, (reg)); 195 WREG32(data, (v)); 196 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 197 } 198 199 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 200 { 201 unsigned long flags; 202 u32 r; 203 204 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 205 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 206 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 207 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 208 return r; 209 } 210 211 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 212 { 213 unsigned long flags; 214 215 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 216 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 217 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 218 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 219 } 220 221 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 222 { 223 unsigned long flags; 224 u32 r; 225 226 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 227 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 228 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 229 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 230 return r; 231 } 232 233 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 234 { 235 unsigned long flags; 236 237 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 238 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 239 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 240 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 241 } 242 243 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 244 { 245 if (adev->flags & AMD_IS_APU) 246 return nbio_v7_0_get_memsize(adev); 247 else 248 return nbio_v6_1_get_memsize(adev); 249 } 250 251 static const u32 vega10_golden_init[] = 252 { 253 }; 254 255 static const u32 raven_golden_init[] = 256 { 257 }; 258 259 static void soc15_init_golden_registers(struct amdgpu_device *adev) 260 { 261 /* Some of the registers might be dependent on GRBM_GFX_INDEX */ 262 mutex_lock(&adev->grbm_idx_mutex); 263 264 switch (adev->asic_type) { 265 case CHIP_VEGA10: 266 amdgpu_program_register_sequence(adev, 267 vega10_golden_init, 268 (const u32)ARRAY_SIZE(vega10_golden_init)); 269 break; 270 case CHIP_RAVEN: 271 amdgpu_program_register_sequence(adev, 272 raven_golden_init, 273 (const u32)ARRAY_SIZE(raven_golden_init)); 274 break; 275 default: 276 break; 277 } 278 mutex_unlock(&adev->grbm_idx_mutex); 279 } 280 static u32 soc15_get_xclk(struct amdgpu_device *adev) 281 { 282 return adev->clock.spll.reference_freq; 283 } 284 285 286 void soc15_grbm_select(struct amdgpu_device *adev, 287 u32 me, u32 pipe, u32 queue, u32 vmid) 288 { 289 u32 grbm_gfx_cntl = 0; 290 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 291 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 292 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 293 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 294 295 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 296 } 297 298 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 299 { 300 /* todo */ 301 } 302 303 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 304 { 305 /* todo */ 306 return false; 307 } 308 309 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 310 u8 *bios, u32 length_bytes) 311 { 312 u32 *dw_ptr; 313 u32 i, length_dw; 314 315 if (bios == NULL) 316 return false; 317 if (length_bytes == 0) 318 return false; 319 /* APU vbios image is part of sbios image */ 320 if (adev->flags & AMD_IS_APU) 321 return false; 322 323 dw_ptr = (u32 *)bios; 324 length_dw = ALIGN(length_bytes, 4) / 4; 325 326 /* set rom index to 0 */ 327 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 328 /* read out the rom data */ 329 for (i = 0; i < length_dw; i++) 330 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 331 332 return true; 333 } 334 335 static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = { 336 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS)}, 337 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2)}, 338 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0)}, 339 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1)}, 340 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2)}, 341 { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3)}, 342 { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG)}, 343 { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG)}, 344 { SOC15_REG_OFFSET(GC, 0, mmCP_STAT)}, 345 { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1)}, 346 { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2)}, 347 { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3)}, 348 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT)}, 349 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1)}, 350 { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS)}, 351 { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1)}, 352 { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS)}, 353 { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)}, 354 }; 355 356 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 357 u32 sh_num, u32 reg_offset) 358 { 359 uint32_t val; 360 361 mutex_lock(&adev->grbm_idx_mutex); 362 if (se_num != 0xffffffff || sh_num != 0xffffffff) 363 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 364 365 val = RREG32(reg_offset); 366 367 if (se_num != 0xffffffff || sh_num != 0xffffffff) 368 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 369 mutex_unlock(&adev->grbm_idx_mutex); 370 return val; 371 } 372 373 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 374 bool indexed, u32 se_num, 375 u32 sh_num, u32 reg_offset) 376 { 377 if (indexed) { 378 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 379 } else { 380 switch (reg_offset) { 381 case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG): 382 return adev->gfx.config.gb_addr_config; 383 default: 384 return RREG32(reg_offset); 385 } 386 } 387 } 388 389 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 390 u32 sh_num, u32 reg_offset, u32 *value) 391 { 392 uint32_t i; 393 394 *value = 0; 395 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 396 if (reg_offset != soc15_allowed_read_registers[i].reg_offset) 397 continue; 398 399 *value = soc15_get_register_value(adev, 400 soc15_allowed_read_registers[i].grbm_indexed, 401 se_num, sh_num, reg_offset); 402 return 0; 403 } 404 return -EINVAL; 405 } 406 407 static int soc15_asic_reset(struct amdgpu_device *adev) 408 { 409 u32 i; 410 411 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 412 413 dev_info(adev->dev, "GPU reset\n"); 414 415 /* disable BM */ 416 pci_clear_master(adev->pdev); 417 418 pci_save_state(adev->pdev); 419 420 for (i = 0; i < AMDGPU_MAX_IP_NUM; i++) { 421 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP){ 422 adev->ip_blocks[i].version->funcs->soft_reset((void *)adev); 423 break; 424 } 425 } 426 427 pci_restore_state(adev->pdev); 428 429 /* wait for asic to come out of reset */ 430 for (i = 0; i < adev->usec_timeout; i++) { 431 u32 memsize = (adev->flags & AMD_IS_APU) ? 432 nbio_v7_0_get_memsize(adev) : 433 nbio_v6_1_get_memsize(adev); 434 if (memsize != 0xffffffff) 435 break; 436 udelay(1); 437 } 438 439 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 440 441 return 0; 442 } 443 444 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 445 u32 cntl_reg, u32 status_reg) 446 { 447 return 0; 448 }*/ 449 450 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 451 { 452 /*int r; 453 454 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 455 if (r) 456 return r; 457 458 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 459 */ 460 return 0; 461 } 462 463 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 464 { 465 /* todo */ 466 467 return 0; 468 } 469 470 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 471 { 472 if (pci_is_root_bus(adev->pdev->bus)) 473 return; 474 475 if (amdgpu_pcie_gen2 == 0) 476 return; 477 478 if (adev->flags & AMD_IS_APU) 479 return; 480 481 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 482 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 483 return; 484 485 /* todo */ 486 } 487 488 static void soc15_program_aspm(struct amdgpu_device *adev) 489 { 490 491 if (amdgpu_aspm == 0) 492 return; 493 494 /* todo */ 495 } 496 497 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 498 bool enable) 499 { 500 if (adev->flags & AMD_IS_APU) { 501 nbio_v7_0_enable_doorbell_aperture(adev, enable); 502 } else { 503 nbio_v6_1_enable_doorbell_aperture(adev, enable); 504 nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable); 505 } 506 } 507 508 static const struct amdgpu_ip_block_version vega10_common_ip_block = 509 { 510 .type = AMD_IP_BLOCK_TYPE_COMMON, 511 .major = 2, 512 .minor = 0, 513 .rev = 0, 514 .funcs = &soc15_common_ip_funcs, 515 }; 516 517 int soc15_set_ip_blocks(struct amdgpu_device *adev) 518 { 519 nbio_v6_1_detect_hw_virt(adev); 520 521 if (amdgpu_sriov_vf(adev)) 522 adev->virt.ops = &xgpu_ai_virt_ops; 523 524 switch (adev->asic_type) { 525 case CHIP_VEGA10: 526 amdgpu_ip_block_add(adev, &vega10_common_ip_block); 527 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); 528 amdgpu_ip_block_add(adev, &vega10_ih_ip_block); 529 if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1) 530 amdgpu_ip_block_add(adev, &psp_v3_1_ip_block); 531 if (!amdgpu_sriov_vf(adev)) 532 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 533 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 534 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 535 #if defined(CONFIG_DRM_AMD_DC) 536 else if (amdgpu_device_has_dc_support(adev)) 537 amdgpu_ip_block_add(adev, &dm_ip_block); 538 #else 539 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." 540 #endif 541 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); 542 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); 543 amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block); 544 amdgpu_ip_block_add(adev, &vce_v4_0_ip_block); 545 break; 546 case CHIP_RAVEN: 547 amdgpu_ip_block_add(adev, &vega10_common_ip_block); 548 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); 549 amdgpu_ip_block_add(adev, &vega10_ih_ip_block); 550 amdgpu_ip_block_add(adev, &psp_v10_0_ip_block); 551 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); 552 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 553 amdgpu_ip_block_add(adev, &dce_virtual_ip_block); 554 #if defined(CONFIG_DRM_AMD_DC) 555 else if (amdgpu_device_has_dc_support(adev)) 556 amdgpu_ip_block_add(adev, &dm_ip_block); 557 #else 558 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." 559 #endif 560 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); 561 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); 562 amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block); 563 break; 564 default: 565 return -EINVAL; 566 } 567 568 return 0; 569 } 570 571 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 572 { 573 if (adev->flags & AMD_IS_APU) 574 return nbio_v7_0_get_rev_id(adev); 575 else 576 return nbio_v6_1_get_rev_id(adev); 577 } 578 579 static const struct amdgpu_asic_funcs soc15_asic_funcs = 580 { 581 .read_disabled_bios = &soc15_read_disabled_bios, 582 .read_bios_from_rom = &soc15_read_bios_from_rom, 583 .read_register = &soc15_read_register, 584 .reset = &soc15_asic_reset, 585 .set_vga_state = &soc15_vga_set_state, 586 .get_xclk = &soc15_get_xclk, 587 .set_uvd_clocks = &soc15_set_uvd_clocks, 588 .set_vce_clocks = &soc15_set_vce_clocks, 589 .get_config_memsize = &soc15_get_config_memsize, 590 }; 591 592 static int soc15_common_early_init(void *handle) 593 { 594 bool psp_enabled = false; 595 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 596 597 adev->smc_rreg = NULL; 598 adev->smc_wreg = NULL; 599 adev->pcie_rreg = &soc15_pcie_rreg; 600 adev->pcie_wreg = &soc15_pcie_wreg; 601 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 602 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 603 adev->didt_rreg = &soc15_didt_rreg; 604 adev->didt_wreg = &soc15_didt_wreg; 605 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 606 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 607 adev->se_cac_rreg = &soc15_se_cac_rreg; 608 adev->se_cac_wreg = &soc15_se_cac_wreg; 609 610 adev->asic_funcs = &soc15_asic_funcs; 611 612 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && 613 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) 614 psp_enabled = true; 615 616 adev->rev_id = soc15_get_rev_id(adev); 617 adev->external_rev_id = 0xFF; 618 switch (adev->asic_type) { 619 case CHIP_VEGA10: 620 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 621 AMD_CG_SUPPORT_GFX_MGLS | 622 AMD_CG_SUPPORT_GFX_RLC_LS | 623 AMD_CG_SUPPORT_GFX_CP_LS | 624 AMD_CG_SUPPORT_GFX_3D_CGCG | 625 AMD_CG_SUPPORT_GFX_3D_CGLS | 626 AMD_CG_SUPPORT_GFX_CGCG | 627 AMD_CG_SUPPORT_GFX_CGLS | 628 AMD_CG_SUPPORT_BIF_MGCG | 629 AMD_CG_SUPPORT_BIF_LS | 630 AMD_CG_SUPPORT_HDP_LS | 631 AMD_CG_SUPPORT_DRM_MGCG | 632 AMD_CG_SUPPORT_DRM_LS | 633 AMD_CG_SUPPORT_ROM_MGCG | 634 AMD_CG_SUPPORT_DF_MGCG | 635 AMD_CG_SUPPORT_SDMA_MGCG | 636 AMD_CG_SUPPORT_SDMA_LS | 637 AMD_CG_SUPPORT_MC_MGCG | 638 AMD_CG_SUPPORT_MC_LS; 639 adev->pg_flags = 0; 640 adev->external_rev_id = 0x1; 641 break; 642 case CHIP_RAVEN: 643 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 644 AMD_CG_SUPPORT_GFX_MGLS | 645 AMD_CG_SUPPORT_GFX_RLC_LS | 646 AMD_CG_SUPPORT_GFX_CP_LS | 647 AMD_CG_SUPPORT_GFX_3D_CGCG | 648 AMD_CG_SUPPORT_GFX_3D_CGLS | 649 AMD_CG_SUPPORT_GFX_CGCG | 650 AMD_CG_SUPPORT_GFX_CGLS | 651 AMD_CG_SUPPORT_BIF_MGCG | 652 AMD_CG_SUPPORT_BIF_LS | 653 AMD_CG_SUPPORT_HDP_MGCG | 654 AMD_CG_SUPPORT_HDP_LS | 655 AMD_CG_SUPPORT_DRM_MGCG | 656 AMD_CG_SUPPORT_DRM_LS | 657 AMD_CG_SUPPORT_ROM_MGCG | 658 AMD_CG_SUPPORT_MC_MGCG | 659 AMD_CG_SUPPORT_MC_LS | 660 AMD_CG_SUPPORT_SDMA_MGCG | 661 AMD_CG_SUPPORT_SDMA_LS; 662 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 663 AMD_PG_SUPPORT_MMHUB; 664 adev->external_rev_id = 0x1; 665 break; 666 default: 667 /* FIXME: not supported yet */ 668 return -EINVAL; 669 } 670 671 if (amdgpu_sriov_vf(adev)) { 672 amdgpu_virt_init_setting(adev); 673 xgpu_ai_mailbox_set_irq_funcs(adev); 674 } 675 676 adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); 677 678 amdgpu_get_pcie_info(adev); 679 680 return 0; 681 } 682 683 static int soc15_common_late_init(void *handle) 684 { 685 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 686 687 if (amdgpu_sriov_vf(adev)) 688 xgpu_ai_mailbox_get_irq(adev); 689 690 return 0; 691 } 692 693 static int soc15_common_sw_init(void *handle) 694 { 695 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 696 697 if (amdgpu_sriov_vf(adev)) 698 xgpu_ai_mailbox_add_irq_id(adev); 699 700 return 0; 701 } 702 703 static int soc15_common_sw_fini(void *handle) 704 { 705 return 0; 706 } 707 708 static int soc15_common_hw_init(void *handle) 709 { 710 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 711 712 /* move the golden regs per IP block */ 713 soc15_init_golden_registers(adev); 714 /* enable pcie gen2/3 link */ 715 soc15_pcie_gen3_enable(adev); 716 /* enable aspm */ 717 soc15_program_aspm(adev); 718 /* setup nbio registers */ 719 if (!(adev->flags & AMD_IS_APU)) 720 nbio_v6_1_init_registers(adev); 721 /* enable the doorbell aperture */ 722 soc15_enable_doorbell_aperture(adev, true); 723 724 return 0; 725 } 726 727 static int soc15_common_hw_fini(void *handle) 728 { 729 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 730 731 /* disable the doorbell aperture */ 732 soc15_enable_doorbell_aperture(adev, false); 733 if (amdgpu_sriov_vf(adev)) 734 xgpu_ai_mailbox_put_irq(adev); 735 736 return 0; 737 } 738 739 static int soc15_common_suspend(void *handle) 740 { 741 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 742 743 return soc15_common_hw_fini(adev); 744 } 745 746 static int soc15_common_resume(void *handle) 747 { 748 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 749 750 return soc15_common_hw_init(adev); 751 } 752 753 static bool soc15_common_is_idle(void *handle) 754 { 755 return true; 756 } 757 758 static int soc15_common_wait_for_idle(void *handle) 759 { 760 return 0; 761 } 762 763 static int soc15_common_soft_reset(void *handle) 764 { 765 return 0; 766 } 767 768 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) 769 { 770 uint32_t def, data; 771 772 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 773 774 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 775 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 776 else 777 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 778 779 if (def != data) 780 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 781 } 782 783 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 784 { 785 uint32_t def, data; 786 787 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 788 789 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 790 data &= ~(0x01000000 | 791 0x02000000 | 792 0x04000000 | 793 0x08000000 | 794 0x10000000 | 795 0x20000000 | 796 0x40000000 | 797 0x80000000); 798 else 799 data |= (0x01000000 | 800 0x02000000 | 801 0x04000000 | 802 0x08000000 | 803 0x10000000 | 804 0x20000000 | 805 0x40000000 | 806 0x80000000); 807 808 if (def != data) 809 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 810 } 811 812 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 813 { 814 uint32_t def, data; 815 816 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 817 818 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 819 data |= 1; 820 else 821 data &= ~1; 822 823 if (def != data) 824 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 825 } 826 827 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 828 bool enable) 829 { 830 uint32_t def, data; 831 832 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 833 834 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 835 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 836 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 837 else 838 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 839 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 840 841 if (def != data) 842 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); 843 } 844 845 static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev, 846 bool enable) 847 { 848 uint32_t data; 849 850 /* Put DF on broadcast mode */ 851 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl)); 852 data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK; 853 WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data); 854 855 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) { 856 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater)); 857 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; 858 data |= DF_MGCG_ENABLE_15_CYCLE_DELAY; 859 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data); 860 } else { 861 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater)); 862 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; 863 data |= DF_MGCG_DISABLE; 864 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data); 865 } 866 867 WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), 868 mmFabricConfigAccessControl_DEFAULT); 869 } 870 871 static int soc15_common_set_clockgating_state(void *handle, 872 enum amd_clockgating_state state) 873 { 874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 875 876 if (amdgpu_sriov_vf(adev)) 877 return 0; 878 879 switch (adev->asic_type) { 880 case CHIP_VEGA10: 881 nbio_v6_1_update_medium_grain_clock_gating(adev, 882 state == AMD_CG_STATE_GATE ? true : false); 883 nbio_v6_1_update_medium_grain_light_sleep(adev, 884 state == AMD_CG_STATE_GATE ? true : false); 885 soc15_update_hdp_light_sleep(adev, 886 state == AMD_CG_STATE_GATE ? true : false); 887 soc15_update_drm_clock_gating(adev, 888 state == AMD_CG_STATE_GATE ? true : false); 889 soc15_update_drm_light_sleep(adev, 890 state == AMD_CG_STATE_GATE ? true : false); 891 soc15_update_rom_medium_grain_clock_gating(adev, 892 state == AMD_CG_STATE_GATE ? true : false); 893 soc15_update_df_medium_grain_clock_gating(adev, 894 state == AMD_CG_STATE_GATE ? true : false); 895 break; 896 case CHIP_RAVEN: 897 nbio_v7_0_update_medium_grain_clock_gating(adev, 898 state == AMD_CG_STATE_GATE ? true : false); 899 nbio_v6_1_update_medium_grain_light_sleep(adev, 900 state == AMD_CG_STATE_GATE ? true : false); 901 soc15_update_hdp_light_sleep(adev, 902 state == AMD_CG_STATE_GATE ? true : false); 903 soc15_update_drm_clock_gating(adev, 904 state == AMD_CG_STATE_GATE ? true : false); 905 soc15_update_drm_light_sleep(adev, 906 state == AMD_CG_STATE_GATE ? true : false); 907 soc15_update_rom_medium_grain_clock_gating(adev, 908 state == AMD_CG_STATE_GATE ? true : false); 909 break; 910 default: 911 break; 912 } 913 return 0; 914 } 915 916 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 917 { 918 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 919 int data; 920 921 if (amdgpu_sriov_vf(adev)) 922 *flags = 0; 923 924 nbio_v6_1_get_clockgating_state(adev, flags); 925 926 /* AMD_CG_SUPPORT_HDP_LS */ 927 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 928 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 929 *flags |= AMD_CG_SUPPORT_HDP_LS; 930 931 /* AMD_CG_SUPPORT_DRM_MGCG */ 932 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 933 if (!(data & 0x01000000)) 934 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 935 936 /* AMD_CG_SUPPORT_DRM_LS */ 937 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 938 if (data & 0x1) 939 *flags |= AMD_CG_SUPPORT_DRM_LS; 940 941 /* AMD_CG_SUPPORT_ROM_MGCG */ 942 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 943 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 944 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 945 946 /* AMD_CG_SUPPORT_DF_MGCG */ 947 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater)); 948 if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY) 949 *flags |= AMD_CG_SUPPORT_DF_MGCG; 950 } 951 952 static int soc15_common_set_powergating_state(void *handle, 953 enum amd_powergating_state state) 954 { 955 /* todo */ 956 return 0; 957 } 958 959 const struct amd_ip_funcs soc15_common_ip_funcs = { 960 .name = "soc15_common", 961 .early_init = soc15_common_early_init, 962 .late_init = soc15_common_late_init, 963 .sw_init = soc15_common_sw_init, 964 .sw_fini = soc15_common_sw_fini, 965 .hw_init = soc15_common_hw_init, 966 .hw_fini = soc15_common_hw_fini, 967 .suspend = soc15_common_suspend, 968 .resume = soc15_common_resume, 969 .is_idle = soc15_common_is_idle, 970 .wait_for_idle = soc15_common_wait_for_idle, 971 .soft_reset = soc15_common_soft_reset, 972 .set_clockgating_state = soc15_common_set_clockgating_state, 973 .set_powergating_state = soc15_common_set_powergating_state, 974 .get_clockgating_state= soc15_common_get_clockgating_state, 975 }; 976