1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "atom.h" 36 #include "amd_pcie.h" 37 38 #include "uvd/uvd_7_0_offset.h" 39 #include "gc/gc_9_0_offset.h" 40 #include "gc/gc_9_0_sh_mask.h" 41 #include "sdma0/sdma0_4_0_offset.h" 42 #include "sdma1/sdma1_4_0_offset.h" 43 #include "hdp/hdp_4_0_offset.h" 44 #include "hdp/hdp_4_0_sh_mask.h" 45 #include "smuio/smuio_9_0_offset.h" 46 #include "smuio/smuio_9_0_sh_mask.h" 47 #include "nbio/nbio_7_0_default.h" 48 #include "nbio/nbio_7_0_offset.h" 49 #include "nbio/nbio_7_0_sh_mask.h" 50 #include "nbio/nbio_7_0_smn.h" 51 #include "mp/mp_9_0_offset.h" 52 53 #include "soc15.h" 54 #include "soc15_common.h" 55 #include "gfx_v9_0.h" 56 #include "gmc_v9_0.h" 57 #include "gfxhub_v1_0.h" 58 #include "mmhub_v1_0.h" 59 #include "df_v1_7.h" 60 #include "df_v3_6.h" 61 #include "nbio_v6_1.h" 62 #include "nbio_v7_0.h" 63 #include "nbio_v7_4.h" 64 #include "vega10_ih.h" 65 #include "sdma_v4_0.h" 66 #include "uvd_v7_0.h" 67 #include "vce_v4_0.h" 68 #include "vcn_v1_0.h" 69 #include "vcn_v2_0.h" 70 #include "vcn_v2_5.h" 71 #include "dce_virtual.h" 72 #include "mxgpu_ai.h" 73 #include "amdgpu_smu.h" 74 #include "amdgpu_ras.h" 75 #include "amdgpu_xgmi.h" 76 #include <uapi/linux/kfd_ioctl.h> 77 78 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 79 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 80 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 81 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 82 83 /* for Vega20 register name change */ 84 #define mmHDP_MEM_POWER_CTRL 0x00d4 85 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 86 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 87 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 88 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 89 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 90 /* 91 * Indirect registers accessor 92 */ 93 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 94 { 95 unsigned long flags, address, data; 96 u32 r; 97 address = adev->nbio.funcs->get_pcie_index_offset(adev); 98 data = adev->nbio.funcs->get_pcie_data_offset(adev); 99 100 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 101 WREG32(address, reg); 102 (void)RREG32(address); 103 r = RREG32(data); 104 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 105 return r; 106 } 107 108 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 109 { 110 unsigned long flags, address, data; 111 112 address = adev->nbio.funcs->get_pcie_index_offset(adev); 113 data = adev->nbio.funcs->get_pcie_data_offset(adev); 114 115 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 116 WREG32(address, reg); 117 (void)RREG32(address); 118 WREG32(data, v); 119 (void)RREG32(data); 120 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 121 } 122 123 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 124 { 125 unsigned long flags, address, data; 126 u64 r; 127 address = adev->nbio.funcs->get_pcie_index_offset(adev); 128 data = adev->nbio.funcs->get_pcie_data_offset(adev); 129 130 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 131 /* read low 32 bit */ 132 WREG32(address, reg); 133 (void)RREG32(address); 134 r = RREG32(data); 135 136 /* read high 32 bit*/ 137 WREG32(address, reg + 4); 138 (void)RREG32(address); 139 r |= ((u64)RREG32(data) << 32); 140 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 141 return r; 142 } 143 144 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 145 { 146 unsigned long flags, address, data; 147 148 address = adev->nbio.funcs->get_pcie_index_offset(adev); 149 data = adev->nbio.funcs->get_pcie_data_offset(adev); 150 151 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 152 /* write low 32 bit */ 153 WREG32(address, reg); 154 (void)RREG32(address); 155 WREG32(data, (u32)(v & 0xffffffffULL)); 156 (void)RREG32(data); 157 158 /* write high 32 bit */ 159 WREG32(address, reg + 4); 160 (void)RREG32(address); 161 WREG32(data, (u32)(v >> 32)); 162 (void)RREG32(data); 163 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 164 } 165 166 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 167 { 168 unsigned long flags, address, data; 169 u32 r; 170 171 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 172 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 173 174 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 175 WREG32(address, ((reg) & 0x1ff)); 176 r = RREG32(data); 177 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 178 return r; 179 } 180 181 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 182 { 183 unsigned long flags, address, data; 184 185 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 186 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 187 188 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 189 WREG32(address, ((reg) & 0x1ff)); 190 WREG32(data, (v)); 191 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 192 } 193 194 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 195 { 196 unsigned long flags, address, data; 197 u32 r; 198 199 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 200 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 201 202 spin_lock_irqsave(&adev->didt_idx_lock, flags); 203 WREG32(address, (reg)); 204 r = RREG32(data); 205 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 206 return r; 207 } 208 209 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 210 { 211 unsigned long flags, address, data; 212 213 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 214 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 215 216 spin_lock_irqsave(&adev->didt_idx_lock, flags); 217 WREG32(address, (reg)); 218 WREG32(data, (v)); 219 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 220 } 221 222 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 223 { 224 unsigned long flags; 225 u32 r; 226 227 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 228 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 229 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 230 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 231 return r; 232 } 233 234 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 235 { 236 unsigned long flags; 237 238 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 239 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 240 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 241 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 242 } 243 244 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 245 { 246 unsigned long flags; 247 u32 r; 248 249 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 250 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 251 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 252 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 253 return r; 254 } 255 256 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 257 { 258 unsigned long flags; 259 260 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 261 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 262 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 263 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 264 } 265 266 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 267 { 268 return adev->nbio.funcs->get_memsize(adev); 269 } 270 271 static u32 soc15_get_xclk(struct amdgpu_device *adev) 272 { 273 return adev->clock.spll.reference_freq; 274 } 275 276 277 void soc15_grbm_select(struct amdgpu_device *adev, 278 u32 me, u32 pipe, u32 queue, u32 vmid) 279 { 280 u32 grbm_gfx_cntl = 0; 281 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 282 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 283 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 284 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 285 286 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 287 } 288 289 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 290 { 291 /* todo */ 292 } 293 294 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 295 { 296 /* todo */ 297 return false; 298 } 299 300 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 301 u8 *bios, u32 length_bytes) 302 { 303 u32 *dw_ptr; 304 u32 i, length_dw; 305 306 if (bios == NULL) 307 return false; 308 if (length_bytes == 0) 309 return false; 310 /* APU vbios image is part of sbios image */ 311 if (adev->flags & AMD_IS_APU) 312 return false; 313 314 dw_ptr = (u32 *)bios; 315 length_dw = ALIGN(length_bytes, 4) / 4; 316 317 /* set rom index to 0 */ 318 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 319 /* read out the rom data */ 320 for (i = 0; i < length_dw; i++) 321 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 322 323 return true; 324 } 325 326 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 327 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 328 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 329 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 330 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 331 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 332 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 333 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 334 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 335 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 336 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 337 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 338 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 339 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 340 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 341 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 342 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 343 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 344 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 345 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 346 }; 347 348 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 349 u32 sh_num, u32 reg_offset) 350 { 351 uint32_t val; 352 353 mutex_lock(&adev->grbm_idx_mutex); 354 if (se_num != 0xffffffff || sh_num != 0xffffffff) 355 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 356 357 val = RREG32(reg_offset); 358 359 if (se_num != 0xffffffff || sh_num != 0xffffffff) 360 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 361 mutex_unlock(&adev->grbm_idx_mutex); 362 return val; 363 } 364 365 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 366 bool indexed, u32 se_num, 367 u32 sh_num, u32 reg_offset) 368 { 369 if (indexed) { 370 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 371 } else { 372 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 373 return adev->gfx.config.gb_addr_config; 374 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 375 return adev->gfx.config.db_debug2; 376 return RREG32(reg_offset); 377 } 378 } 379 380 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 381 u32 sh_num, u32 reg_offset, u32 *value) 382 { 383 uint32_t i; 384 struct soc15_allowed_register_entry *en; 385 386 *value = 0; 387 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 388 en = &soc15_allowed_read_registers[i]; 389 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 390 + en->reg_offset)) 391 continue; 392 393 *value = soc15_get_register_value(adev, 394 soc15_allowed_read_registers[i].grbm_indexed, 395 se_num, sh_num, reg_offset); 396 return 0; 397 } 398 return -EINVAL; 399 } 400 401 402 /** 403 * soc15_program_register_sequence - program an array of registers. 404 * 405 * @adev: amdgpu_device pointer 406 * @regs: pointer to the register array 407 * @array_size: size of the register array 408 * 409 * Programs an array or registers with and and or masks. 410 * This is a helper for setting golden registers. 411 */ 412 413 void soc15_program_register_sequence(struct amdgpu_device *adev, 414 const struct soc15_reg_golden *regs, 415 const u32 array_size) 416 { 417 const struct soc15_reg_golden *entry; 418 u32 tmp, reg; 419 int i; 420 421 for (i = 0; i < array_size; ++i) { 422 entry = ®s[i]; 423 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 424 425 if (entry->and_mask == 0xffffffff) { 426 tmp = entry->or_mask; 427 } else { 428 tmp = RREG32(reg); 429 tmp &= ~(entry->and_mask); 430 tmp |= (entry->or_mask & entry->and_mask); 431 } 432 433 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 434 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 435 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 436 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 437 WREG32_RLC(reg, tmp); 438 else 439 WREG32(reg, tmp); 440 441 } 442 443 } 444 445 static int soc15_asic_mode1_reset(struct amdgpu_device *adev) 446 { 447 u32 i; 448 int ret = 0; 449 450 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 451 452 dev_info(adev->dev, "GPU mode1 reset\n"); 453 454 /* disable BM */ 455 pci_clear_master(adev->pdev); 456 457 pci_save_state(adev->pdev); 458 459 ret = psp_gpu_reset(adev); 460 if (ret) 461 dev_err(adev->dev, "GPU mode1 reset failed\n"); 462 463 pci_restore_state(adev->pdev); 464 465 /* wait for asic to come out of reset */ 466 for (i = 0; i < adev->usec_timeout; i++) { 467 u32 memsize = adev->nbio.funcs->get_memsize(adev); 468 469 if (memsize != 0xffffffff) 470 break; 471 udelay(1); 472 } 473 474 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 475 476 return ret; 477 } 478 479 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap) 480 { 481 void *pp_handle = adev->powerplay.pp_handle; 482 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 483 484 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) { 485 *cap = false; 486 return -ENOENT; 487 } 488 489 return pp_funcs->get_asic_baco_capability(pp_handle, cap); 490 } 491 492 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 493 { 494 void *pp_handle = adev->powerplay.pp_handle; 495 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 496 497 if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state) 498 return -ENOENT; 499 500 /* enter BACO state */ 501 if (pp_funcs->set_asic_baco_state(pp_handle, 1)) 502 return -EIO; 503 504 /* exit BACO state */ 505 if (pp_funcs->set_asic_baco_state(pp_handle, 0)) 506 return -EIO; 507 508 dev_info(adev->dev, "GPU BACO reset\n"); 509 510 adev->in_baco_reset = 1; 511 512 return 0; 513 } 514 515 static int soc15_mode2_reset(struct amdgpu_device *adev) 516 { 517 if (!adev->powerplay.pp_funcs || 518 !adev->powerplay.pp_funcs->asic_reset_mode_2) 519 return -ENOENT; 520 521 return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle); 522 } 523 524 static enum amd_reset_method 525 soc15_asic_reset_method(struct amdgpu_device *adev) 526 { 527 bool baco_reset; 528 529 switch (adev->asic_type) { 530 case CHIP_RAVEN: 531 return AMD_RESET_METHOD_MODE2; 532 case CHIP_VEGA10: 533 case CHIP_VEGA12: 534 soc15_asic_get_baco_capability(adev, &baco_reset); 535 break; 536 case CHIP_VEGA20: 537 if (adev->psp.sos_fw_version >= 0x80067) 538 soc15_asic_get_baco_capability(adev, &baco_reset); 539 else 540 baco_reset = false; 541 if (baco_reset) { 542 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0); 543 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 544 545 if (hive || (ras && ras->supported)) 546 baco_reset = false; 547 } 548 break; 549 default: 550 baco_reset = false; 551 break; 552 } 553 554 if (baco_reset) 555 return AMD_RESET_METHOD_BACO; 556 else 557 return AMD_RESET_METHOD_MODE1; 558 } 559 560 static int soc15_asic_reset(struct amdgpu_device *adev) 561 { 562 switch (soc15_asic_reset_method(adev)) { 563 case AMD_RESET_METHOD_BACO: 564 amdgpu_inc_vram_lost(adev); 565 return soc15_asic_baco_reset(adev); 566 case AMD_RESET_METHOD_MODE2: 567 return soc15_mode2_reset(adev); 568 default: 569 amdgpu_inc_vram_lost(adev); 570 return soc15_asic_mode1_reset(adev); 571 } 572 } 573 574 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 575 u32 cntl_reg, u32 status_reg) 576 { 577 return 0; 578 }*/ 579 580 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 581 { 582 /*int r; 583 584 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 585 if (r) 586 return r; 587 588 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 589 */ 590 return 0; 591 } 592 593 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 594 { 595 /* todo */ 596 597 return 0; 598 } 599 600 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 601 { 602 if (pci_is_root_bus(adev->pdev->bus)) 603 return; 604 605 if (amdgpu_pcie_gen2 == 0) 606 return; 607 608 if (adev->flags & AMD_IS_APU) 609 return; 610 611 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 612 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 613 return; 614 615 /* todo */ 616 } 617 618 static void soc15_program_aspm(struct amdgpu_device *adev) 619 { 620 621 if (amdgpu_aspm == 0) 622 return; 623 624 /* todo */ 625 } 626 627 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 628 bool enable) 629 { 630 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 631 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 632 } 633 634 static const struct amdgpu_ip_block_version vega10_common_ip_block = 635 { 636 .type = AMD_IP_BLOCK_TYPE_COMMON, 637 .major = 2, 638 .minor = 0, 639 .rev = 0, 640 .funcs = &soc15_common_ip_funcs, 641 }; 642 643 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 644 { 645 return adev->nbio.funcs->get_rev_id(adev); 646 } 647 648 int soc15_set_ip_blocks(struct amdgpu_device *adev) 649 { 650 /* Set IP register base before any HW register access */ 651 switch (adev->asic_type) { 652 case CHIP_VEGA10: 653 case CHIP_VEGA12: 654 case CHIP_RAVEN: 655 case CHIP_RENOIR: 656 vega10_reg_base_init(adev); 657 break; 658 case CHIP_VEGA20: 659 vega20_reg_base_init(adev); 660 break; 661 case CHIP_ARCTURUS: 662 arct_reg_base_init(adev); 663 break; 664 default: 665 return -EINVAL; 666 } 667 668 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 669 adev->gmc.xgmi.supported = true; 670 671 if (adev->flags & AMD_IS_APU) { 672 adev->nbio.funcs = &nbio_v7_0_funcs; 673 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 674 } else if (adev->asic_type == CHIP_VEGA20 || 675 adev->asic_type == CHIP_ARCTURUS) { 676 adev->nbio.funcs = &nbio_v7_4_funcs; 677 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 678 } else { 679 adev->nbio.funcs = &nbio_v6_1_funcs; 680 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 681 } 682 683 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 684 adev->df_funcs = &df_v3_6_funcs; 685 else 686 adev->df_funcs = &df_v1_7_funcs; 687 688 adev->rev_id = soc15_get_rev_id(adev); 689 adev->nbio.funcs->detect_hw_virt(adev); 690 691 if (amdgpu_sriov_vf(adev)) 692 adev->virt.ops = &xgpu_ai_virt_ops; 693 694 switch (adev->asic_type) { 695 case CHIP_VEGA10: 696 case CHIP_VEGA12: 697 case CHIP_VEGA20: 698 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 699 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 700 701 /* For Vega10 SR-IOV, PSP need to be initialized before IH */ 702 if (amdgpu_sriov_vf(adev)) { 703 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 704 if (adev->asic_type == CHIP_VEGA20) 705 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 706 else 707 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 708 } 709 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 710 } else { 711 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 712 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 713 if (adev->asic_type == CHIP_VEGA20) 714 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 715 else 716 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 717 } 718 } 719 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 720 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 721 if (!amdgpu_sriov_vf(adev)) { 722 if (is_support_sw_smu(adev)) 723 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 724 else 725 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 726 } 727 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 728 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 729 #if defined(CONFIG_DRM_AMD_DC) 730 else if (amdgpu_device_has_dc_support(adev)) 731 amdgpu_device_ip_block_add(adev, &dm_ip_block); 732 #endif 733 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { 734 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 735 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 736 } 737 break; 738 case CHIP_RAVEN: 739 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 740 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 741 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 742 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 743 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 744 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 745 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 746 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 747 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 748 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 749 #if defined(CONFIG_DRM_AMD_DC) 750 else if (amdgpu_device_has_dc_support(adev)) 751 amdgpu_device_ip_block_add(adev, &dm_ip_block); 752 #endif 753 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 754 break; 755 case CHIP_ARCTURUS: 756 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 757 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 758 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 759 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 760 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 761 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 762 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 763 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 764 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 765 break; 766 case CHIP_RENOIR: 767 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 768 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 769 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 770 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 771 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 772 if (is_support_sw_smu(adev)) 773 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 774 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 775 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 776 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 777 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 778 #if defined(CONFIG_DRM_AMD_DC) 779 else if (amdgpu_device_has_dc_support(adev)) 780 amdgpu_device_ip_block_add(adev, &dm_ip_block); 781 #else 782 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." 783 #endif 784 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 785 break; 786 default: 787 return -EINVAL; 788 } 789 790 return 0; 791 } 792 793 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 794 { 795 adev->nbio.funcs->hdp_flush(adev, ring); 796 } 797 798 static void soc15_invalidate_hdp(struct amdgpu_device *adev, 799 struct amdgpu_ring *ring) 800 { 801 if (!ring || !ring->funcs->emit_wreg) 802 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 803 else 804 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 805 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 806 } 807 808 static bool soc15_need_full_reset(struct amdgpu_device *adev) 809 { 810 /* change this when we implement soft reset */ 811 return true; 812 } 813 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 814 uint64_t *count1) 815 { 816 uint32_t perfctr = 0; 817 uint64_t cnt0_of, cnt1_of; 818 int tmp; 819 820 /* This reports 0 on APUs, so return to avoid writing/reading registers 821 * that may or may not be different from their GPU counterparts 822 */ 823 if (adev->flags & AMD_IS_APU) 824 return; 825 826 /* Set the 2 events that we wish to watch, defined above */ 827 /* Reg 40 is # received msgs */ 828 /* Reg 104 is # of posted requests sent */ 829 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 830 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 831 832 /* Write to enable desired perf counters */ 833 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 834 /* Zero out and enable the perf counters 835 * Write 0x5: 836 * Bit 0 = Start all counters(1) 837 * Bit 2 = Global counter reset enable(1) 838 */ 839 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 840 841 msleep(1000); 842 843 /* Load the shadow and disable the perf counters 844 * Write 0x2: 845 * Bit 0 = Stop counters(0) 846 * Bit 1 = Load the shadow counters(1) 847 */ 848 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 849 850 /* Read register values to get any >32bit overflow */ 851 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 852 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 853 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 854 855 /* Get the values and add the overflow */ 856 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 857 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 858 } 859 860 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 861 uint64_t *count1) 862 { 863 uint32_t perfctr = 0; 864 uint64_t cnt0_of, cnt1_of; 865 int tmp; 866 867 /* This reports 0 on APUs, so return to avoid writing/reading registers 868 * that may or may not be different from their GPU counterparts 869 */ 870 if (adev->flags & AMD_IS_APU) 871 return; 872 873 /* Set the 2 events that we wish to watch, defined above */ 874 /* Reg 40 is # received msgs */ 875 /* Reg 108 is # of posted requests sent on VG20 */ 876 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 877 EVENT0_SEL, 40); 878 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 879 EVENT1_SEL, 108); 880 881 /* Write to enable desired perf counters */ 882 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 883 /* Zero out and enable the perf counters 884 * Write 0x5: 885 * Bit 0 = Start all counters(1) 886 * Bit 2 = Global counter reset enable(1) 887 */ 888 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 889 890 msleep(1000); 891 892 /* Load the shadow and disable the perf counters 893 * Write 0x2: 894 * Bit 0 = Stop counters(0) 895 * Bit 1 = Load the shadow counters(1) 896 */ 897 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 898 899 /* Read register values to get any >32bit overflow */ 900 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 901 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 902 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 903 904 /* Get the values and add the overflow */ 905 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 906 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 907 } 908 909 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 910 { 911 u32 sol_reg; 912 913 /* Just return false for soc15 GPUs. Reset does not seem to 914 * be necessary. 915 */ 916 if (!amdgpu_passthrough(adev)) 917 return false; 918 919 if (adev->flags & AMD_IS_APU) 920 return false; 921 922 /* Check sOS sign of life register to confirm sys driver and sOS 923 * are already been loaded. 924 */ 925 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 926 if (sol_reg) 927 return true; 928 929 return false; 930 } 931 932 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 933 { 934 uint64_t nak_r, nak_g; 935 936 /* Get the number of NAKs received and generated */ 937 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 938 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 939 940 /* Add the total number of NAKs, i.e the number of replays */ 941 return (nak_r + nak_g); 942 } 943 944 static const struct amdgpu_asic_funcs soc15_asic_funcs = 945 { 946 .read_disabled_bios = &soc15_read_disabled_bios, 947 .read_bios_from_rom = &soc15_read_bios_from_rom, 948 .read_register = &soc15_read_register, 949 .reset = &soc15_asic_reset, 950 .reset_method = &soc15_asic_reset_method, 951 .set_vga_state = &soc15_vga_set_state, 952 .get_xclk = &soc15_get_xclk, 953 .set_uvd_clocks = &soc15_set_uvd_clocks, 954 .set_vce_clocks = &soc15_set_vce_clocks, 955 .get_config_memsize = &soc15_get_config_memsize, 956 .flush_hdp = &soc15_flush_hdp, 957 .invalidate_hdp = &soc15_invalidate_hdp, 958 .need_full_reset = &soc15_need_full_reset, 959 .init_doorbell_index = &vega10_doorbell_index_init, 960 .get_pcie_usage = &soc15_get_pcie_usage, 961 .need_reset_on_init = &soc15_need_reset_on_init, 962 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 963 }; 964 965 static const struct amdgpu_asic_funcs vega20_asic_funcs = 966 { 967 .read_disabled_bios = &soc15_read_disabled_bios, 968 .read_bios_from_rom = &soc15_read_bios_from_rom, 969 .read_register = &soc15_read_register, 970 .reset = &soc15_asic_reset, 971 .set_vga_state = &soc15_vga_set_state, 972 .get_xclk = &soc15_get_xclk, 973 .set_uvd_clocks = &soc15_set_uvd_clocks, 974 .set_vce_clocks = &soc15_set_vce_clocks, 975 .get_config_memsize = &soc15_get_config_memsize, 976 .flush_hdp = &soc15_flush_hdp, 977 .invalidate_hdp = &soc15_invalidate_hdp, 978 .need_full_reset = &soc15_need_full_reset, 979 .init_doorbell_index = &vega20_doorbell_index_init, 980 .get_pcie_usage = &vega20_get_pcie_usage, 981 .need_reset_on_init = &soc15_need_reset_on_init, 982 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 983 .reset_method = &soc15_asic_reset_method 984 }; 985 986 static int soc15_common_early_init(void *handle) 987 { 988 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 989 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 990 991 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 992 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 993 adev->smc_rreg = NULL; 994 adev->smc_wreg = NULL; 995 adev->pcie_rreg = &soc15_pcie_rreg; 996 adev->pcie_wreg = &soc15_pcie_wreg; 997 adev->pcie_rreg64 = &soc15_pcie_rreg64; 998 adev->pcie_wreg64 = &soc15_pcie_wreg64; 999 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 1000 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 1001 adev->didt_rreg = &soc15_didt_rreg; 1002 adev->didt_wreg = &soc15_didt_wreg; 1003 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 1004 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 1005 adev->se_cac_rreg = &soc15_se_cac_rreg; 1006 adev->se_cac_wreg = &soc15_se_cac_wreg; 1007 1008 1009 adev->external_rev_id = 0xFF; 1010 switch (adev->asic_type) { 1011 case CHIP_VEGA10: 1012 adev->asic_funcs = &soc15_asic_funcs; 1013 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1014 AMD_CG_SUPPORT_GFX_MGLS | 1015 AMD_CG_SUPPORT_GFX_RLC_LS | 1016 AMD_CG_SUPPORT_GFX_CP_LS | 1017 AMD_CG_SUPPORT_GFX_3D_CGCG | 1018 AMD_CG_SUPPORT_GFX_3D_CGLS | 1019 AMD_CG_SUPPORT_GFX_CGCG | 1020 AMD_CG_SUPPORT_GFX_CGLS | 1021 AMD_CG_SUPPORT_BIF_MGCG | 1022 AMD_CG_SUPPORT_BIF_LS | 1023 AMD_CG_SUPPORT_HDP_LS | 1024 AMD_CG_SUPPORT_DRM_MGCG | 1025 AMD_CG_SUPPORT_DRM_LS | 1026 AMD_CG_SUPPORT_ROM_MGCG | 1027 AMD_CG_SUPPORT_DF_MGCG | 1028 AMD_CG_SUPPORT_SDMA_MGCG | 1029 AMD_CG_SUPPORT_SDMA_LS | 1030 AMD_CG_SUPPORT_MC_MGCG | 1031 AMD_CG_SUPPORT_MC_LS; 1032 adev->pg_flags = 0; 1033 adev->external_rev_id = 0x1; 1034 break; 1035 case CHIP_VEGA12: 1036 adev->asic_funcs = &soc15_asic_funcs; 1037 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1038 AMD_CG_SUPPORT_GFX_MGLS | 1039 AMD_CG_SUPPORT_GFX_CGCG | 1040 AMD_CG_SUPPORT_GFX_CGLS | 1041 AMD_CG_SUPPORT_GFX_3D_CGCG | 1042 AMD_CG_SUPPORT_GFX_3D_CGLS | 1043 AMD_CG_SUPPORT_GFX_CP_LS | 1044 AMD_CG_SUPPORT_MC_LS | 1045 AMD_CG_SUPPORT_MC_MGCG | 1046 AMD_CG_SUPPORT_SDMA_MGCG | 1047 AMD_CG_SUPPORT_SDMA_LS | 1048 AMD_CG_SUPPORT_BIF_MGCG | 1049 AMD_CG_SUPPORT_BIF_LS | 1050 AMD_CG_SUPPORT_HDP_MGCG | 1051 AMD_CG_SUPPORT_HDP_LS | 1052 AMD_CG_SUPPORT_ROM_MGCG | 1053 AMD_CG_SUPPORT_VCE_MGCG | 1054 AMD_CG_SUPPORT_UVD_MGCG; 1055 adev->pg_flags = 0; 1056 adev->external_rev_id = adev->rev_id + 0x14; 1057 break; 1058 case CHIP_VEGA20: 1059 adev->asic_funcs = &vega20_asic_funcs; 1060 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1061 AMD_CG_SUPPORT_GFX_MGLS | 1062 AMD_CG_SUPPORT_GFX_CGCG | 1063 AMD_CG_SUPPORT_GFX_CGLS | 1064 AMD_CG_SUPPORT_GFX_3D_CGCG | 1065 AMD_CG_SUPPORT_GFX_3D_CGLS | 1066 AMD_CG_SUPPORT_GFX_CP_LS | 1067 AMD_CG_SUPPORT_MC_LS | 1068 AMD_CG_SUPPORT_MC_MGCG | 1069 AMD_CG_SUPPORT_SDMA_MGCG | 1070 AMD_CG_SUPPORT_SDMA_LS | 1071 AMD_CG_SUPPORT_BIF_MGCG | 1072 AMD_CG_SUPPORT_BIF_LS | 1073 AMD_CG_SUPPORT_HDP_MGCG | 1074 AMD_CG_SUPPORT_HDP_LS | 1075 AMD_CG_SUPPORT_ROM_MGCG | 1076 AMD_CG_SUPPORT_VCE_MGCG | 1077 AMD_CG_SUPPORT_UVD_MGCG; 1078 adev->pg_flags = 0; 1079 adev->external_rev_id = adev->rev_id + 0x28; 1080 break; 1081 case CHIP_RAVEN: 1082 adev->asic_funcs = &soc15_asic_funcs; 1083 if (adev->rev_id >= 0x8) 1084 adev->external_rev_id = adev->rev_id + 0x79; 1085 else if (adev->pdev->device == 0x15d8) 1086 adev->external_rev_id = adev->rev_id + 0x41; 1087 else if (adev->rev_id == 1) 1088 adev->external_rev_id = adev->rev_id + 0x20; 1089 else 1090 adev->external_rev_id = adev->rev_id + 0x01; 1091 1092 if (adev->rev_id >= 0x8) { 1093 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1094 AMD_CG_SUPPORT_GFX_MGLS | 1095 AMD_CG_SUPPORT_GFX_CP_LS | 1096 AMD_CG_SUPPORT_GFX_3D_CGCG | 1097 AMD_CG_SUPPORT_GFX_3D_CGLS | 1098 AMD_CG_SUPPORT_GFX_CGCG | 1099 AMD_CG_SUPPORT_GFX_CGLS | 1100 AMD_CG_SUPPORT_BIF_LS | 1101 AMD_CG_SUPPORT_HDP_LS | 1102 AMD_CG_SUPPORT_ROM_MGCG | 1103 AMD_CG_SUPPORT_MC_MGCG | 1104 AMD_CG_SUPPORT_MC_LS | 1105 AMD_CG_SUPPORT_SDMA_MGCG | 1106 AMD_CG_SUPPORT_SDMA_LS | 1107 AMD_CG_SUPPORT_VCN_MGCG; 1108 1109 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1110 } else if (adev->pdev->device == 0x15d8) { 1111 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1112 AMD_CG_SUPPORT_GFX_MGLS | 1113 AMD_CG_SUPPORT_GFX_CP_LS | 1114 AMD_CG_SUPPORT_GFX_3D_CGCG | 1115 AMD_CG_SUPPORT_GFX_3D_CGLS | 1116 AMD_CG_SUPPORT_GFX_CGCG | 1117 AMD_CG_SUPPORT_GFX_CGLS | 1118 AMD_CG_SUPPORT_BIF_LS | 1119 AMD_CG_SUPPORT_HDP_LS | 1120 AMD_CG_SUPPORT_ROM_MGCG | 1121 AMD_CG_SUPPORT_MC_MGCG | 1122 AMD_CG_SUPPORT_MC_LS | 1123 AMD_CG_SUPPORT_SDMA_MGCG | 1124 AMD_CG_SUPPORT_SDMA_LS; 1125 1126 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1127 AMD_PG_SUPPORT_MMHUB | 1128 AMD_PG_SUPPORT_VCN | 1129 AMD_PG_SUPPORT_VCN_DPG; 1130 } else { 1131 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1132 AMD_CG_SUPPORT_GFX_MGLS | 1133 AMD_CG_SUPPORT_GFX_RLC_LS | 1134 AMD_CG_SUPPORT_GFX_CP_LS | 1135 AMD_CG_SUPPORT_GFX_3D_CGCG | 1136 AMD_CG_SUPPORT_GFX_3D_CGLS | 1137 AMD_CG_SUPPORT_GFX_CGCG | 1138 AMD_CG_SUPPORT_GFX_CGLS | 1139 AMD_CG_SUPPORT_BIF_MGCG | 1140 AMD_CG_SUPPORT_BIF_LS | 1141 AMD_CG_SUPPORT_HDP_MGCG | 1142 AMD_CG_SUPPORT_HDP_LS | 1143 AMD_CG_SUPPORT_DRM_MGCG | 1144 AMD_CG_SUPPORT_DRM_LS | 1145 AMD_CG_SUPPORT_ROM_MGCG | 1146 AMD_CG_SUPPORT_MC_MGCG | 1147 AMD_CG_SUPPORT_MC_LS | 1148 AMD_CG_SUPPORT_SDMA_MGCG | 1149 AMD_CG_SUPPORT_SDMA_LS | 1150 AMD_CG_SUPPORT_VCN_MGCG; 1151 1152 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1153 } 1154 break; 1155 case CHIP_ARCTURUS: 1156 adev->asic_funcs = &vega20_asic_funcs; 1157 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1158 AMD_CG_SUPPORT_GFX_MGLS | 1159 AMD_CG_SUPPORT_GFX_CGCG | 1160 AMD_CG_SUPPORT_GFX_CGLS | 1161 AMD_CG_SUPPORT_GFX_CP_LS | 1162 AMD_CG_SUPPORT_HDP_MGCG | 1163 AMD_CG_SUPPORT_HDP_LS | 1164 AMD_CG_SUPPORT_SDMA_MGCG | 1165 AMD_CG_SUPPORT_SDMA_LS | 1166 AMD_CG_SUPPORT_MC_MGCG | 1167 AMD_CG_SUPPORT_MC_LS; 1168 adev->pg_flags = 0; 1169 adev->external_rev_id = adev->rev_id + 0x32; 1170 break; 1171 case CHIP_RENOIR: 1172 adev->asic_funcs = &soc15_asic_funcs; 1173 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1174 AMD_CG_SUPPORT_GFX_MGLS | 1175 AMD_CG_SUPPORT_GFX_3D_CGCG | 1176 AMD_CG_SUPPORT_GFX_3D_CGLS | 1177 AMD_CG_SUPPORT_GFX_CGCG | 1178 AMD_CG_SUPPORT_GFX_CGLS | 1179 AMD_CG_SUPPORT_GFX_CP_LS | 1180 AMD_CG_SUPPORT_MC_MGCG | 1181 AMD_CG_SUPPORT_MC_LS | 1182 AMD_CG_SUPPORT_SDMA_MGCG | 1183 AMD_CG_SUPPORT_SDMA_LS | 1184 AMD_CG_SUPPORT_BIF_LS | 1185 AMD_CG_SUPPORT_HDP_LS | 1186 AMD_CG_SUPPORT_ROM_MGCG | 1187 AMD_CG_SUPPORT_VCN_MGCG | 1188 AMD_CG_SUPPORT_IH_CG | 1189 AMD_CG_SUPPORT_ATHUB_LS | 1190 AMD_CG_SUPPORT_ATHUB_MGCG | 1191 AMD_CG_SUPPORT_DF_MGCG; 1192 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1193 AMD_PG_SUPPORT_VCN | 1194 AMD_PG_SUPPORT_VCN_DPG; 1195 adev->external_rev_id = adev->rev_id + 0x91; 1196 1197 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1198 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1199 AMD_PG_SUPPORT_CP | 1200 AMD_PG_SUPPORT_RLC_SMU_HS; 1201 break; 1202 default: 1203 /* FIXME: not supported yet */ 1204 return -EINVAL; 1205 } 1206 1207 if (amdgpu_sriov_vf(adev)) { 1208 amdgpu_virt_init_setting(adev); 1209 xgpu_ai_mailbox_set_irq_funcs(adev); 1210 } 1211 1212 return 0; 1213 } 1214 1215 static int soc15_common_late_init(void *handle) 1216 { 1217 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1218 1219 if (amdgpu_sriov_vf(adev)) 1220 xgpu_ai_mailbox_get_irq(adev); 1221 1222 return 0; 1223 } 1224 1225 static int soc15_common_sw_init(void *handle) 1226 { 1227 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1228 1229 if (amdgpu_sriov_vf(adev)) 1230 xgpu_ai_mailbox_add_irq_id(adev); 1231 1232 adev->df_funcs->sw_init(adev); 1233 1234 return 0; 1235 } 1236 1237 static int soc15_common_sw_fini(void *handle) 1238 { 1239 return 0; 1240 } 1241 1242 static void soc15_doorbell_range_init(struct amdgpu_device *adev) 1243 { 1244 int i; 1245 struct amdgpu_ring *ring; 1246 1247 /* sdma/ih doorbell range are programed by hypervisor */ 1248 if (!amdgpu_sriov_vf(adev)) { 1249 for (i = 0; i < adev->sdma.num_instances; i++) { 1250 ring = &adev->sdma.instance[i].ring; 1251 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1252 ring->use_doorbell, ring->doorbell_index, 1253 adev->doorbell_index.sdma_doorbell_range); 1254 } 1255 1256 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 1257 adev->irq.ih.doorbell_index); 1258 } 1259 } 1260 1261 static int soc15_common_hw_init(void *handle) 1262 { 1263 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1264 1265 /* enable pcie gen2/3 link */ 1266 soc15_pcie_gen3_enable(adev); 1267 /* enable aspm */ 1268 soc15_program_aspm(adev); 1269 /* setup nbio registers */ 1270 adev->nbio.funcs->init_registers(adev); 1271 /* remap HDP registers to a hole in mmio space, 1272 * for the purpose of expose those registers 1273 * to process space 1274 */ 1275 if (adev->nbio.funcs->remap_hdp_registers) 1276 adev->nbio.funcs->remap_hdp_registers(adev); 1277 1278 /* enable the doorbell aperture */ 1279 soc15_enable_doorbell_aperture(adev, true); 1280 /* HW doorbell routing policy: doorbell writing not 1281 * in SDMA/IH/MM/ACV range will be routed to CP. So 1282 * we need to init SDMA/IH/MM/ACV doorbell range prior 1283 * to CP ip block init and ring test. 1284 */ 1285 soc15_doorbell_range_init(adev); 1286 1287 return 0; 1288 } 1289 1290 static int soc15_common_hw_fini(void *handle) 1291 { 1292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1293 1294 /* disable the doorbell aperture */ 1295 soc15_enable_doorbell_aperture(adev, false); 1296 if (amdgpu_sriov_vf(adev)) 1297 xgpu_ai_mailbox_put_irq(adev); 1298 1299 return 0; 1300 } 1301 1302 static int soc15_common_suspend(void *handle) 1303 { 1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1305 1306 return soc15_common_hw_fini(adev); 1307 } 1308 1309 static int soc15_common_resume(void *handle) 1310 { 1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1312 1313 return soc15_common_hw_init(adev); 1314 } 1315 1316 static bool soc15_common_is_idle(void *handle) 1317 { 1318 return true; 1319 } 1320 1321 static int soc15_common_wait_for_idle(void *handle) 1322 { 1323 return 0; 1324 } 1325 1326 static int soc15_common_soft_reset(void *handle) 1327 { 1328 return 0; 1329 } 1330 1331 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) 1332 { 1333 uint32_t def, data; 1334 1335 if (adev->asic_type == CHIP_VEGA20 || 1336 adev->asic_type == CHIP_ARCTURUS) { 1337 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); 1338 1339 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1340 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1341 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1342 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1343 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; 1344 else 1345 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1346 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1347 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1348 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); 1349 1350 if (def != data) 1351 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); 1352 } else { 1353 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1354 1355 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1356 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1357 else 1358 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1359 1360 if (def != data) 1361 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 1362 } 1363 } 1364 1365 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1366 { 1367 uint32_t def, data; 1368 1369 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1370 1371 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1372 data &= ~(0x01000000 | 1373 0x02000000 | 1374 0x04000000 | 1375 0x08000000 | 1376 0x10000000 | 1377 0x20000000 | 1378 0x40000000 | 1379 0x80000000); 1380 else 1381 data |= (0x01000000 | 1382 0x02000000 | 1383 0x04000000 | 1384 0x08000000 | 1385 0x10000000 | 1386 0x20000000 | 1387 0x40000000 | 1388 0x80000000); 1389 1390 if (def != data) 1391 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1392 } 1393 1394 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1395 { 1396 uint32_t def, data; 1397 1398 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1399 1400 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1401 data |= 1; 1402 else 1403 data &= ~1; 1404 1405 if (def != data) 1406 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1407 } 1408 1409 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1410 bool enable) 1411 { 1412 uint32_t def, data; 1413 1414 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1415 1416 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1417 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1418 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1419 else 1420 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1421 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1422 1423 if (def != data) 1424 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); 1425 } 1426 1427 static int soc15_common_set_clockgating_state(void *handle, 1428 enum amd_clockgating_state state) 1429 { 1430 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1431 1432 if (amdgpu_sriov_vf(adev)) 1433 return 0; 1434 1435 switch (adev->asic_type) { 1436 case CHIP_VEGA10: 1437 case CHIP_VEGA12: 1438 case CHIP_VEGA20: 1439 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1440 state == AMD_CG_STATE_GATE ? true : false); 1441 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1442 state == AMD_CG_STATE_GATE ? true : false); 1443 soc15_update_hdp_light_sleep(adev, 1444 state == AMD_CG_STATE_GATE ? true : false); 1445 soc15_update_drm_clock_gating(adev, 1446 state == AMD_CG_STATE_GATE ? true : false); 1447 soc15_update_drm_light_sleep(adev, 1448 state == AMD_CG_STATE_GATE ? true : false); 1449 soc15_update_rom_medium_grain_clock_gating(adev, 1450 state == AMD_CG_STATE_GATE ? true : false); 1451 adev->df_funcs->update_medium_grain_clock_gating(adev, 1452 state == AMD_CG_STATE_GATE ? true : false); 1453 break; 1454 case CHIP_RAVEN: 1455 case CHIP_RENOIR: 1456 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1457 state == AMD_CG_STATE_GATE ? true : false); 1458 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1459 state == AMD_CG_STATE_GATE ? true : false); 1460 soc15_update_hdp_light_sleep(adev, 1461 state == AMD_CG_STATE_GATE ? true : false); 1462 soc15_update_drm_clock_gating(adev, 1463 state == AMD_CG_STATE_GATE ? true : false); 1464 soc15_update_drm_light_sleep(adev, 1465 state == AMD_CG_STATE_GATE ? true : false); 1466 soc15_update_rom_medium_grain_clock_gating(adev, 1467 state == AMD_CG_STATE_GATE ? true : false); 1468 break; 1469 case CHIP_ARCTURUS: 1470 soc15_update_hdp_light_sleep(adev, 1471 state == AMD_CG_STATE_GATE ? true : false); 1472 break; 1473 default: 1474 break; 1475 } 1476 return 0; 1477 } 1478 1479 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1480 { 1481 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1482 int data; 1483 1484 if (amdgpu_sriov_vf(adev)) 1485 *flags = 0; 1486 1487 adev->nbio.funcs->get_clockgating_state(adev, flags); 1488 1489 /* AMD_CG_SUPPORT_HDP_LS */ 1490 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1491 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 1492 *flags |= AMD_CG_SUPPORT_HDP_LS; 1493 1494 /* AMD_CG_SUPPORT_DRM_MGCG */ 1495 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1496 if (!(data & 0x01000000)) 1497 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1498 1499 /* AMD_CG_SUPPORT_DRM_LS */ 1500 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1501 if (data & 0x1) 1502 *flags |= AMD_CG_SUPPORT_DRM_LS; 1503 1504 /* AMD_CG_SUPPORT_ROM_MGCG */ 1505 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1506 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 1507 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 1508 1509 adev->df_funcs->get_clockgating_state(adev, flags); 1510 } 1511 1512 static int soc15_common_set_powergating_state(void *handle, 1513 enum amd_powergating_state state) 1514 { 1515 /* todo */ 1516 return 0; 1517 } 1518 1519 const struct amd_ip_funcs soc15_common_ip_funcs = { 1520 .name = "soc15_common", 1521 .early_init = soc15_common_early_init, 1522 .late_init = soc15_common_late_init, 1523 .sw_init = soc15_common_sw_init, 1524 .sw_fini = soc15_common_sw_fini, 1525 .hw_init = soc15_common_hw_init, 1526 .hw_fini = soc15_common_hw_fini, 1527 .suspend = soc15_common_suspend, 1528 .resume = soc15_common_resume, 1529 .is_idle = soc15_common_is_idle, 1530 .wait_for_idle = soc15_common_wait_for_idle, 1531 .soft_reset = soc15_common_soft_reset, 1532 .set_clockgating_state = soc15_common_set_clockgating_state, 1533 .set_powergating_state = soc15_common_set_powergating_state, 1534 .get_clockgating_state= soc15_common_get_clockgating_state, 1535 }; 1536