1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "uvd/uvd_7_0_offset.h" 41 #include "gc/gc_9_0_offset.h" 42 #include "gc/gc_9_0_sh_mask.h" 43 #include "sdma0/sdma0_4_0_offset.h" 44 #include "sdma1/sdma1_4_0_offset.h" 45 #include "nbio/nbio_7_0_default.h" 46 #include "nbio/nbio_7_0_offset.h" 47 #include "nbio/nbio_7_0_sh_mask.h" 48 #include "nbio/nbio_7_0_smn.h" 49 #include "mp/mp_9_0_offset.h" 50 51 #include "soc15.h" 52 #include "soc15_common.h" 53 #include "gfx_v9_0.h" 54 #include "gmc_v9_0.h" 55 #include "gfxhub_v1_0.h" 56 #include "mmhub_v1_0.h" 57 #include "df_v1_7.h" 58 #include "df_v3_6.h" 59 #include "nbio_v6_1.h" 60 #include "nbio_v7_0.h" 61 #include "nbio_v7_4.h" 62 #include "hdp_v4_0.h" 63 #include "vega10_ih.h" 64 #include "vega20_ih.h" 65 #include "navi10_ih.h" 66 #include "sdma_v4_0.h" 67 #include "uvd_v7_0.h" 68 #include "vce_v4_0.h" 69 #include "vcn_v1_0.h" 70 #include "vcn_v2_0.h" 71 #include "jpeg_v2_0.h" 72 #include "vcn_v2_5.h" 73 #include "jpeg_v2_5.h" 74 #include "smuio_v9_0.h" 75 #include "smuio_v11_0.h" 76 #include "smuio_v13_0.h" 77 #include "amdgpu_vkms.h" 78 #include "mxgpu_ai.h" 79 #include "amdgpu_ras.h" 80 #include "amdgpu_xgmi.h" 81 #include <uapi/linux/kfd_ioctl.h> 82 83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 87 88 static const struct amd_ip_funcs soc15_common_ip_funcs; 89 90 /* Vega, Raven, Arcturus */ 91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = 92 { 93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 94 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 95 }; 96 97 static const struct amdgpu_video_codecs vega_video_codecs_encode = 98 { 99 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), 100 .codec_array = vega_video_codecs_encode_array, 101 }; 102 103 /* Vega */ 104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = 105 { 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 112 }; 113 114 static const struct amdgpu_video_codecs vega_video_codecs_decode = 115 { 116 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), 117 .codec_array = vega_video_codecs_decode_array, 118 }; 119 120 /* Raven */ 121 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = 122 { 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)}, 130 }; 131 132 static const struct amdgpu_video_codecs rv_video_codecs_decode = 133 { 134 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), 135 .codec_array = rv_video_codecs_decode_array, 136 }; 137 138 /* Renoir, Arcturus */ 139 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = 140 { 141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 148 }; 149 150 static const struct amdgpu_video_codecs rn_video_codecs_decode = 151 { 152 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), 153 .codec_array = rn_video_codecs_decode_array, 154 }; 155 156 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, 157 const struct amdgpu_video_codecs **codecs) 158 { 159 switch (adev->asic_type) { 160 case CHIP_VEGA20: 161 case CHIP_VEGA10: 162 case CHIP_VEGA12: 163 if (encode) 164 *codecs = &vega_video_codecs_encode; 165 else 166 *codecs = &vega_video_codecs_decode; 167 return 0; 168 case CHIP_RAVEN: 169 if (encode) 170 *codecs = &vega_video_codecs_encode; 171 else 172 *codecs = &rv_video_codecs_decode; 173 return 0; 174 case CHIP_ARCTURUS: 175 case CHIP_ALDEBARAN: 176 case CHIP_RENOIR: 177 if (encode) 178 *codecs = &vega_video_codecs_encode; 179 else 180 *codecs = &rn_video_codecs_decode; 181 return 0; 182 default: 183 return -EINVAL; 184 } 185 } 186 187 /* 188 * Indirect registers accessor 189 */ 190 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 191 { 192 unsigned long address, data; 193 address = adev->nbio.funcs->get_pcie_index_offset(adev); 194 data = adev->nbio.funcs->get_pcie_data_offset(adev); 195 196 return amdgpu_device_indirect_rreg(adev, address, data, reg); 197 } 198 199 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 200 { 201 unsigned long address, data; 202 203 address = adev->nbio.funcs->get_pcie_index_offset(adev); 204 data = adev->nbio.funcs->get_pcie_data_offset(adev); 205 206 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 207 } 208 209 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 210 { 211 unsigned long address, data; 212 address = adev->nbio.funcs->get_pcie_index_offset(adev); 213 data = adev->nbio.funcs->get_pcie_data_offset(adev); 214 215 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 216 } 217 218 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 219 { 220 unsigned long address, data; 221 222 address = adev->nbio.funcs->get_pcie_index_offset(adev); 223 data = adev->nbio.funcs->get_pcie_data_offset(adev); 224 225 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 226 } 227 228 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 229 { 230 unsigned long flags, address, data; 231 u32 r; 232 233 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 234 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 235 236 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 237 WREG32(address, ((reg) & 0x1ff)); 238 r = RREG32(data); 239 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 240 return r; 241 } 242 243 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 244 { 245 unsigned long flags, address, data; 246 247 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 248 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 249 250 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 251 WREG32(address, ((reg) & 0x1ff)); 252 WREG32(data, (v)); 253 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 254 } 255 256 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 257 { 258 unsigned long flags, address, data; 259 u32 r; 260 261 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 262 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 263 264 spin_lock_irqsave(&adev->didt_idx_lock, flags); 265 WREG32(address, (reg)); 266 r = RREG32(data); 267 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 268 return r; 269 } 270 271 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 272 { 273 unsigned long flags, address, data; 274 275 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 276 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 277 278 spin_lock_irqsave(&adev->didt_idx_lock, flags); 279 WREG32(address, (reg)); 280 WREG32(data, (v)); 281 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 282 } 283 284 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 285 { 286 unsigned long flags; 287 u32 r; 288 289 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 290 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 291 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 292 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 293 return r; 294 } 295 296 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 297 { 298 unsigned long flags; 299 300 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 301 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 302 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 303 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 304 } 305 306 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 307 { 308 unsigned long flags; 309 u32 r; 310 311 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 312 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 313 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 314 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 315 return r; 316 } 317 318 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 319 { 320 unsigned long flags; 321 322 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 323 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 324 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 325 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 326 } 327 328 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 329 { 330 return adev->nbio.funcs->get_memsize(adev); 331 } 332 333 static u32 soc15_get_xclk(struct amdgpu_device *adev) 334 { 335 u32 reference_clock = adev->clock.spll.reference_freq; 336 337 if (adev->asic_type == CHIP_RENOIR) 338 return 10000; 339 if (adev->asic_type == CHIP_RAVEN) 340 return reference_clock / 4; 341 342 return reference_clock; 343 } 344 345 346 void soc15_grbm_select(struct amdgpu_device *adev, 347 u32 me, u32 pipe, u32 queue, u32 vmid) 348 { 349 u32 grbm_gfx_cntl = 0; 350 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 351 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 352 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 353 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 354 355 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 356 } 357 358 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 359 { 360 /* todo */ 361 } 362 363 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 364 { 365 /* todo */ 366 return false; 367 } 368 369 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 370 u8 *bios, u32 length_bytes) 371 { 372 u32 *dw_ptr; 373 u32 i, length_dw; 374 uint32_t rom_index_offset; 375 uint32_t rom_data_offset; 376 377 if (bios == NULL) 378 return false; 379 if (length_bytes == 0) 380 return false; 381 /* APU vbios image is part of sbios image */ 382 if (adev->flags & AMD_IS_APU) 383 return false; 384 385 dw_ptr = (u32 *)bios; 386 length_dw = ALIGN(length_bytes, 4) / 4; 387 388 rom_index_offset = 389 adev->smuio.funcs->get_rom_index_offset(adev); 390 rom_data_offset = 391 adev->smuio.funcs->get_rom_data_offset(adev); 392 393 /* set rom index to 0 */ 394 WREG32(rom_index_offset, 0); 395 /* read out the rom data */ 396 for (i = 0; i < length_dw; i++) 397 dw_ptr[i] = RREG32(rom_data_offset); 398 399 return true; 400 } 401 402 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 403 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 404 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 405 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 406 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 407 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 408 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 409 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 410 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 411 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 412 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 413 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 414 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 415 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 416 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 417 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 418 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 419 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 420 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 421 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 422 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 423 }; 424 425 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 426 u32 sh_num, u32 reg_offset) 427 { 428 uint32_t val; 429 430 mutex_lock(&adev->grbm_idx_mutex); 431 if (se_num != 0xffffffff || sh_num != 0xffffffff) 432 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 433 434 val = RREG32(reg_offset); 435 436 if (se_num != 0xffffffff || sh_num != 0xffffffff) 437 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 438 mutex_unlock(&adev->grbm_idx_mutex); 439 return val; 440 } 441 442 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 443 bool indexed, u32 se_num, 444 u32 sh_num, u32 reg_offset) 445 { 446 if (indexed) { 447 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 448 } else { 449 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 450 return adev->gfx.config.gb_addr_config; 451 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 452 return adev->gfx.config.db_debug2; 453 return RREG32(reg_offset); 454 } 455 } 456 457 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 458 u32 sh_num, u32 reg_offset, u32 *value) 459 { 460 uint32_t i; 461 struct soc15_allowed_register_entry *en; 462 463 *value = 0; 464 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 465 en = &soc15_allowed_read_registers[i]; 466 if (adev->reg_offset[en->hwip][en->inst] && 467 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 468 + en->reg_offset)) 469 continue; 470 471 *value = soc15_get_register_value(adev, 472 soc15_allowed_read_registers[i].grbm_indexed, 473 se_num, sh_num, reg_offset); 474 return 0; 475 } 476 return -EINVAL; 477 } 478 479 480 /** 481 * soc15_program_register_sequence - program an array of registers. 482 * 483 * @adev: amdgpu_device pointer 484 * @regs: pointer to the register array 485 * @array_size: size of the register array 486 * 487 * Programs an array or registers with and and or masks. 488 * This is a helper for setting golden registers. 489 */ 490 491 void soc15_program_register_sequence(struct amdgpu_device *adev, 492 const struct soc15_reg_golden *regs, 493 const u32 array_size) 494 { 495 const struct soc15_reg_golden *entry; 496 u32 tmp, reg; 497 int i; 498 499 for (i = 0; i < array_size; ++i) { 500 entry = ®s[i]; 501 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 502 503 if (entry->and_mask == 0xffffffff) { 504 tmp = entry->or_mask; 505 } else { 506 tmp = (entry->hwip == GC_HWIP) ? 507 RREG32_SOC15_IP(GC, reg) : RREG32(reg); 508 509 tmp &= ~(entry->and_mask); 510 tmp |= (entry->or_mask & entry->and_mask); 511 } 512 513 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 514 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 515 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 516 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 517 WREG32_RLC(reg, tmp); 518 else 519 (entry->hwip == GC_HWIP) ? 520 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); 521 522 } 523 524 } 525 526 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 527 { 528 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 529 int ret = 0; 530 531 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 532 if (ras && adev->ras_enabled) 533 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 534 535 ret = amdgpu_dpm_baco_reset(adev); 536 if (ret) 537 return ret; 538 539 /* re-enable doorbell interrupt after BACO exit */ 540 if (ras && adev->ras_enabled) 541 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 542 543 return 0; 544 } 545 546 static enum amd_reset_method 547 soc15_asic_reset_method(struct amdgpu_device *adev) 548 { 549 bool baco_reset = false; 550 bool connected_to_cpu = false; 551 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 552 553 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) 554 connected_to_cpu = true; 555 556 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 557 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 558 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 559 amdgpu_reset_method == AMD_RESET_METHOD_PCI) { 560 /* If connected to cpu, driver only support mode2 */ 561 if (connected_to_cpu) 562 return AMD_RESET_METHOD_MODE2; 563 return amdgpu_reset_method; 564 } 565 566 if (amdgpu_reset_method != -1) 567 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 568 amdgpu_reset_method); 569 570 switch (adev->asic_type) { 571 case CHIP_RAVEN: 572 case CHIP_RENOIR: 573 return AMD_RESET_METHOD_MODE2; 574 case CHIP_VEGA10: 575 case CHIP_VEGA12: 576 case CHIP_ARCTURUS: 577 baco_reset = amdgpu_dpm_is_baco_supported(adev); 578 break; 579 case CHIP_VEGA20: 580 if (adev->psp.sos.fw_version >= 0x80067) 581 baco_reset = amdgpu_dpm_is_baco_supported(adev); 582 583 /* 584 * 1. PMFW version > 0x284300: all cases use baco 585 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 586 */ 587 if (ras && adev->ras_enabled && 588 adev->pm.fw_version <= 0x283400) 589 baco_reset = false; 590 break; 591 case CHIP_ALDEBARAN: 592 /* 593 * 1.connected to cpu: driver issue mode2 reset 594 * 2.discret gpu: driver issue mode1 reset 595 */ 596 if (connected_to_cpu) 597 return AMD_RESET_METHOD_MODE2; 598 break; 599 default: 600 break; 601 } 602 603 if (baco_reset) 604 return AMD_RESET_METHOD_BACO; 605 else 606 return AMD_RESET_METHOD_MODE1; 607 } 608 609 static int soc15_asic_reset(struct amdgpu_device *adev) 610 { 611 /* original raven doesn't have full asic reset */ 612 if ((adev->apu_flags & AMD_APU_IS_RAVEN) && 613 !(adev->apu_flags & AMD_APU_IS_RAVEN2)) 614 return 0; 615 616 switch (soc15_asic_reset_method(adev)) { 617 case AMD_RESET_METHOD_PCI: 618 dev_info(adev->dev, "PCI reset\n"); 619 return amdgpu_device_pci_reset(adev); 620 case AMD_RESET_METHOD_BACO: 621 dev_info(adev->dev, "BACO reset\n"); 622 return soc15_asic_baco_reset(adev); 623 case AMD_RESET_METHOD_MODE2: 624 dev_info(adev->dev, "MODE2 reset\n"); 625 return amdgpu_dpm_mode2_reset(adev); 626 default: 627 dev_info(adev->dev, "MODE1 reset\n"); 628 return amdgpu_device_mode1_reset(adev); 629 } 630 } 631 632 static bool soc15_supports_baco(struct amdgpu_device *adev) 633 { 634 switch (adev->asic_type) { 635 case CHIP_VEGA10: 636 case CHIP_VEGA12: 637 case CHIP_ARCTURUS: 638 return amdgpu_dpm_is_baco_supported(adev); 639 case CHIP_VEGA20: 640 if (adev->psp.sos.fw_version >= 0x80067) 641 return amdgpu_dpm_is_baco_supported(adev); 642 return false; 643 default: 644 return false; 645 } 646 } 647 648 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 649 u32 cntl_reg, u32 status_reg) 650 { 651 return 0; 652 }*/ 653 654 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 655 { 656 /*int r; 657 658 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 659 if (r) 660 return r; 661 662 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 663 */ 664 return 0; 665 } 666 667 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 668 { 669 /* todo */ 670 671 return 0; 672 } 673 674 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 675 { 676 if (pci_is_root_bus(adev->pdev->bus)) 677 return; 678 679 if (amdgpu_pcie_gen2 == 0) 680 return; 681 682 if (adev->flags & AMD_IS_APU) 683 return; 684 685 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 686 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 687 return; 688 689 /* todo */ 690 } 691 692 static void soc15_program_aspm(struct amdgpu_device *adev) 693 { 694 if (!amdgpu_aspm) 695 return; 696 697 if (!(adev->flags & AMD_IS_APU) && 698 (adev->nbio.funcs->program_aspm)) 699 adev->nbio.funcs->program_aspm(adev); 700 } 701 702 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 703 bool enable) 704 { 705 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 706 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 707 } 708 709 static const struct amdgpu_ip_block_version vega10_common_ip_block = 710 { 711 .type = AMD_IP_BLOCK_TYPE_COMMON, 712 .major = 2, 713 .minor = 0, 714 .rev = 0, 715 .funcs = &soc15_common_ip_funcs, 716 }; 717 718 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 719 { 720 return adev->nbio.funcs->get_rev_id(adev); 721 } 722 723 static void soc15_reg_base_init(struct amdgpu_device *adev) 724 { 725 int r; 726 727 /* Set IP register base before any HW register access */ 728 switch (adev->asic_type) { 729 case CHIP_VEGA10: 730 case CHIP_VEGA12: 731 case CHIP_RAVEN: 732 vega10_reg_base_init(adev); 733 break; 734 case CHIP_RENOIR: 735 /* It's safe to do ip discovery here for Renior, 736 * it doesn't support SRIOV. */ 737 if (amdgpu_discovery) { 738 r = amdgpu_discovery_reg_base_init(adev); 739 if (r == 0) 740 break; 741 DRM_WARN("failed to init reg base from ip discovery table, " 742 "fallback to legacy init method\n"); 743 } 744 vega10_reg_base_init(adev); 745 break; 746 case CHIP_VEGA20: 747 vega20_reg_base_init(adev); 748 break; 749 case CHIP_ARCTURUS: 750 arct_reg_base_init(adev); 751 break; 752 case CHIP_ALDEBARAN: 753 aldebaran_reg_base_init(adev); 754 break; 755 default: 756 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); 757 break; 758 } 759 } 760 761 void soc15_set_virt_ops(struct amdgpu_device *adev) 762 { 763 adev->virt.ops = &xgpu_ai_virt_ops; 764 765 /* init soc15 reg base early enough so we can 766 * request request full access for sriov before 767 * set_ip_blocks. */ 768 soc15_reg_base_init(adev); 769 } 770 771 int soc15_set_ip_blocks(struct amdgpu_device *adev) 772 { 773 /* for bare metal case */ 774 if (!amdgpu_sriov_vf(adev)) 775 soc15_reg_base_init(adev); 776 777 if (adev->flags & AMD_IS_APU) { 778 adev->nbio.funcs = &nbio_v7_0_funcs; 779 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 780 } else if (adev->asic_type == CHIP_VEGA20 || 781 adev->asic_type == CHIP_ARCTURUS || 782 adev->asic_type == CHIP_ALDEBARAN) { 783 adev->nbio.funcs = &nbio_v7_4_funcs; 784 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 785 } else { 786 adev->nbio.funcs = &nbio_v6_1_funcs; 787 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 788 } 789 adev->hdp.funcs = &hdp_v4_0_funcs; 790 791 if (adev->asic_type == CHIP_VEGA20 || 792 adev->asic_type == CHIP_ARCTURUS || 793 adev->asic_type == CHIP_ALDEBARAN) 794 adev->df.funcs = &df_v3_6_funcs; 795 else 796 adev->df.funcs = &df_v1_7_funcs; 797 798 if (adev->asic_type == CHIP_VEGA20 || 799 adev->asic_type == CHIP_ARCTURUS) 800 adev->smuio.funcs = &smuio_v11_0_funcs; 801 else if (adev->asic_type == CHIP_ALDEBARAN) 802 adev->smuio.funcs = &smuio_v13_0_funcs; 803 else 804 adev->smuio.funcs = &smuio_v9_0_funcs; 805 806 adev->rev_id = soc15_get_rev_id(adev); 807 808 switch (adev->asic_type) { 809 case CHIP_VEGA10: 810 case CHIP_VEGA12: 811 case CHIP_VEGA20: 812 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 813 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 814 815 /* For Vega10 SR-IOV, PSP need to be initialized before IH */ 816 if (amdgpu_sriov_vf(adev)) { 817 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 818 if (adev->asic_type == CHIP_VEGA20) 819 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 820 else 821 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 822 } 823 if (adev->asic_type == CHIP_VEGA20) 824 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 825 else 826 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 827 } else { 828 if (adev->asic_type == CHIP_VEGA20) 829 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 830 else 831 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 832 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 833 if (adev->asic_type == CHIP_VEGA20) 834 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 835 else 836 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 837 } 838 } 839 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 840 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 841 if (is_support_sw_smu(adev)) { 842 if (!amdgpu_sriov_vf(adev)) 843 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 844 } else { 845 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 846 } 847 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 848 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 849 #if defined(CONFIG_DRM_AMD_DC) 850 else if (amdgpu_device_has_dc_support(adev)) 851 amdgpu_device_ip_block_add(adev, &dm_ip_block); 852 #endif 853 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { 854 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 855 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 856 } 857 break; 858 case CHIP_RAVEN: 859 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 860 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 861 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 862 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 863 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 864 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 865 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 866 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 867 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 868 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 869 #if defined(CONFIG_DRM_AMD_DC) 870 else if (amdgpu_device_has_dc_support(adev)) 871 amdgpu_device_ip_block_add(adev, &dm_ip_block); 872 #endif 873 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 874 break; 875 case CHIP_ARCTURUS: 876 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 877 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 878 879 if (amdgpu_sriov_vf(adev)) { 880 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 881 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 882 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 883 } else { 884 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 885 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 886 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 887 } 888 889 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 890 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 891 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 892 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 893 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 894 895 if (amdgpu_sriov_vf(adev)) { 896 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 897 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 898 } else { 899 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 900 } 901 if (!amdgpu_sriov_vf(adev)) 902 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 903 break; 904 case CHIP_RENOIR: 905 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 906 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 907 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 908 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 909 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 910 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 911 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 912 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 913 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 914 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 915 #if defined(CONFIG_DRM_AMD_DC) 916 else if (amdgpu_device_has_dc_support(adev)) 917 amdgpu_device_ip_block_add(adev, &dm_ip_block); 918 #endif 919 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 920 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 921 break; 922 case CHIP_ALDEBARAN: 923 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 924 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 925 926 if (amdgpu_sriov_vf(adev)) { 927 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 928 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 929 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 930 } else { 931 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 932 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 933 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 934 } 935 936 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 937 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 938 939 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 940 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 941 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 942 break; 943 default: 944 return -EINVAL; 945 } 946 947 return 0; 948 } 949 950 static bool soc15_need_full_reset(struct amdgpu_device *adev) 951 { 952 /* change this when we implement soft reset */ 953 return true; 954 } 955 956 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 957 uint64_t *count1) 958 { 959 uint32_t perfctr = 0; 960 uint64_t cnt0_of, cnt1_of; 961 int tmp; 962 963 /* This reports 0 on APUs, so return to avoid writing/reading registers 964 * that may or may not be different from their GPU counterparts 965 */ 966 if (adev->flags & AMD_IS_APU) 967 return; 968 969 /* Set the 2 events that we wish to watch, defined above */ 970 /* Reg 40 is # received msgs */ 971 /* Reg 104 is # of posted requests sent */ 972 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 973 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 974 975 /* Write to enable desired perf counters */ 976 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 977 /* Zero out and enable the perf counters 978 * Write 0x5: 979 * Bit 0 = Start all counters(1) 980 * Bit 2 = Global counter reset enable(1) 981 */ 982 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 983 984 msleep(1000); 985 986 /* Load the shadow and disable the perf counters 987 * Write 0x2: 988 * Bit 0 = Stop counters(0) 989 * Bit 1 = Load the shadow counters(1) 990 */ 991 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 992 993 /* Read register values to get any >32bit overflow */ 994 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 995 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 996 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 997 998 /* Get the values and add the overflow */ 999 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 1000 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 1001 } 1002 1003 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 1004 uint64_t *count1) 1005 { 1006 uint32_t perfctr = 0; 1007 uint64_t cnt0_of, cnt1_of; 1008 int tmp; 1009 1010 /* This reports 0 on APUs, so return to avoid writing/reading registers 1011 * that may or may not be different from their GPU counterparts 1012 */ 1013 if (adev->flags & AMD_IS_APU) 1014 return; 1015 1016 /* Set the 2 events that we wish to watch, defined above */ 1017 /* Reg 40 is # received msgs */ 1018 /* Reg 108 is # of posted requests sent on VG20 */ 1019 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 1020 EVENT0_SEL, 40); 1021 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 1022 EVENT1_SEL, 108); 1023 1024 /* Write to enable desired perf counters */ 1025 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 1026 /* Zero out and enable the perf counters 1027 * Write 0x5: 1028 * Bit 0 = Start all counters(1) 1029 * Bit 2 = Global counter reset enable(1) 1030 */ 1031 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 1032 1033 msleep(1000); 1034 1035 /* Load the shadow and disable the perf counters 1036 * Write 0x2: 1037 * Bit 0 = Stop counters(0) 1038 * Bit 1 = Load the shadow counters(1) 1039 */ 1040 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 1041 1042 /* Read register values to get any >32bit overflow */ 1043 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 1044 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 1045 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 1046 1047 /* Get the values and add the overflow */ 1048 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 1049 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 1050 } 1051 1052 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 1053 { 1054 u32 sol_reg; 1055 1056 /* Just return false for soc15 GPUs. Reset does not seem to 1057 * be necessary. 1058 */ 1059 if (!amdgpu_passthrough(adev)) 1060 return false; 1061 1062 if (adev->flags & AMD_IS_APU) 1063 return false; 1064 1065 /* Check sOS sign of life register to confirm sys driver and sOS 1066 * are already been loaded. 1067 */ 1068 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 1069 if (sol_reg) 1070 return true; 1071 1072 return false; 1073 } 1074 1075 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 1076 { 1077 uint64_t nak_r, nak_g; 1078 1079 /* Get the number of NAKs received and generated */ 1080 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 1081 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 1082 1083 /* Add the total number of NAKs, i.e the number of replays */ 1084 return (nak_r + nak_g); 1085 } 1086 1087 static void soc15_pre_asic_init(struct amdgpu_device *adev) 1088 { 1089 gmc_v9_0_restore_registers(adev); 1090 } 1091 1092 static const struct amdgpu_asic_funcs soc15_asic_funcs = 1093 { 1094 .read_disabled_bios = &soc15_read_disabled_bios, 1095 .read_bios_from_rom = &soc15_read_bios_from_rom, 1096 .read_register = &soc15_read_register, 1097 .reset = &soc15_asic_reset, 1098 .reset_method = &soc15_asic_reset_method, 1099 .set_vga_state = &soc15_vga_set_state, 1100 .get_xclk = &soc15_get_xclk, 1101 .set_uvd_clocks = &soc15_set_uvd_clocks, 1102 .set_vce_clocks = &soc15_set_vce_clocks, 1103 .get_config_memsize = &soc15_get_config_memsize, 1104 .need_full_reset = &soc15_need_full_reset, 1105 .init_doorbell_index = &vega10_doorbell_index_init, 1106 .get_pcie_usage = &soc15_get_pcie_usage, 1107 .need_reset_on_init = &soc15_need_reset_on_init, 1108 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1109 .supports_baco = &soc15_supports_baco, 1110 .pre_asic_init = &soc15_pre_asic_init, 1111 .query_video_codecs = &soc15_query_video_codecs, 1112 }; 1113 1114 static const struct amdgpu_asic_funcs vega20_asic_funcs = 1115 { 1116 .read_disabled_bios = &soc15_read_disabled_bios, 1117 .read_bios_from_rom = &soc15_read_bios_from_rom, 1118 .read_register = &soc15_read_register, 1119 .reset = &soc15_asic_reset, 1120 .reset_method = &soc15_asic_reset_method, 1121 .set_vga_state = &soc15_vga_set_state, 1122 .get_xclk = &soc15_get_xclk, 1123 .set_uvd_clocks = &soc15_set_uvd_clocks, 1124 .set_vce_clocks = &soc15_set_vce_clocks, 1125 .get_config_memsize = &soc15_get_config_memsize, 1126 .need_full_reset = &soc15_need_full_reset, 1127 .init_doorbell_index = &vega20_doorbell_index_init, 1128 .get_pcie_usage = &vega20_get_pcie_usage, 1129 .need_reset_on_init = &soc15_need_reset_on_init, 1130 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1131 .supports_baco = &soc15_supports_baco, 1132 .pre_asic_init = &soc15_pre_asic_init, 1133 .query_video_codecs = &soc15_query_video_codecs, 1134 }; 1135 1136 static int soc15_common_early_init(void *handle) 1137 { 1138 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 1139 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1140 1141 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 1142 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 1143 adev->smc_rreg = NULL; 1144 adev->smc_wreg = NULL; 1145 adev->pcie_rreg = &soc15_pcie_rreg; 1146 adev->pcie_wreg = &soc15_pcie_wreg; 1147 adev->pcie_rreg64 = &soc15_pcie_rreg64; 1148 adev->pcie_wreg64 = &soc15_pcie_wreg64; 1149 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 1150 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 1151 adev->didt_rreg = &soc15_didt_rreg; 1152 adev->didt_wreg = &soc15_didt_wreg; 1153 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 1154 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 1155 adev->se_cac_rreg = &soc15_se_cac_rreg; 1156 adev->se_cac_wreg = &soc15_se_cac_wreg; 1157 1158 1159 adev->external_rev_id = 0xFF; 1160 switch (adev->asic_type) { 1161 case CHIP_VEGA10: 1162 adev->asic_funcs = &soc15_asic_funcs; 1163 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1164 AMD_CG_SUPPORT_GFX_MGLS | 1165 AMD_CG_SUPPORT_GFX_RLC_LS | 1166 AMD_CG_SUPPORT_GFX_CP_LS | 1167 AMD_CG_SUPPORT_GFX_3D_CGCG | 1168 AMD_CG_SUPPORT_GFX_3D_CGLS | 1169 AMD_CG_SUPPORT_GFX_CGCG | 1170 AMD_CG_SUPPORT_GFX_CGLS | 1171 AMD_CG_SUPPORT_BIF_MGCG | 1172 AMD_CG_SUPPORT_BIF_LS | 1173 AMD_CG_SUPPORT_HDP_LS | 1174 AMD_CG_SUPPORT_DRM_MGCG | 1175 AMD_CG_SUPPORT_DRM_LS | 1176 AMD_CG_SUPPORT_ROM_MGCG | 1177 AMD_CG_SUPPORT_DF_MGCG | 1178 AMD_CG_SUPPORT_SDMA_MGCG | 1179 AMD_CG_SUPPORT_SDMA_LS | 1180 AMD_CG_SUPPORT_MC_MGCG | 1181 AMD_CG_SUPPORT_MC_LS; 1182 adev->pg_flags = 0; 1183 adev->external_rev_id = 0x1; 1184 break; 1185 case CHIP_VEGA12: 1186 adev->asic_funcs = &soc15_asic_funcs; 1187 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1188 AMD_CG_SUPPORT_GFX_MGLS | 1189 AMD_CG_SUPPORT_GFX_CGCG | 1190 AMD_CG_SUPPORT_GFX_CGLS | 1191 AMD_CG_SUPPORT_GFX_3D_CGCG | 1192 AMD_CG_SUPPORT_GFX_3D_CGLS | 1193 AMD_CG_SUPPORT_GFX_CP_LS | 1194 AMD_CG_SUPPORT_MC_LS | 1195 AMD_CG_SUPPORT_MC_MGCG | 1196 AMD_CG_SUPPORT_SDMA_MGCG | 1197 AMD_CG_SUPPORT_SDMA_LS | 1198 AMD_CG_SUPPORT_BIF_MGCG | 1199 AMD_CG_SUPPORT_BIF_LS | 1200 AMD_CG_SUPPORT_HDP_MGCG | 1201 AMD_CG_SUPPORT_HDP_LS | 1202 AMD_CG_SUPPORT_ROM_MGCG | 1203 AMD_CG_SUPPORT_VCE_MGCG | 1204 AMD_CG_SUPPORT_UVD_MGCG; 1205 adev->pg_flags = 0; 1206 adev->external_rev_id = adev->rev_id + 0x14; 1207 break; 1208 case CHIP_VEGA20: 1209 adev->asic_funcs = &vega20_asic_funcs; 1210 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1211 AMD_CG_SUPPORT_GFX_MGLS | 1212 AMD_CG_SUPPORT_GFX_CGCG | 1213 AMD_CG_SUPPORT_GFX_CGLS | 1214 AMD_CG_SUPPORT_GFX_3D_CGCG | 1215 AMD_CG_SUPPORT_GFX_3D_CGLS | 1216 AMD_CG_SUPPORT_GFX_CP_LS | 1217 AMD_CG_SUPPORT_MC_LS | 1218 AMD_CG_SUPPORT_MC_MGCG | 1219 AMD_CG_SUPPORT_SDMA_MGCG | 1220 AMD_CG_SUPPORT_SDMA_LS | 1221 AMD_CG_SUPPORT_BIF_MGCG | 1222 AMD_CG_SUPPORT_BIF_LS | 1223 AMD_CG_SUPPORT_HDP_MGCG | 1224 AMD_CG_SUPPORT_HDP_LS | 1225 AMD_CG_SUPPORT_ROM_MGCG | 1226 AMD_CG_SUPPORT_VCE_MGCG | 1227 AMD_CG_SUPPORT_UVD_MGCG; 1228 adev->pg_flags = 0; 1229 adev->external_rev_id = adev->rev_id + 0x28; 1230 break; 1231 case CHIP_RAVEN: 1232 adev->asic_funcs = &soc15_asic_funcs; 1233 1234 if (adev->rev_id >= 0x8) 1235 adev->apu_flags |= AMD_APU_IS_RAVEN2; 1236 1237 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1238 adev->external_rev_id = adev->rev_id + 0x79; 1239 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1240 adev->external_rev_id = adev->rev_id + 0x41; 1241 else if (adev->rev_id == 1) 1242 adev->external_rev_id = adev->rev_id + 0x20; 1243 else 1244 adev->external_rev_id = adev->rev_id + 0x01; 1245 1246 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1247 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1248 AMD_CG_SUPPORT_GFX_MGLS | 1249 AMD_CG_SUPPORT_GFX_CP_LS | 1250 AMD_CG_SUPPORT_GFX_3D_CGCG | 1251 AMD_CG_SUPPORT_GFX_3D_CGLS | 1252 AMD_CG_SUPPORT_GFX_CGCG | 1253 AMD_CG_SUPPORT_GFX_CGLS | 1254 AMD_CG_SUPPORT_BIF_LS | 1255 AMD_CG_SUPPORT_HDP_LS | 1256 AMD_CG_SUPPORT_MC_MGCG | 1257 AMD_CG_SUPPORT_MC_LS | 1258 AMD_CG_SUPPORT_SDMA_MGCG | 1259 AMD_CG_SUPPORT_SDMA_LS | 1260 AMD_CG_SUPPORT_VCN_MGCG; 1261 1262 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1263 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { 1264 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1265 AMD_CG_SUPPORT_GFX_MGLS | 1266 AMD_CG_SUPPORT_GFX_CP_LS | 1267 AMD_CG_SUPPORT_GFX_3D_CGLS | 1268 AMD_CG_SUPPORT_GFX_CGCG | 1269 AMD_CG_SUPPORT_GFX_CGLS | 1270 AMD_CG_SUPPORT_BIF_LS | 1271 AMD_CG_SUPPORT_HDP_LS | 1272 AMD_CG_SUPPORT_MC_MGCG | 1273 AMD_CG_SUPPORT_MC_LS | 1274 AMD_CG_SUPPORT_SDMA_MGCG | 1275 AMD_CG_SUPPORT_SDMA_LS | 1276 AMD_CG_SUPPORT_VCN_MGCG; 1277 1278 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1279 AMD_PG_SUPPORT_MMHUB | 1280 AMD_PG_SUPPORT_VCN; 1281 } else { 1282 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1283 AMD_CG_SUPPORT_GFX_MGLS | 1284 AMD_CG_SUPPORT_GFX_RLC_LS | 1285 AMD_CG_SUPPORT_GFX_CP_LS | 1286 AMD_CG_SUPPORT_GFX_3D_CGLS | 1287 AMD_CG_SUPPORT_GFX_CGCG | 1288 AMD_CG_SUPPORT_GFX_CGLS | 1289 AMD_CG_SUPPORT_BIF_MGCG | 1290 AMD_CG_SUPPORT_BIF_LS | 1291 AMD_CG_SUPPORT_HDP_MGCG | 1292 AMD_CG_SUPPORT_HDP_LS | 1293 AMD_CG_SUPPORT_DRM_MGCG | 1294 AMD_CG_SUPPORT_DRM_LS | 1295 AMD_CG_SUPPORT_MC_MGCG | 1296 AMD_CG_SUPPORT_MC_LS | 1297 AMD_CG_SUPPORT_SDMA_MGCG | 1298 AMD_CG_SUPPORT_SDMA_LS | 1299 AMD_CG_SUPPORT_VCN_MGCG; 1300 1301 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1302 } 1303 break; 1304 case CHIP_ARCTURUS: 1305 adev->asic_funcs = &vega20_asic_funcs; 1306 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1307 AMD_CG_SUPPORT_GFX_MGLS | 1308 AMD_CG_SUPPORT_GFX_CGCG | 1309 AMD_CG_SUPPORT_GFX_CGLS | 1310 AMD_CG_SUPPORT_GFX_CP_LS | 1311 AMD_CG_SUPPORT_HDP_MGCG | 1312 AMD_CG_SUPPORT_HDP_LS | 1313 AMD_CG_SUPPORT_SDMA_MGCG | 1314 AMD_CG_SUPPORT_SDMA_LS | 1315 AMD_CG_SUPPORT_MC_MGCG | 1316 AMD_CG_SUPPORT_MC_LS | 1317 AMD_CG_SUPPORT_IH_CG | 1318 AMD_CG_SUPPORT_VCN_MGCG | 1319 AMD_CG_SUPPORT_JPEG_MGCG; 1320 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; 1321 adev->external_rev_id = adev->rev_id + 0x32; 1322 break; 1323 case CHIP_RENOIR: 1324 adev->asic_funcs = &soc15_asic_funcs; 1325 1326 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1327 adev->external_rev_id = adev->rev_id + 0x91; 1328 else 1329 adev->external_rev_id = adev->rev_id + 0xa1; 1330 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1331 AMD_CG_SUPPORT_GFX_MGLS | 1332 AMD_CG_SUPPORT_GFX_3D_CGCG | 1333 AMD_CG_SUPPORT_GFX_3D_CGLS | 1334 AMD_CG_SUPPORT_GFX_CGCG | 1335 AMD_CG_SUPPORT_GFX_CGLS | 1336 AMD_CG_SUPPORT_GFX_CP_LS | 1337 AMD_CG_SUPPORT_MC_MGCG | 1338 AMD_CG_SUPPORT_MC_LS | 1339 AMD_CG_SUPPORT_SDMA_MGCG | 1340 AMD_CG_SUPPORT_SDMA_LS | 1341 AMD_CG_SUPPORT_BIF_LS | 1342 AMD_CG_SUPPORT_HDP_LS | 1343 AMD_CG_SUPPORT_VCN_MGCG | 1344 AMD_CG_SUPPORT_JPEG_MGCG | 1345 AMD_CG_SUPPORT_IH_CG | 1346 AMD_CG_SUPPORT_ATHUB_LS | 1347 AMD_CG_SUPPORT_ATHUB_MGCG | 1348 AMD_CG_SUPPORT_DF_MGCG; 1349 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1350 AMD_PG_SUPPORT_VCN | 1351 AMD_PG_SUPPORT_JPEG | 1352 AMD_PG_SUPPORT_VCN_DPG; 1353 break; 1354 case CHIP_ALDEBARAN: 1355 adev->asic_funcs = &vega20_asic_funcs; 1356 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1357 AMD_CG_SUPPORT_GFX_MGLS | 1358 AMD_CG_SUPPORT_GFX_CP_LS | 1359 AMD_CG_SUPPORT_HDP_LS | 1360 AMD_CG_SUPPORT_SDMA_MGCG | 1361 AMD_CG_SUPPORT_SDMA_LS | 1362 AMD_CG_SUPPORT_IH_CG | 1363 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; 1364 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 1365 adev->external_rev_id = adev->rev_id + 0x3c; 1366 break; 1367 default: 1368 /* FIXME: not supported yet */ 1369 return -EINVAL; 1370 } 1371 1372 if (amdgpu_sriov_vf(adev)) { 1373 amdgpu_virt_init_setting(adev); 1374 xgpu_ai_mailbox_set_irq_funcs(adev); 1375 } 1376 1377 return 0; 1378 } 1379 1380 static int soc15_common_late_init(void *handle) 1381 { 1382 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1383 int r = 0; 1384 1385 if (amdgpu_sriov_vf(adev)) 1386 xgpu_ai_mailbox_get_irq(adev); 1387 1388 if (adev->nbio.ras_funcs && 1389 adev->nbio.ras_funcs->ras_late_init) 1390 r = adev->nbio.ras_funcs->ras_late_init(adev); 1391 1392 return r; 1393 } 1394 1395 static int soc15_common_sw_init(void *handle) 1396 { 1397 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1398 1399 if (amdgpu_sriov_vf(adev)) 1400 xgpu_ai_mailbox_add_irq_id(adev); 1401 1402 adev->df.funcs->sw_init(adev); 1403 1404 return 0; 1405 } 1406 1407 static int soc15_common_sw_fini(void *handle) 1408 { 1409 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1410 1411 if (adev->nbio.ras_funcs && 1412 adev->nbio.ras_funcs->ras_fini) 1413 adev->nbio.ras_funcs->ras_fini(adev); 1414 adev->df.funcs->sw_fini(adev); 1415 return 0; 1416 } 1417 1418 static void soc15_doorbell_range_init(struct amdgpu_device *adev) 1419 { 1420 int i; 1421 struct amdgpu_ring *ring; 1422 1423 /* sdma/ih doorbell range are programed by hypervisor */ 1424 if (!amdgpu_sriov_vf(adev)) { 1425 for (i = 0; i < adev->sdma.num_instances; i++) { 1426 ring = &adev->sdma.instance[i].ring; 1427 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1428 ring->use_doorbell, ring->doorbell_index, 1429 adev->doorbell_index.sdma_doorbell_range); 1430 } 1431 1432 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 1433 adev->irq.ih.doorbell_index); 1434 } 1435 } 1436 1437 static int soc15_common_hw_init(void *handle) 1438 { 1439 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1440 1441 /* enable pcie gen2/3 link */ 1442 soc15_pcie_gen3_enable(adev); 1443 /* enable aspm */ 1444 soc15_program_aspm(adev); 1445 /* setup nbio registers */ 1446 adev->nbio.funcs->init_registers(adev); 1447 /* remap HDP registers to a hole in mmio space, 1448 * for the purpose of expose those registers 1449 * to process space 1450 */ 1451 if (adev->nbio.funcs->remap_hdp_registers) 1452 adev->nbio.funcs->remap_hdp_registers(adev); 1453 1454 /* enable the doorbell aperture */ 1455 soc15_enable_doorbell_aperture(adev, true); 1456 /* HW doorbell routing policy: doorbell writing not 1457 * in SDMA/IH/MM/ACV range will be routed to CP. So 1458 * we need to init SDMA/IH/MM/ACV doorbell range prior 1459 * to CP ip block init and ring test. 1460 */ 1461 soc15_doorbell_range_init(adev); 1462 1463 return 0; 1464 } 1465 1466 static int soc15_common_hw_fini(void *handle) 1467 { 1468 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1469 1470 /* disable the doorbell aperture */ 1471 soc15_enable_doorbell_aperture(adev, false); 1472 if (amdgpu_sriov_vf(adev)) 1473 xgpu_ai_mailbox_put_irq(adev); 1474 1475 if (adev->nbio.ras_if && 1476 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1477 if (adev->nbio.ras_funcs && 1478 adev->nbio.ras_funcs->init_ras_controller_interrupt) 1479 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1480 if (adev->nbio.ras_funcs && 1481 adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) 1482 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1483 } 1484 1485 return 0; 1486 } 1487 1488 static int soc15_common_suspend(void *handle) 1489 { 1490 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1491 1492 return soc15_common_hw_fini(adev); 1493 } 1494 1495 static int soc15_common_resume(void *handle) 1496 { 1497 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1498 1499 return soc15_common_hw_init(adev); 1500 } 1501 1502 static bool soc15_common_is_idle(void *handle) 1503 { 1504 return true; 1505 } 1506 1507 static int soc15_common_wait_for_idle(void *handle) 1508 { 1509 return 0; 1510 } 1511 1512 static int soc15_common_soft_reset(void *handle) 1513 { 1514 return 0; 1515 } 1516 1517 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1518 { 1519 uint32_t def, data; 1520 1521 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1522 1523 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1524 data &= ~(0x01000000 | 1525 0x02000000 | 1526 0x04000000 | 1527 0x08000000 | 1528 0x10000000 | 1529 0x20000000 | 1530 0x40000000 | 1531 0x80000000); 1532 else 1533 data |= (0x01000000 | 1534 0x02000000 | 1535 0x04000000 | 1536 0x08000000 | 1537 0x10000000 | 1538 0x20000000 | 1539 0x40000000 | 1540 0x80000000); 1541 1542 if (def != data) 1543 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1544 } 1545 1546 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1547 { 1548 uint32_t def, data; 1549 1550 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1551 1552 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1553 data |= 1; 1554 else 1555 data &= ~1; 1556 1557 if (def != data) 1558 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1559 } 1560 1561 static int soc15_common_set_clockgating_state(void *handle, 1562 enum amd_clockgating_state state) 1563 { 1564 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1565 1566 if (amdgpu_sriov_vf(adev)) 1567 return 0; 1568 1569 switch (adev->asic_type) { 1570 case CHIP_VEGA10: 1571 case CHIP_VEGA12: 1572 case CHIP_VEGA20: 1573 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1574 state == AMD_CG_STATE_GATE); 1575 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1576 state == AMD_CG_STATE_GATE); 1577 adev->hdp.funcs->update_clock_gating(adev, 1578 state == AMD_CG_STATE_GATE); 1579 soc15_update_drm_clock_gating(adev, 1580 state == AMD_CG_STATE_GATE); 1581 soc15_update_drm_light_sleep(adev, 1582 state == AMD_CG_STATE_GATE); 1583 adev->smuio.funcs->update_rom_clock_gating(adev, 1584 state == AMD_CG_STATE_GATE); 1585 adev->df.funcs->update_medium_grain_clock_gating(adev, 1586 state == AMD_CG_STATE_GATE); 1587 break; 1588 case CHIP_RAVEN: 1589 case CHIP_RENOIR: 1590 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1591 state == AMD_CG_STATE_GATE); 1592 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1593 state == AMD_CG_STATE_GATE); 1594 adev->hdp.funcs->update_clock_gating(adev, 1595 state == AMD_CG_STATE_GATE); 1596 soc15_update_drm_clock_gating(adev, 1597 state == AMD_CG_STATE_GATE); 1598 soc15_update_drm_light_sleep(adev, 1599 state == AMD_CG_STATE_GATE); 1600 break; 1601 case CHIP_ARCTURUS: 1602 case CHIP_ALDEBARAN: 1603 adev->hdp.funcs->update_clock_gating(adev, 1604 state == AMD_CG_STATE_GATE); 1605 break; 1606 default: 1607 break; 1608 } 1609 return 0; 1610 } 1611 1612 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1613 { 1614 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1615 int data; 1616 1617 if (amdgpu_sriov_vf(adev)) 1618 *flags = 0; 1619 1620 adev->nbio.funcs->get_clockgating_state(adev, flags); 1621 1622 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1623 1624 if (adev->asic_type != CHIP_ALDEBARAN) { 1625 1626 /* AMD_CG_SUPPORT_DRM_MGCG */ 1627 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1628 if (!(data & 0x01000000)) 1629 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1630 1631 /* AMD_CG_SUPPORT_DRM_LS */ 1632 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1633 if (data & 0x1) 1634 *flags |= AMD_CG_SUPPORT_DRM_LS; 1635 } 1636 1637 /* AMD_CG_SUPPORT_ROM_MGCG */ 1638 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1639 1640 adev->df.funcs->get_clockgating_state(adev, flags); 1641 } 1642 1643 static int soc15_common_set_powergating_state(void *handle, 1644 enum amd_powergating_state state) 1645 { 1646 /* todo */ 1647 return 0; 1648 } 1649 1650 static const struct amd_ip_funcs soc15_common_ip_funcs = { 1651 .name = "soc15_common", 1652 .early_init = soc15_common_early_init, 1653 .late_init = soc15_common_late_init, 1654 .sw_init = soc15_common_sw_init, 1655 .sw_fini = soc15_common_sw_fini, 1656 .hw_init = soc15_common_hw_init, 1657 .hw_fini = soc15_common_hw_fini, 1658 .suspend = soc15_common_suspend, 1659 .resume = soc15_common_resume, 1660 .is_idle = soc15_common_is_idle, 1661 .wait_for_idle = soc15_common_wait_for_idle, 1662 .soft_reset = soc15_common_soft_reset, 1663 .set_clockgating_state = soc15_common_set_clockgating_state, 1664 .set_powergating_state = soc15_common_set_powergating_state, 1665 .get_clockgating_state= soc15_common_get_clockgating_state, 1666 }; 1667