1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "atom.h" 36 #include "amd_pcie.h" 37 38 #include "uvd/uvd_7_0_offset.h" 39 #include "gc/gc_9_0_offset.h" 40 #include "gc/gc_9_0_sh_mask.h" 41 #include "sdma0/sdma0_4_0_offset.h" 42 #include "sdma1/sdma1_4_0_offset.h" 43 #include "hdp/hdp_4_0_offset.h" 44 #include "hdp/hdp_4_0_sh_mask.h" 45 #include "smuio/smuio_9_0_offset.h" 46 #include "smuio/smuio_9_0_sh_mask.h" 47 #include "nbio/nbio_7_0_default.h" 48 #include "nbio/nbio_7_0_offset.h" 49 #include "nbio/nbio_7_0_sh_mask.h" 50 #include "nbio/nbio_7_0_smn.h" 51 #include "mp/mp_9_0_offset.h" 52 53 #include "soc15.h" 54 #include "soc15_common.h" 55 #include "gfx_v9_0.h" 56 #include "gmc_v9_0.h" 57 #include "gfxhub_v1_0.h" 58 #include "mmhub_v1_0.h" 59 #include "df_v1_7.h" 60 #include "df_v3_6.h" 61 #include "nbio_v6_1.h" 62 #include "nbio_v7_0.h" 63 #include "nbio_v7_4.h" 64 #include "vega10_ih.h" 65 #include "sdma_v4_0.h" 66 #include "uvd_v7_0.h" 67 #include "vce_v4_0.h" 68 #include "vcn_v1_0.h" 69 #include "vcn_v2_0.h" 70 #include "jpeg_v2_0.h" 71 #include "vcn_v2_5.h" 72 #include "jpeg_v2_5.h" 73 #include "dce_virtual.h" 74 #include "mxgpu_ai.h" 75 #include "amdgpu_smu.h" 76 #include "amdgpu_ras.h" 77 #include "amdgpu_xgmi.h" 78 #include <uapi/linux/kfd_ioctl.h> 79 80 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 81 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 82 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 84 85 /* for Vega20 register name change */ 86 #define mmHDP_MEM_POWER_CTRL 0x00d4 87 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 89 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 91 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 92 /* 93 * Indirect registers accessor 94 */ 95 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 96 { 97 unsigned long flags, address, data; 98 u32 r; 99 address = adev->nbio.funcs->get_pcie_index_offset(adev); 100 data = adev->nbio.funcs->get_pcie_data_offset(adev); 101 102 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 103 WREG32(address, reg); 104 (void)RREG32(address); 105 r = RREG32(data); 106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 107 return r; 108 } 109 110 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 111 { 112 unsigned long flags, address, data; 113 114 address = adev->nbio.funcs->get_pcie_index_offset(adev); 115 data = adev->nbio.funcs->get_pcie_data_offset(adev); 116 117 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 118 WREG32(address, reg); 119 (void)RREG32(address); 120 WREG32(data, v); 121 (void)RREG32(data); 122 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 123 } 124 125 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 126 { 127 unsigned long flags, address, data; 128 u64 r; 129 address = adev->nbio.funcs->get_pcie_index_offset(adev); 130 data = adev->nbio.funcs->get_pcie_data_offset(adev); 131 132 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 133 /* read low 32 bit */ 134 WREG32(address, reg); 135 (void)RREG32(address); 136 r = RREG32(data); 137 138 /* read high 32 bit*/ 139 WREG32(address, reg + 4); 140 (void)RREG32(address); 141 r |= ((u64)RREG32(data) << 32); 142 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 143 return r; 144 } 145 146 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 147 { 148 unsigned long flags, address, data; 149 150 address = adev->nbio.funcs->get_pcie_index_offset(adev); 151 data = adev->nbio.funcs->get_pcie_data_offset(adev); 152 153 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 154 /* write low 32 bit */ 155 WREG32(address, reg); 156 (void)RREG32(address); 157 WREG32(data, (u32)(v & 0xffffffffULL)); 158 (void)RREG32(data); 159 160 /* write high 32 bit */ 161 WREG32(address, reg + 4); 162 (void)RREG32(address); 163 WREG32(data, (u32)(v >> 32)); 164 (void)RREG32(data); 165 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 166 } 167 168 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 169 { 170 unsigned long flags, address, data; 171 u32 r; 172 173 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 174 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 175 176 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 177 WREG32(address, ((reg) & 0x1ff)); 178 r = RREG32(data); 179 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 180 return r; 181 } 182 183 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 184 { 185 unsigned long flags, address, data; 186 187 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 188 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 189 190 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 191 WREG32(address, ((reg) & 0x1ff)); 192 WREG32(data, (v)); 193 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 194 } 195 196 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 197 { 198 unsigned long flags, address, data; 199 u32 r; 200 201 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 202 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 203 204 spin_lock_irqsave(&adev->didt_idx_lock, flags); 205 WREG32(address, (reg)); 206 r = RREG32(data); 207 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 208 return r; 209 } 210 211 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 212 { 213 unsigned long flags, address, data; 214 215 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 216 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 217 218 spin_lock_irqsave(&adev->didt_idx_lock, flags); 219 WREG32(address, (reg)); 220 WREG32(data, (v)); 221 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 222 } 223 224 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 225 { 226 unsigned long flags; 227 u32 r; 228 229 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 230 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 231 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 232 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 233 return r; 234 } 235 236 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 237 { 238 unsigned long flags; 239 240 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 241 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 242 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 243 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 244 } 245 246 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 247 { 248 unsigned long flags; 249 u32 r; 250 251 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 252 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 253 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 254 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 255 return r; 256 } 257 258 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 259 { 260 unsigned long flags; 261 262 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 263 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 264 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 265 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 266 } 267 268 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 269 { 270 return adev->nbio.funcs->get_memsize(adev); 271 } 272 273 static u32 soc15_get_xclk(struct amdgpu_device *adev) 274 { 275 return adev->clock.spll.reference_freq; 276 } 277 278 279 void soc15_grbm_select(struct amdgpu_device *adev, 280 u32 me, u32 pipe, u32 queue, u32 vmid) 281 { 282 u32 grbm_gfx_cntl = 0; 283 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 284 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 285 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 286 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 287 288 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 289 } 290 291 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 292 { 293 /* todo */ 294 } 295 296 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 297 { 298 /* todo */ 299 return false; 300 } 301 302 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 303 u8 *bios, u32 length_bytes) 304 { 305 u32 *dw_ptr; 306 u32 i, length_dw; 307 308 if (bios == NULL) 309 return false; 310 if (length_bytes == 0) 311 return false; 312 /* APU vbios image is part of sbios image */ 313 if (adev->flags & AMD_IS_APU) 314 return false; 315 316 dw_ptr = (u32 *)bios; 317 length_dw = ALIGN(length_bytes, 4) / 4; 318 319 /* set rom index to 0 */ 320 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 321 /* read out the rom data */ 322 for (i = 0; i < length_dw; i++) 323 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 324 325 return true; 326 } 327 328 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 329 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 330 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 331 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 332 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 333 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 334 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 335 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 336 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 337 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 338 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 339 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 340 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 341 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 342 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 343 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 344 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 345 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 346 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 347 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 348 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 349 }; 350 351 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 352 u32 sh_num, u32 reg_offset) 353 { 354 uint32_t val; 355 356 mutex_lock(&adev->grbm_idx_mutex); 357 if (se_num != 0xffffffff || sh_num != 0xffffffff) 358 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 359 360 val = RREG32(reg_offset); 361 362 if (se_num != 0xffffffff || sh_num != 0xffffffff) 363 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 364 mutex_unlock(&adev->grbm_idx_mutex); 365 return val; 366 } 367 368 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 369 bool indexed, u32 se_num, 370 u32 sh_num, u32 reg_offset) 371 { 372 if (indexed) { 373 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 374 } else { 375 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 376 return adev->gfx.config.gb_addr_config; 377 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 378 return adev->gfx.config.db_debug2; 379 return RREG32(reg_offset); 380 } 381 } 382 383 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 384 u32 sh_num, u32 reg_offset, u32 *value) 385 { 386 uint32_t i; 387 struct soc15_allowed_register_entry *en; 388 389 *value = 0; 390 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 391 en = &soc15_allowed_read_registers[i]; 392 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 393 + en->reg_offset)) 394 continue; 395 396 *value = soc15_get_register_value(adev, 397 soc15_allowed_read_registers[i].grbm_indexed, 398 se_num, sh_num, reg_offset); 399 return 0; 400 } 401 return -EINVAL; 402 } 403 404 405 /** 406 * soc15_program_register_sequence - program an array of registers. 407 * 408 * @adev: amdgpu_device pointer 409 * @regs: pointer to the register array 410 * @array_size: size of the register array 411 * 412 * Programs an array or registers with and and or masks. 413 * This is a helper for setting golden registers. 414 */ 415 416 void soc15_program_register_sequence(struct amdgpu_device *adev, 417 const struct soc15_reg_golden *regs, 418 const u32 array_size) 419 { 420 const struct soc15_reg_golden *entry; 421 u32 tmp, reg; 422 int i; 423 424 for (i = 0; i < array_size; ++i) { 425 entry = ®s[i]; 426 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 427 428 if (entry->and_mask == 0xffffffff) { 429 tmp = entry->or_mask; 430 } else { 431 tmp = RREG32(reg); 432 tmp &= ~(entry->and_mask); 433 tmp |= (entry->or_mask & entry->and_mask); 434 } 435 436 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 437 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 438 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 439 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 440 WREG32_RLC(reg, tmp); 441 else 442 WREG32(reg, tmp); 443 444 } 445 446 } 447 448 static int soc15_asic_mode1_reset(struct amdgpu_device *adev) 449 { 450 u32 i; 451 int ret = 0; 452 453 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 454 455 dev_info(adev->dev, "GPU mode1 reset\n"); 456 457 /* disable BM */ 458 pci_clear_master(adev->pdev); 459 460 pci_save_state(adev->pdev); 461 462 ret = psp_gpu_reset(adev); 463 if (ret) 464 dev_err(adev->dev, "GPU mode1 reset failed\n"); 465 466 pci_restore_state(adev->pdev); 467 468 /* wait for asic to come out of reset */ 469 for (i = 0; i < adev->usec_timeout; i++) { 470 u32 memsize = adev->nbio.funcs->get_memsize(adev); 471 472 if (memsize != 0xffffffff) 473 break; 474 udelay(1); 475 } 476 477 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 478 479 return ret; 480 } 481 482 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap) 483 { 484 if (is_support_sw_smu(adev)) { 485 struct smu_context *smu = &adev->smu; 486 487 *cap = smu_baco_is_support(smu); 488 return 0; 489 } else { 490 void *pp_handle = adev->powerplay.pp_handle; 491 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 492 493 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) { 494 *cap = false; 495 return -ENOENT; 496 } 497 498 return pp_funcs->get_asic_baco_capability(pp_handle, cap); 499 } 500 } 501 502 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 503 { 504 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 505 506 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 507 if (ras && ras->supported) 508 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 509 510 dev_info(adev->dev, "GPU BACO reset\n"); 511 512 if (is_support_sw_smu(adev)) { 513 struct smu_context *smu = &adev->smu; 514 int ret; 515 516 ret = smu_baco_enter(smu); 517 if (ret) 518 return ret; 519 520 ret = smu_baco_exit(smu); 521 if (ret) 522 return ret; 523 } else { 524 void *pp_handle = adev->powerplay.pp_handle; 525 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 526 527 if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state) 528 return -ENOENT; 529 530 /* enter BACO state */ 531 if (pp_funcs->set_asic_baco_state(pp_handle, 1)) 532 return -EIO; 533 534 /* exit BACO state */ 535 if (pp_funcs->set_asic_baco_state(pp_handle, 0)) 536 return -EIO; 537 } 538 539 /* re-enable doorbell interrupt after BACO exit */ 540 if (ras && ras->supported) 541 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 542 543 return 0; 544 } 545 546 static int soc15_mode2_reset(struct amdgpu_device *adev) 547 { 548 if (is_support_sw_smu(adev)) 549 return smu_mode2_reset(&adev->smu); 550 if (!adev->powerplay.pp_funcs || 551 !adev->powerplay.pp_funcs->asic_reset_mode_2) 552 return -ENOENT; 553 554 return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle); 555 } 556 557 static enum amd_reset_method 558 soc15_asic_reset_method(struct amdgpu_device *adev) 559 { 560 bool baco_reset; 561 562 switch (adev->asic_type) { 563 case CHIP_RAVEN: 564 case CHIP_RENOIR: 565 return AMD_RESET_METHOD_MODE2; 566 case CHIP_VEGA10: 567 case CHIP_VEGA12: 568 case CHIP_ARCTURUS: 569 soc15_asic_get_baco_capability(adev, &baco_reset); 570 break; 571 case CHIP_VEGA20: 572 if (adev->psp.sos_fw_version >= 0x80067) 573 soc15_asic_get_baco_capability(adev, &baco_reset); 574 else 575 baco_reset = false; 576 if (baco_reset) { 577 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0); 578 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 579 580 if (hive || (ras && ras->supported)) 581 baco_reset = false; 582 } 583 break; 584 default: 585 baco_reset = false; 586 break; 587 } 588 589 if (baco_reset) 590 return AMD_RESET_METHOD_BACO; 591 else 592 return AMD_RESET_METHOD_MODE1; 593 } 594 595 static int soc15_asic_reset(struct amdgpu_device *adev) 596 { 597 switch (soc15_asic_reset_method(adev)) { 598 case AMD_RESET_METHOD_BACO: 599 if (!adev->in_suspend) 600 amdgpu_inc_vram_lost(adev); 601 return soc15_asic_baco_reset(adev); 602 case AMD_RESET_METHOD_MODE2: 603 return soc15_mode2_reset(adev); 604 default: 605 if (!adev->in_suspend) 606 amdgpu_inc_vram_lost(adev); 607 return soc15_asic_mode1_reset(adev); 608 } 609 } 610 611 static bool soc15_supports_baco(struct amdgpu_device *adev) 612 { 613 bool baco_support; 614 615 switch (adev->asic_type) { 616 case CHIP_VEGA10: 617 case CHIP_VEGA12: 618 soc15_asic_get_baco_capability(adev, &baco_support); 619 break; 620 case CHIP_VEGA20: 621 if (adev->psp.sos_fw_version >= 0x80067) 622 soc15_asic_get_baco_capability(adev, &baco_support); 623 else 624 baco_support = false; 625 break; 626 default: 627 return false; 628 } 629 630 return baco_support; 631 } 632 633 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 634 u32 cntl_reg, u32 status_reg) 635 { 636 return 0; 637 }*/ 638 639 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 640 { 641 /*int r; 642 643 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 644 if (r) 645 return r; 646 647 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 648 */ 649 return 0; 650 } 651 652 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 653 { 654 /* todo */ 655 656 return 0; 657 } 658 659 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 660 { 661 if (pci_is_root_bus(adev->pdev->bus)) 662 return; 663 664 if (amdgpu_pcie_gen2 == 0) 665 return; 666 667 if (adev->flags & AMD_IS_APU) 668 return; 669 670 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 671 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 672 return; 673 674 /* todo */ 675 } 676 677 static void soc15_program_aspm(struct amdgpu_device *adev) 678 { 679 680 if (amdgpu_aspm == 0) 681 return; 682 683 /* todo */ 684 } 685 686 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 687 bool enable) 688 { 689 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 690 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 691 } 692 693 static const struct amdgpu_ip_block_version vega10_common_ip_block = 694 { 695 .type = AMD_IP_BLOCK_TYPE_COMMON, 696 .major = 2, 697 .minor = 0, 698 .rev = 0, 699 .funcs = &soc15_common_ip_funcs, 700 }; 701 702 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 703 { 704 return adev->nbio.funcs->get_rev_id(adev); 705 } 706 707 int soc15_set_ip_blocks(struct amdgpu_device *adev) 708 { 709 /* Set IP register base before any HW register access */ 710 switch (adev->asic_type) { 711 case CHIP_VEGA10: 712 case CHIP_VEGA12: 713 case CHIP_RAVEN: 714 case CHIP_RENOIR: 715 vega10_reg_base_init(adev); 716 break; 717 case CHIP_VEGA20: 718 vega20_reg_base_init(adev); 719 break; 720 case CHIP_ARCTURUS: 721 arct_reg_base_init(adev); 722 break; 723 default: 724 return -EINVAL; 725 } 726 727 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 728 adev->gmc.xgmi.supported = true; 729 730 if (adev->flags & AMD_IS_APU) { 731 adev->nbio.funcs = &nbio_v7_0_funcs; 732 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 733 } else if (adev->asic_type == CHIP_VEGA20 || 734 adev->asic_type == CHIP_ARCTURUS) { 735 adev->nbio.funcs = &nbio_v7_4_funcs; 736 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 737 } else { 738 adev->nbio.funcs = &nbio_v6_1_funcs; 739 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 740 } 741 742 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 743 adev->df_funcs = &df_v3_6_funcs; 744 else 745 adev->df_funcs = &df_v1_7_funcs; 746 747 adev->rev_id = soc15_get_rev_id(adev); 748 adev->nbio.funcs->detect_hw_virt(adev); 749 750 if (amdgpu_sriov_vf(adev)) 751 adev->virt.ops = &xgpu_ai_virt_ops; 752 753 switch (adev->asic_type) { 754 case CHIP_VEGA10: 755 case CHIP_VEGA12: 756 case CHIP_VEGA20: 757 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 758 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 759 760 /* For Vega10 SR-IOV, PSP need to be initialized before IH */ 761 if (amdgpu_sriov_vf(adev)) { 762 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 763 if (adev->asic_type == CHIP_VEGA20) 764 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 765 else 766 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 767 } 768 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 769 } else { 770 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 771 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 772 if (adev->asic_type == CHIP_VEGA20) 773 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 774 else 775 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 776 } 777 } 778 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 779 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 780 if (!amdgpu_sriov_vf(adev)) { 781 if (is_support_sw_smu(adev)) 782 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 783 else 784 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 785 } 786 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 787 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 788 #if defined(CONFIG_DRM_AMD_DC) 789 else if (amdgpu_device_has_dc_support(adev)) 790 amdgpu_device_ip_block_add(adev, &dm_ip_block); 791 #endif 792 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { 793 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 794 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 795 } 796 break; 797 case CHIP_RAVEN: 798 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 799 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 800 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 801 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 802 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 803 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 804 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 805 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 806 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 807 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 808 #if defined(CONFIG_DRM_AMD_DC) 809 else if (amdgpu_device_has_dc_support(adev)) 810 amdgpu_device_ip_block_add(adev, &dm_ip_block); 811 #endif 812 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 813 break; 814 case CHIP_ARCTURUS: 815 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 816 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 817 818 if (amdgpu_sriov_vf(adev)) { 819 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 820 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 821 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 822 } else { 823 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 824 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 825 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 826 } 827 828 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 829 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 830 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 831 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 832 if (!amdgpu_sriov_vf(adev)) 833 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 834 835 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) 836 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 837 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 838 break; 839 case CHIP_RENOIR: 840 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 841 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 842 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 843 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 844 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 845 if (is_support_sw_smu(adev)) 846 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 847 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 848 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 849 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 850 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 851 #if defined(CONFIG_DRM_AMD_DC) 852 else if (amdgpu_device_has_dc_support(adev)) 853 amdgpu_device_ip_block_add(adev, &dm_ip_block); 854 #endif 855 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 856 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 857 break; 858 default: 859 return -EINVAL; 860 } 861 862 return 0; 863 } 864 865 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 866 { 867 adev->nbio.funcs->hdp_flush(adev, ring); 868 } 869 870 static void soc15_invalidate_hdp(struct amdgpu_device *adev, 871 struct amdgpu_ring *ring) 872 { 873 if (!ring || !ring->funcs->emit_wreg) 874 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 875 else 876 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 877 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 878 } 879 880 static bool soc15_need_full_reset(struct amdgpu_device *adev) 881 { 882 /* change this when we implement soft reset */ 883 return true; 884 } 885 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 886 uint64_t *count1) 887 { 888 uint32_t perfctr = 0; 889 uint64_t cnt0_of, cnt1_of; 890 int tmp; 891 892 /* This reports 0 on APUs, so return to avoid writing/reading registers 893 * that may or may not be different from their GPU counterparts 894 */ 895 if (adev->flags & AMD_IS_APU) 896 return; 897 898 /* Set the 2 events that we wish to watch, defined above */ 899 /* Reg 40 is # received msgs */ 900 /* Reg 104 is # of posted requests sent */ 901 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 902 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 903 904 /* Write to enable desired perf counters */ 905 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 906 /* Zero out and enable the perf counters 907 * Write 0x5: 908 * Bit 0 = Start all counters(1) 909 * Bit 2 = Global counter reset enable(1) 910 */ 911 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 912 913 msleep(1000); 914 915 /* Load the shadow and disable the perf counters 916 * Write 0x2: 917 * Bit 0 = Stop counters(0) 918 * Bit 1 = Load the shadow counters(1) 919 */ 920 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 921 922 /* Read register values to get any >32bit overflow */ 923 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 924 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 925 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 926 927 /* Get the values and add the overflow */ 928 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 929 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 930 } 931 932 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 933 uint64_t *count1) 934 { 935 uint32_t perfctr = 0; 936 uint64_t cnt0_of, cnt1_of; 937 int tmp; 938 939 /* This reports 0 on APUs, so return to avoid writing/reading registers 940 * that may or may not be different from their GPU counterparts 941 */ 942 if (adev->flags & AMD_IS_APU) 943 return; 944 945 /* Set the 2 events that we wish to watch, defined above */ 946 /* Reg 40 is # received msgs */ 947 /* Reg 108 is # of posted requests sent on VG20 */ 948 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 949 EVENT0_SEL, 40); 950 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 951 EVENT1_SEL, 108); 952 953 /* Write to enable desired perf counters */ 954 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 955 /* Zero out and enable the perf counters 956 * Write 0x5: 957 * Bit 0 = Start all counters(1) 958 * Bit 2 = Global counter reset enable(1) 959 */ 960 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 961 962 msleep(1000); 963 964 /* Load the shadow and disable the perf counters 965 * Write 0x2: 966 * Bit 0 = Stop counters(0) 967 * Bit 1 = Load the shadow counters(1) 968 */ 969 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 970 971 /* Read register values to get any >32bit overflow */ 972 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 973 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 974 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 975 976 /* Get the values and add the overflow */ 977 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 978 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 979 } 980 981 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 982 { 983 u32 sol_reg; 984 985 /* Just return false for soc15 GPUs. Reset does not seem to 986 * be necessary. 987 */ 988 if (!amdgpu_passthrough(adev)) 989 return false; 990 991 if (adev->flags & AMD_IS_APU) 992 return false; 993 994 /* Check sOS sign of life register to confirm sys driver and sOS 995 * are already been loaded. 996 */ 997 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 998 if (sol_reg) 999 return true; 1000 1001 return false; 1002 } 1003 1004 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 1005 { 1006 uint64_t nak_r, nak_g; 1007 1008 /* Get the number of NAKs received and generated */ 1009 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 1010 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 1011 1012 /* Add the total number of NAKs, i.e the number of replays */ 1013 return (nak_r + nak_g); 1014 } 1015 1016 static const struct amdgpu_asic_funcs soc15_asic_funcs = 1017 { 1018 .read_disabled_bios = &soc15_read_disabled_bios, 1019 .read_bios_from_rom = &soc15_read_bios_from_rom, 1020 .read_register = &soc15_read_register, 1021 .reset = &soc15_asic_reset, 1022 .reset_method = &soc15_asic_reset_method, 1023 .set_vga_state = &soc15_vga_set_state, 1024 .get_xclk = &soc15_get_xclk, 1025 .set_uvd_clocks = &soc15_set_uvd_clocks, 1026 .set_vce_clocks = &soc15_set_vce_clocks, 1027 .get_config_memsize = &soc15_get_config_memsize, 1028 .flush_hdp = &soc15_flush_hdp, 1029 .invalidate_hdp = &soc15_invalidate_hdp, 1030 .need_full_reset = &soc15_need_full_reset, 1031 .init_doorbell_index = &vega10_doorbell_index_init, 1032 .get_pcie_usage = &soc15_get_pcie_usage, 1033 .need_reset_on_init = &soc15_need_reset_on_init, 1034 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1035 .supports_baco = &soc15_supports_baco, 1036 }; 1037 1038 static const struct amdgpu_asic_funcs vega20_asic_funcs = 1039 { 1040 .read_disabled_bios = &soc15_read_disabled_bios, 1041 .read_bios_from_rom = &soc15_read_bios_from_rom, 1042 .read_register = &soc15_read_register, 1043 .reset = &soc15_asic_reset, 1044 .reset_method = &soc15_asic_reset_method, 1045 .set_vga_state = &soc15_vga_set_state, 1046 .get_xclk = &soc15_get_xclk, 1047 .set_uvd_clocks = &soc15_set_uvd_clocks, 1048 .set_vce_clocks = &soc15_set_vce_clocks, 1049 .get_config_memsize = &soc15_get_config_memsize, 1050 .flush_hdp = &soc15_flush_hdp, 1051 .invalidate_hdp = &soc15_invalidate_hdp, 1052 .need_full_reset = &soc15_need_full_reset, 1053 .init_doorbell_index = &vega20_doorbell_index_init, 1054 .get_pcie_usage = &vega20_get_pcie_usage, 1055 .need_reset_on_init = &soc15_need_reset_on_init, 1056 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1057 .supports_baco = &soc15_supports_baco, 1058 }; 1059 1060 static int soc15_common_early_init(void *handle) 1061 { 1062 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1064 1065 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 1066 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 1067 adev->smc_rreg = NULL; 1068 adev->smc_wreg = NULL; 1069 adev->pcie_rreg = &soc15_pcie_rreg; 1070 adev->pcie_wreg = &soc15_pcie_wreg; 1071 adev->pcie_rreg64 = &soc15_pcie_rreg64; 1072 adev->pcie_wreg64 = &soc15_pcie_wreg64; 1073 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 1074 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 1075 adev->didt_rreg = &soc15_didt_rreg; 1076 adev->didt_wreg = &soc15_didt_wreg; 1077 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 1078 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 1079 adev->se_cac_rreg = &soc15_se_cac_rreg; 1080 adev->se_cac_wreg = &soc15_se_cac_wreg; 1081 1082 1083 adev->external_rev_id = 0xFF; 1084 switch (adev->asic_type) { 1085 case CHIP_VEGA10: 1086 adev->asic_funcs = &soc15_asic_funcs; 1087 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1088 AMD_CG_SUPPORT_GFX_MGLS | 1089 AMD_CG_SUPPORT_GFX_RLC_LS | 1090 AMD_CG_SUPPORT_GFX_CP_LS | 1091 AMD_CG_SUPPORT_GFX_3D_CGCG | 1092 AMD_CG_SUPPORT_GFX_3D_CGLS | 1093 AMD_CG_SUPPORT_GFX_CGCG | 1094 AMD_CG_SUPPORT_GFX_CGLS | 1095 AMD_CG_SUPPORT_BIF_MGCG | 1096 AMD_CG_SUPPORT_BIF_LS | 1097 AMD_CG_SUPPORT_HDP_LS | 1098 AMD_CG_SUPPORT_DRM_MGCG | 1099 AMD_CG_SUPPORT_DRM_LS | 1100 AMD_CG_SUPPORT_ROM_MGCG | 1101 AMD_CG_SUPPORT_DF_MGCG | 1102 AMD_CG_SUPPORT_SDMA_MGCG | 1103 AMD_CG_SUPPORT_SDMA_LS | 1104 AMD_CG_SUPPORT_MC_MGCG | 1105 AMD_CG_SUPPORT_MC_LS; 1106 adev->pg_flags = 0; 1107 adev->external_rev_id = 0x1; 1108 break; 1109 case CHIP_VEGA12: 1110 adev->asic_funcs = &soc15_asic_funcs; 1111 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1112 AMD_CG_SUPPORT_GFX_MGLS | 1113 AMD_CG_SUPPORT_GFX_CGCG | 1114 AMD_CG_SUPPORT_GFX_CGLS | 1115 AMD_CG_SUPPORT_GFX_3D_CGCG | 1116 AMD_CG_SUPPORT_GFX_3D_CGLS | 1117 AMD_CG_SUPPORT_GFX_CP_LS | 1118 AMD_CG_SUPPORT_MC_LS | 1119 AMD_CG_SUPPORT_MC_MGCG | 1120 AMD_CG_SUPPORT_SDMA_MGCG | 1121 AMD_CG_SUPPORT_SDMA_LS | 1122 AMD_CG_SUPPORT_BIF_MGCG | 1123 AMD_CG_SUPPORT_BIF_LS | 1124 AMD_CG_SUPPORT_HDP_MGCG | 1125 AMD_CG_SUPPORT_HDP_LS | 1126 AMD_CG_SUPPORT_ROM_MGCG | 1127 AMD_CG_SUPPORT_VCE_MGCG | 1128 AMD_CG_SUPPORT_UVD_MGCG; 1129 adev->pg_flags = 0; 1130 adev->external_rev_id = adev->rev_id + 0x14; 1131 break; 1132 case CHIP_VEGA20: 1133 adev->asic_funcs = &vega20_asic_funcs; 1134 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1135 AMD_CG_SUPPORT_GFX_MGLS | 1136 AMD_CG_SUPPORT_GFX_CGCG | 1137 AMD_CG_SUPPORT_GFX_CGLS | 1138 AMD_CG_SUPPORT_GFX_3D_CGCG | 1139 AMD_CG_SUPPORT_GFX_3D_CGLS | 1140 AMD_CG_SUPPORT_GFX_CP_LS | 1141 AMD_CG_SUPPORT_MC_LS | 1142 AMD_CG_SUPPORT_MC_MGCG | 1143 AMD_CG_SUPPORT_SDMA_MGCG | 1144 AMD_CG_SUPPORT_SDMA_LS | 1145 AMD_CG_SUPPORT_BIF_MGCG | 1146 AMD_CG_SUPPORT_BIF_LS | 1147 AMD_CG_SUPPORT_HDP_MGCG | 1148 AMD_CG_SUPPORT_HDP_LS | 1149 AMD_CG_SUPPORT_ROM_MGCG | 1150 AMD_CG_SUPPORT_VCE_MGCG | 1151 AMD_CG_SUPPORT_UVD_MGCG; 1152 adev->pg_flags = 0; 1153 adev->external_rev_id = adev->rev_id + 0x28; 1154 break; 1155 case CHIP_RAVEN: 1156 adev->asic_funcs = &soc15_asic_funcs; 1157 if (adev->rev_id >= 0x8) 1158 adev->external_rev_id = adev->rev_id + 0x79; 1159 else if (adev->pdev->device == 0x15d8) 1160 adev->external_rev_id = adev->rev_id + 0x41; 1161 else if (adev->rev_id == 1) 1162 adev->external_rev_id = adev->rev_id + 0x20; 1163 else 1164 adev->external_rev_id = adev->rev_id + 0x01; 1165 1166 if (adev->rev_id >= 0x8) { 1167 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1168 AMD_CG_SUPPORT_GFX_MGLS | 1169 AMD_CG_SUPPORT_GFX_CP_LS | 1170 AMD_CG_SUPPORT_GFX_3D_CGCG | 1171 AMD_CG_SUPPORT_GFX_3D_CGLS | 1172 AMD_CG_SUPPORT_GFX_CGCG | 1173 AMD_CG_SUPPORT_GFX_CGLS | 1174 AMD_CG_SUPPORT_BIF_LS | 1175 AMD_CG_SUPPORT_HDP_LS | 1176 AMD_CG_SUPPORT_ROM_MGCG | 1177 AMD_CG_SUPPORT_MC_MGCG | 1178 AMD_CG_SUPPORT_MC_LS | 1179 AMD_CG_SUPPORT_SDMA_MGCG | 1180 AMD_CG_SUPPORT_SDMA_LS | 1181 AMD_CG_SUPPORT_VCN_MGCG; 1182 1183 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1184 AMD_PG_SUPPORT_VCN | 1185 AMD_PG_SUPPORT_VCN_DPG; 1186 } else if (adev->pdev->device == 0x15d8) { 1187 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1188 AMD_CG_SUPPORT_GFX_MGLS | 1189 AMD_CG_SUPPORT_GFX_CP_LS | 1190 AMD_CG_SUPPORT_GFX_3D_CGCG | 1191 AMD_CG_SUPPORT_GFX_3D_CGLS | 1192 AMD_CG_SUPPORT_GFX_CGCG | 1193 AMD_CG_SUPPORT_GFX_CGLS | 1194 AMD_CG_SUPPORT_BIF_LS | 1195 AMD_CG_SUPPORT_HDP_LS | 1196 AMD_CG_SUPPORT_ROM_MGCG | 1197 AMD_CG_SUPPORT_MC_MGCG | 1198 AMD_CG_SUPPORT_MC_LS | 1199 AMD_CG_SUPPORT_SDMA_MGCG | 1200 AMD_CG_SUPPORT_SDMA_LS; 1201 1202 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1203 AMD_PG_SUPPORT_MMHUB | 1204 AMD_PG_SUPPORT_VCN | 1205 AMD_PG_SUPPORT_VCN_DPG; 1206 } else { 1207 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1208 AMD_CG_SUPPORT_GFX_MGLS | 1209 AMD_CG_SUPPORT_GFX_RLC_LS | 1210 AMD_CG_SUPPORT_GFX_CP_LS | 1211 AMD_CG_SUPPORT_GFX_3D_CGCG | 1212 AMD_CG_SUPPORT_GFX_3D_CGLS | 1213 AMD_CG_SUPPORT_GFX_CGCG | 1214 AMD_CG_SUPPORT_GFX_CGLS | 1215 AMD_CG_SUPPORT_BIF_MGCG | 1216 AMD_CG_SUPPORT_BIF_LS | 1217 AMD_CG_SUPPORT_HDP_MGCG | 1218 AMD_CG_SUPPORT_HDP_LS | 1219 AMD_CG_SUPPORT_DRM_MGCG | 1220 AMD_CG_SUPPORT_DRM_LS | 1221 AMD_CG_SUPPORT_ROM_MGCG | 1222 AMD_CG_SUPPORT_MC_MGCG | 1223 AMD_CG_SUPPORT_MC_LS | 1224 AMD_CG_SUPPORT_SDMA_MGCG | 1225 AMD_CG_SUPPORT_SDMA_LS | 1226 AMD_CG_SUPPORT_VCN_MGCG; 1227 1228 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1229 AMD_PG_SUPPORT_VCN | 1230 AMD_PG_SUPPORT_VCN_DPG; 1231 } 1232 break; 1233 case CHIP_ARCTURUS: 1234 adev->asic_funcs = &vega20_asic_funcs; 1235 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1236 AMD_CG_SUPPORT_GFX_MGLS | 1237 AMD_CG_SUPPORT_GFX_CGCG | 1238 AMD_CG_SUPPORT_GFX_CGLS | 1239 AMD_CG_SUPPORT_GFX_CP_LS | 1240 AMD_CG_SUPPORT_HDP_MGCG | 1241 AMD_CG_SUPPORT_HDP_LS | 1242 AMD_CG_SUPPORT_SDMA_MGCG | 1243 AMD_CG_SUPPORT_SDMA_LS | 1244 AMD_CG_SUPPORT_MC_MGCG | 1245 AMD_CG_SUPPORT_MC_LS | 1246 AMD_CG_SUPPORT_IH_CG | 1247 AMD_CG_SUPPORT_VCN_MGCG | 1248 AMD_CG_SUPPORT_JPEG_MGCG; 1249 adev->pg_flags = 0; 1250 adev->external_rev_id = adev->rev_id + 0x32; 1251 break; 1252 case CHIP_RENOIR: 1253 adev->asic_funcs = &soc15_asic_funcs; 1254 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1255 AMD_CG_SUPPORT_GFX_MGLS | 1256 AMD_CG_SUPPORT_GFX_3D_CGCG | 1257 AMD_CG_SUPPORT_GFX_3D_CGLS | 1258 AMD_CG_SUPPORT_GFX_CGCG | 1259 AMD_CG_SUPPORT_GFX_CGLS | 1260 AMD_CG_SUPPORT_GFX_CP_LS | 1261 AMD_CG_SUPPORT_MC_MGCG | 1262 AMD_CG_SUPPORT_MC_LS | 1263 AMD_CG_SUPPORT_SDMA_MGCG | 1264 AMD_CG_SUPPORT_SDMA_LS | 1265 AMD_CG_SUPPORT_BIF_LS | 1266 AMD_CG_SUPPORT_HDP_LS | 1267 AMD_CG_SUPPORT_ROM_MGCG | 1268 AMD_CG_SUPPORT_VCN_MGCG | 1269 AMD_CG_SUPPORT_JPEG_MGCG | 1270 AMD_CG_SUPPORT_IH_CG | 1271 AMD_CG_SUPPORT_ATHUB_LS | 1272 AMD_CG_SUPPORT_ATHUB_MGCG | 1273 AMD_CG_SUPPORT_DF_MGCG; 1274 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1275 AMD_PG_SUPPORT_VCN | 1276 AMD_PG_SUPPORT_JPEG | 1277 AMD_PG_SUPPORT_VCN_DPG; 1278 adev->external_rev_id = adev->rev_id + 0x91; 1279 break; 1280 default: 1281 /* FIXME: not supported yet */ 1282 return -EINVAL; 1283 } 1284 1285 if (amdgpu_sriov_vf(adev)) { 1286 amdgpu_virt_init_setting(adev); 1287 xgpu_ai_mailbox_set_irq_funcs(adev); 1288 } 1289 1290 return 0; 1291 } 1292 1293 static int soc15_common_late_init(void *handle) 1294 { 1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1296 int r = 0; 1297 1298 if (amdgpu_sriov_vf(adev)) 1299 xgpu_ai_mailbox_get_irq(adev); 1300 1301 if (adev->nbio.funcs->ras_late_init) 1302 r = adev->nbio.funcs->ras_late_init(adev); 1303 1304 return r; 1305 } 1306 1307 static int soc15_common_sw_init(void *handle) 1308 { 1309 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1310 1311 if (amdgpu_sriov_vf(adev)) 1312 xgpu_ai_mailbox_add_irq_id(adev); 1313 1314 adev->df_funcs->sw_init(adev); 1315 1316 return 0; 1317 } 1318 1319 static int soc15_common_sw_fini(void *handle) 1320 { 1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1322 1323 amdgpu_nbio_ras_fini(adev); 1324 adev->df_funcs->sw_fini(adev); 1325 return 0; 1326 } 1327 1328 static void soc15_doorbell_range_init(struct amdgpu_device *adev) 1329 { 1330 int i; 1331 struct amdgpu_ring *ring; 1332 1333 /* sdma/ih doorbell range are programed by hypervisor */ 1334 if (!amdgpu_sriov_vf(adev)) { 1335 for (i = 0; i < adev->sdma.num_instances; i++) { 1336 ring = &adev->sdma.instance[i].ring; 1337 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1338 ring->use_doorbell, ring->doorbell_index, 1339 adev->doorbell_index.sdma_doorbell_range); 1340 } 1341 1342 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 1343 adev->irq.ih.doorbell_index); 1344 } 1345 } 1346 1347 static int soc15_common_hw_init(void *handle) 1348 { 1349 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1350 1351 /* enable pcie gen2/3 link */ 1352 soc15_pcie_gen3_enable(adev); 1353 /* enable aspm */ 1354 soc15_program_aspm(adev); 1355 /* setup nbio registers */ 1356 adev->nbio.funcs->init_registers(adev); 1357 /* remap HDP registers to a hole in mmio space, 1358 * for the purpose of expose those registers 1359 * to process space 1360 */ 1361 if (adev->nbio.funcs->remap_hdp_registers) 1362 adev->nbio.funcs->remap_hdp_registers(adev); 1363 1364 /* enable the doorbell aperture */ 1365 soc15_enable_doorbell_aperture(adev, true); 1366 /* HW doorbell routing policy: doorbell writing not 1367 * in SDMA/IH/MM/ACV range will be routed to CP. So 1368 * we need to init SDMA/IH/MM/ACV doorbell range prior 1369 * to CP ip block init and ring test. 1370 */ 1371 soc15_doorbell_range_init(adev); 1372 1373 return 0; 1374 } 1375 1376 static int soc15_common_hw_fini(void *handle) 1377 { 1378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1379 1380 /* disable the doorbell aperture */ 1381 soc15_enable_doorbell_aperture(adev, false); 1382 if (amdgpu_sriov_vf(adev)) 1383 xgpu_ai_mailbox_put_irq(adev); 1384 1385 if (adev->nbio.ras_if && 1386 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1387 if (adev->nbio.funcs->init_ras_controller_interrupt) 1388 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1389 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) 1390 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1391 } 1392 1393 return 0; 1394 } 1395 1396 static int soc15_common_suspend(void *handle) 1397 { 1398 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1399 1400 return soc15_common_hw_fini(adev); 1401 } 1402 1403 static int soc15_common_resume(void *handle) 1404 { 1405 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1406 1407 return soc15_common_hw_init(adev); 1408 } 1409 1410 static bool soc15_common_is_idle(void *handle) 1411 { 1412 return true; 1413 } 1414 1415 static int soc15_common_wait_for_idle(void *handle) 1416 { 1417 return 0; 1418 } 1419 1420 static int soc15_common_soft_reset(void *handle) 1421 { 1422 return 0; 1423 } 1424 1425 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) 1426 { 1427 uint32_t def, data; 1428 1429 if (adev->asic_type == CHIP_VEGA20 || 1430 adev->asic_type == CHIP_ARCTURUS) { 1431 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); 1432 1433 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1434 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1435 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1436 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1437 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; 1438 else 1439 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1440 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1441 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1442 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); 1443 1444 if (def != data) 1445 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); 1446 } else { 1447 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1448 1449 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1450 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1451 else 1452 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1453 1454 if (def != data) 1455 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 1456 } 1457 } 1458 1459 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1460 { 1461 uint32_t def, data; 1462 1463 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1464 1465 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1466 data &= ~(0x01000000 | 1467 0x02000000 | 1468 0x04000000 | 1469 0x08000000 | 1470 0x10000000 | 1471 0x20000000 | 1472 0x40000000 | 1473 0x80000000); 1474 else 1475 data |= (0x01000000 | 1476 0x02000000 | 1477 0x04000000 | 1478 0x08000000 | 1479 0x10000000 | 1480 0x20000000 | 1481 0x40000000 | 1482 0x80000000); 1483 1484 if (def != data) 1485 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1486 } 1487 1488 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1489 { 1490 uint32_t def, data; 1491 1492 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1493 1494 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1495 data |= 1; 1496 else 1497 data &= ~1; 1498 1499 if (def != data) 1500 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1501 } 1502 1503 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1504 bool enable) 1505 { 1506 uint32_t def, data; 1507 1508 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1509 1510 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1511 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1512 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1513 else 1514 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1515 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1516 1517 if (def != data) 1518 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); 1519 } 1520 1521 static int soc15_common_set_clockgating_state(void *handle, 1522 enum amd_clockgating_state state) 1523 { 1524 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1525 1526 if (amdgpu_sriov_vf(adev)) 1527 return 0; 1528 1529 switch (adev->asic_type) { 1530 case CHIP_VEGA10: 1531 case CHIP_VEGA12: 1532 case CHIP_VEGA20: 1533 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1534 state == AMD_CG_STATE_GATE ? true : false); 1535 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1536 state == AMD_CG_STATE_GATE ? true : false); 1537 soc15_update_hdp_light_sleep(adev, 1538 state == AMD_CG_STATE_GATE ? true : false); 1539 soc15_update_drm_clock_gating(adev, 1540 state == AMD_CG_STATE_GATE ? true : false); 1541 soc15_update_drm_light_sleep(adev, 1542 state == AMD_CG_STATE_GATE ? true : false); 1543 soc15_update_rom_medium_grain_clock_gating(adev, 1544 state == AMD_CG_STATE_GATE ? true : false); 1545 adev->df_funcs->update_medium_grain_clock_gating(adev, 1546 state == AMD_CG_STATE_GATE ? true : false); 1547 break; 1548 case CHIP_RAVEN: 1549 case CHIP_RENOIR: 1550 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1551 state == AMD_CG_STATE_GATE ? true : false); 1552 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1553 state == AMD_CG_STATE_GATE ? true : false); 1554 soc15_update_hdp_light_sleep(adev, 1555 state == AMD_CG_STATE_GATE ? true : false); 1556 soc15_update_drm_clock_gating(adev, 1557 state == AMD_CG_STATE_GATE ? true : false); 1558 soc15_update_drm_light_sleep(adev, 1559 state == AMD_CG_STATE_GATE ? true : false); 1560 soc15_update_rom_medium_grain_clock_gating(adev, 1561 state == AMD_CG_STATE_GATE ? true : false); 1562 break; 1563 case CHIP_ARCTURUS: 1564 soc15_update_hdp_light_sleep(adev, 1565 state == AMD_CG_STATE_GATE ? true : false); 1566 break; 1567 default: 1568 break; 1569 } 1570 return 0; 1571 } 1572 1573 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1574 { 1575 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1576 int data; 1577 1578 if (amdgpu_sriov_vf(adev)) 1579 *flags = 0; 1580 1581 adev->nbio.funcs->get_clockgating_state(adev, flags); 1582 1583 /* AMD_CG_SUPPORT_HDP_LS */ 1584 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1585 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 1586 *flags |= AMD_CG_SUPPORT_HDP_LS; 1587 1588 /* AMD_CG_SUPPORT_DRM_MGCG */ 1589 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1590 if (!(data & 0x01000000)) 1591 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1592 1593 /* AMD_CG_SUPPORT_DRM_LS */ 1594 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1595 if (data & 0x1) 1596 *flags |= AMD_CG_SUPPORT_DRM_LS; 1597 1598 /* AMD_CG_SUPPORT_ROM_MGCG */ 1599 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1600 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 1601 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 1602 1603 adev->df_funcs->get_clockgating_state(adev, flags); 1604 } 1605 1606 static int soc15_common_set_powergating_state(void *handle, 1607 enum amd_powergating_state state) 1608 { 1609 /* todo */ 1610 return 0; 1611 } 1612 1613 const struct amd_ip_funcs soc15_common_ip_funcs = { 1614 .name = "soc15_common", 1615 .early_init = soc15_common_early_init, 1616 .late_init = soc15_common_late_init, 1617 .sw_init = soc15_common_sw_init, 1618 .sw_fini = soc15_common_sw_fini, 1619 .hw_init = soc15_common_hw_init, 1620 .hw_fini = soc15_common_hw_fini, 1621 .suspend = soc15_common_suspend, 1622 .resume = soc15_common_resume, 1623 .is_idle = soc15_common_is_idle, 1624 .wait_for_idle = soc15_common_wait_for_idle, 1625 .soft_reset = soc15_common_soft_reset, 1626 .set_clockgating_state = soc15_common_set_clockgating_state, 1627 .set_powergating_state = soc15_common_set_powergating_state, 1628 .get_clockgating_state= soc15_common_get_clockgating_state, 1629 }; 1630