1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "uvd/uvd_7_0_offset.h" 41 #include "gc/gc_9_0_offset.h" 42 #include "gc/gc_9_0_sh_mask.h" 43 #include "sdma0/sdma0_4_0_offset.h" 44 #include "sdma1/sdma1_4_0_offset.h" 45 #include "nbio/nbio_7_0_default.h" 46 #include "nbio/nbio_7_0_offset.h" 47 #include "nbio/nbio_7_0_sh_mask.h" 48 #include "nbio/nbio_7_0_smn.h" 49 #include "mp/mp_9_0_offset.h" 50 51 #include "soc15.h" 52 #include "soc15_common.h" 53 #include "gfx_v9_0.h" 54 #include "gmc_v9_0.h" 55 #include "gfxhub_v1_0.h" 56 #include "mmhub_v1_0.h" 57 #include "df_v1_7.h" 58 #include "df_v3_6.h" 59 #include "nbio_v6_1.h" 60 #include "nbio_v7_0.h" 61 #include "nbio_v7_4.h" 62 #include "hdp_v4_0.h" 63 #include "vega10_ih.h" 64 #include "vega20_ih.h" 65 #include "navi10_ih.h" 66 #include "sdma_v4_0.h" 67 #include "uvd_v7_0.h" 68 #include "vce_v4_0.h" 69 #include "vcn_v1_0.h" 70 #include "vcn_v2_0.h" 71 #include "jpeg_v2_0.h" 72 #include "vcn_v2_5.h" 73 #include "jpeg_v2_5.h" 74 #include "smuio_v9_0.h" 75 #include "smuio_v11_0.h" 76 #include "smuio_v13_0.h" 77 #include "amdgpu_vkms.h" 78 #include "mxgpu_ai.h" 79 #include "amdgpu_ras.h" 80 #include "amdgpu_xgmi.h" 81 #include <uapi/linux/kfd_ioctl.h> 82 83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 87 88 static const struct amd_ip_funcs soc15_common_ip_funcs; 89 90 /* Vega, Raven, Arcturus */ 91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = 92 { 93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 94 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 95 }; 96 97 static const struct amdgpu_video_codecs vega_video_codecs_encode = 98 { 99 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), 100 .codec_array = vega_video_codecs_encode_array, 101 }; 102 103 /* Vega */ 104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = 105 { 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 112 }; 113 114 static const struct amdgpu_video_codecs vega_video_codecs_decode = 115 { 116 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), 117 .codec_array = vega_video_codecs_decode_array, 118 }; 119 120 /* Raven */ 121 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = 122 { 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)}, 130 }; 131 132 static const struct amdgpu_video_codecs rv_video_codecs_decode = 133 { 134 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), 135 .codec_array = rv_video_codecs_decode_array, 136 }; 137 138 /* Renoir, Arcturus */ 139 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = 140 { 141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 148 }; 149 150 static const struct amdgpu_video_codecs rn_video_codecs_decode = 151 { 152 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), 153 .codec_array = rn_video_codecs_decode_array, 154 }; 155 156 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, 157 const struct amdgpu_video_codecs **codecs) 158 { 159 if (adev->ip_versions[VCE_HWIP][0]) { 160 switch (adev->ip_versions[VCE_HWIP][0]) { 161 case IP_VERSION(4, 0, 0): 162 case IP_VERSION(4, 1, 0): 163 if (encode) 164 *codecs = &vega_video_codecs_encode; 165 else 166 *codecs = &vega_video_codecs_decode; 167 return 0; 168 default: 169 return -EINVAL; 170 } 171 } else { 172 switch (adev->ip_versions[UVD_HWIP][0]) { 173 case IP_VERSION(1, 0, 0): 174 case IP_VERSION(1, 0, 1): 175 if (encode) 176 *codecs = &vega_video_codecs_encode; 177 else 178 *codecs = &rv_video_codecs_decode; 179 return 0; 180 case IP_VERSION(2, 5, 0): 181 case IP_VERSION(2, 6, 0): 182 case IP_VERSION(2, 2, 0): 183 if (encode) 184 *codecs = &vega_video_codecs_encode; 185 else 186 *codecs = &rn_video_codecs_decode; 187 return 0; 188 default: 189 return -EINVAL; 190 } 191 } 192 } 193 194 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 195 { 196 unsigned long flags, address, data; 197 u32 r; 198 199 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 200 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 201 202 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 203 WREG32(address, ((reg) & 0x1ff)); 204 r = RREG32(data); 205 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 206 return r; 207 } 208 209 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 210 { 211 unsigned long flags, address, data; 212 213 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 214 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 215 216 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 217 WREG32(address, ((reg) & 0x1ff)); 218 WREG32(data, (v)); 219 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 220 } 221 222 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 223 { 224 unsigned long flags, address, data; 225 u32 r; 226 227 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 228 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 229 230 spin_lock_irqsave(&adev->didt_idx_lock, flags); 231 WREG32(address, (reg)); 232 r = RREG32(data); 233 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 234 return r; 235 } 236 237 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 238 { 239 unsigned long flags, address, data; 240 241 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 242 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 243 244 spin_lock_irqsave(&adev->didt_idx_lock, flags); 245 WREG32(address, (reg)); 246 WREG32(data, (v)); 247 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 248 } 249 250 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 251 { 252 unsigned long flags; 253 u32 r; 254 255 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 256 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 257 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 258 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 259 return r; 260 } 261 262 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 263 { 264 unsigned long flags; 265 266 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 267 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 268 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 269 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 270 } 271 272 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 273 { 274 unsigned long flags; 275 u32 r; 276 277 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 278 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 279 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 280 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 281 return r; 282 } 283 284 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 285 { 286 unsigned long flags; 287 288 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 289 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 290 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 291 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 292 } 293 294 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 295 { 296 return adev->nbio.funcs->get_memsize(adev); 297 } 298 299 static u32 soc15_get_xclk(struct amdgpu_device *adev) 300 { 301 u32 reference_clock = adev->clock.spll.reference_freq; 302 303 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) || 304 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1)) 305 return 10000; 306 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) || 307 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1)) 308 return reference_clock / 4; 309 310 return reference_clock; 311 } 312 313 314 void soc15_grbm_select(struct amdgpu_device *adev, 315 u32 me, u32 pipe, u32 queue, u32 vmid) 316 { 317 u32 grbm_gfx_cntl = 0; 318 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 319 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 320 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 321 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 322 323 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 324 } 325 326 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 327 { 328 /* todo */ 329 } 330 331 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 332 { 333 /* todo */ 334 return false; 335 } 336 337 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 340 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 341 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 342 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 343 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 344 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 345 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 346 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 347 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 348 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 349 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 352 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 353 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 354 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 355 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 356 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 357 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 358 }; 359 360 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 361 u32 sh_num, u32 reg_offset) 362 { 363 uint32_t val; 364 365 mutex_lock(&adev->grbm_idx_mutex); 366 if (se_num != 0xffffffff || sh_num != 0xffffffff) 367 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 368 369 val = RREG32(reg_offset); 370 371 if (se_num != 0xffffffff || sh_num != 0xffffffff) 372 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 373 mutex_unlock(&adev->grbm_idx_mutex); 374 return val; 375 } 376 377 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 378 bool indexed, u32 se_num, 379 u32 sh_num, u32 reg_offset) 380 { 381 if (indexed) { 382 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 383 } else { 384 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 385 return adev->gfx.config.gb_addr_config; 386 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 387 return adev->gfx.config.db_debug2; 388 return RREG32(reg_offset); 389 } 390 } 391 392 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 393 u32 sh_num, u32 reg_offset, u32 *value) 394 { 395 uint32_t i; 396 struct soc15_allowed_register_entry *en; 397 398 *value = 0; 399 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 400 en = &soc15_allowed_read_registers[i]; 401 if (!adev->reg_offset[en->hwip][en->inst]) 402 continue; 403 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 404 + en->reg_offset)) 405 continue; 406 407 *value = soc15_get_register_value(adev, 408 soc15_allowed_read_registers[i].grbm_indexed, 409 se_num, sh_num, reg_offset); 410 return 0; 411 } 412 return -EINVAL; 413 } 414 415 416 /** 417 * soc15_program_register_sequence - program an array of registers. 418 * 419 * @adev: amdgpu_device pointer 420 * @regs: pointer to the register array 421 * @array_size: size of the register array 422 * 423 * Programs an array or registers with and and or masks. 424 * This is a helper for setting golden registers. 425 */ 426 427 void soc15_program_register_sequence(struct amdgpu_device *adev, 428 const struct soc15_reg_golden *regs, 429 const u32 array_size) 430 { 431 const struct soc15_reg_golden *entry; 432 u32 tmp, reg; 433 int i; 434 435 for (i = 0; i < array_size; ++i) { 436 entry = ®s[i]; 437 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 438 439 if (entry->and_mask == 0xffffffff) { 440 tmp = entry->or_mask; 441 } else { 442 tmp = (entry->hwip == GC_HWIP) ? 443 RREG32_SOC15_IP(GC, reg) : RREG32(reg); 444 445 tmp &= ~(entry->and_mask); 446 tmp |= (entry->or_mask & entry->and_mask); 447 } 448 449 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 450 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 451 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 452 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 453 WREG32_RLC(reg, tmp); 454 else 455 (entry->hwip == GC_HWIP) ? 456 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); 457 458 } 459 460 } 461 462 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 463 { 464 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 465 int ret = 0; 466 467 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 468 if (ras && adev->ras_enabled) 469 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 470 471 ret = amdgpu_dpm_baco_reset(adev); 472 if (ret) 473 return ret; 474 475 /* re-enable doorbell interrupt after BACO exit */ 476 if (ras && adev->ras_enabled) 477 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 478 479 return 0; 480 } 481 482 static enum amd_reset_method 483 soc15_asic_reset_method(struct amdgpu_device *adev) 484 { 485 bool baco_reset = false; 486 bool connected_to_cpu = false; 487 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 488 489 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) 490 connected_to_cpu = true; 491 492 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 493 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 494 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 495 amdgpu_reset_method == AMD_RESET_METHOD_PCI) { 496 /* If connected to cpu, driver only support mode2 */ 497 if (connected_to_cpu) 498 return AMD_RESET_METHOD_MODE2; 499 return amdgpu_reset_method; 500 } 501 502 if (amdgpu_reset_method != -1) 503 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 504 amdgpu_reset_method); 505 506 switch (adev->ip_versions[MP1_HWIP][0]) { 507 case IP_VERSION(10, 0, 0): 508 case IP_VERSION(10, 0, 1): 509 case IP_VERSION(12, 0, 0): 510 case IP_VERSION(12, 0, 1): 511 return AMD_RESET_METHOD_MODE2; 512 case IP_VERSION(9, 0, 0): 513 case IP_VERSION(11, 0, 2): 514 if (adev->asic_type == CHIP_VEGA20) { 515 if (adev->psp.sos.fw_version >= 0x80067) 516 baco_reset = amdgpu_dpm_is_baco_supported(adev); 517 /* 518 * 1. PMFW version > 0x284300: all cases use baco 519 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 520 */ 521 if (ras && adev->ras_enabled && 522 adev->pm.fw_version <= 0x283400) 523 baco_reset = false; 524 } else { 525 baco_reset = amdgpu_dpm_is_baco_supported(adev); 526 } 527 break; 528 case IP_VERSION(13, 0, 2): 529 /* 530 * 1.connected to cpu: driver issue mode2 reset 531 * 2.discret gpu: driver issue mode1 reset 532 */ 533 if (connected_to_cpu) 534 return AMD_RESET_METHOD_MODE2; 535 break; 536 default: 537 break; 538 } 539 540 if (baco_reset) 541 return AMD_RESET_METHOD_BACO; 542 else 543 return AMD_RESET_METHOD_MODE1; 544 } 545 546 static int soc15_asic_reset(struct amdgpu_device *adev) 547 { 548 /* original raven doesn't have full asic reset */ 549 if ((adev->apu_flags & AMD_APU_IS_RAVEN) || 550 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 551 return 0; 552 553 switch (soc15_asic_reset_method(adev)) { 554 case AMD_RESET_METHOD_PCI: 555 dev_info(adev->dev, "PCI reset\n"); 556 return amdgpu_device_pci_reset(adev); 557 case AMD_RESET_METHOD_BACO: 558 dev_info(adev->dev, "BACO reset\n"); 559 return soc15_asic_baco_reset(adev); 560 case AMD_RESET_METHOD_MODE2: 561 dev_info(adev->dev, "MODE2 reset\n"); 562 return amdgpu_dpm_mode2_reset(adev); 563 default: 564 dev_info(adev->dev, "MODE1 reset\n"); 565 return amdgpu_device_mode1_reset(adev); 566 } 567 } 568 569 static bool soc15_supports_baco(struct amdgpu_device *adev) 570 { 571 switch (adev->ip_versions[MP1_HWIP][0]) { 572 case IP_VERSION(9, 0, 0): 573 case IP_VERSION(11, 0, 2): 574 if (adev->asic_type == CHIP_VEGA20) { 575 if (adev->psp.sos.fw_version >= 0x80067) 576 return amdgpu_dpm_is_baco_supported(adev); 577 return false; 578 } else { 579 return amdgpu_dpm_is_baco_supported(adev); 580 } 581 break; 582 default: 583 return false; 584 } 585 } 586 587 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 588 u32 cntl_reg, u32 status_reg) 589 { 590 return 0; 591 }*/ 592 593 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 594 { 595 /*int r; 596 597 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 598 if (r) 599 return r; 600 601 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 602 */ 603 return 0; 604 } 605 606 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 607 { 608 /* todo */ 609 610 return 0; 611 } 612 613 static void soc15_program_aspm(struct amdgpu_device *adev) 614 { 615 if (!amdgpu_device_should_use_aspm(adev)) 616 return; 617 618 if (!(adev->flags & AMD_IS_APU) && 619 (adev->nbio.funcs->program_aspm)) 620 adev->nbio.funcs->program_aspm(adev); 621 } 622 623 const struct amdgpu_ip_block_version vega10_common_ip_block = 624 { 625 .type = AMD_IP_BLOCK_TYPE_COMMON, 626 .major = 2, 627 .minor = 0, 628 .rev = 0, 629 .funcs = &soc15_common_ip_funcs, 630 }; 631 632 static void soc15_reg_base_init(struct amdgpu_device *adev) 633 { 634 /* Set IP register base before any HW register access */ 635 switch (adev->asic_type) { 636 case CHIP_VEGA10: 637 case CHIP_VEGA12: 638 case CHIP_RAVEN: 639 case CHIP_RENOIR: 640 vega10_reg_base_init(adev); 641 break; 642 case CHIP_VEGA20: 643 vega20_reg_base_init(adev); 644 break; 645 case CHIP_ARCTURUS: 646 arct_reg_base_init(adev); 647 break; 648 case CHIP_ALDEBARAN: 649 aldebaran_reg_base_init(adev); 650 break; 651 default: 652 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); 653 break; 654 } 655 } 656 657 void soc15_set_virt_ops(struct amdgpu_device *adev) 658 { 659 adev->virt.ops = &xgpu_ai_virt_ops; 660 661 /* init soc15 reg base early enough so we can 662 * request request full access for sriov before 663 * set_ip_blocks. */ 664 soc15_reg_base_init(adev); 665 } 666 667 static bool soc15_need_full_reset(struct amdgpu_device *adev) 668 { 669 /* change this when we implement soft reset */ 670 return true; 671 } 672 673 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 674 uint64_t *count1) 675 { 676 uint32_t perfctr = 0; 677 uint64_t cnt0_of, cnt1_of; 678 int tmp; 679 680 /* This reports 0 on APUs, so return to avoid writing/reading registers 681 * that may or may not be different from their GPU counterparts 682 */ 683 if (adev->flags & AMD_IS_APU) 684 return; 685 686 /* Set the 2 events that we wish to watch, defined above */ 687 /* Reg 40 is # received msgs */ 688 /* Reg 104 is # of posted requests sent */ 689 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 690 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 691 692 /* Write to enable desired perf counters */ 693 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 694 /* Zero out and enable the perf counters 695 * Write 0x5: 696 * Bit 0 = Start all counters(1) 697 * Bit 2 = Global counter reset enable(1) 698 */ 699 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 700 701 msleep(1000); 702 703 /* Load the shadow and disable the perf counters 704 * Write 0x2: 705 * Bit 0 = Stop counters(0) 706 * Bit 1 = Load the shadow counters(1) 707 */ 708 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 709 710 /* Read register values to get any >32bit overflow */ 711 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 712 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 713 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 714 715 /* Get the values and add the overflow */ 716 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 717 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 718 } 719 720 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 721 uint64_t *count1) 722 { 723 uint32_t perfctr = 0; 724 uint64_t cnt0_of, cnt1_of; 725 int tmp; 726 727 /* This reports 0 on APUs, so return to avoid writing/reading registers 728 * that may or may not be different from their GPU counterparts 729 */ 730 if (adev->flags & AMD_IS_APU) 731 return; 732 733 /* Set the 2 events that we wish to watch, defined above */ 734 /* Reg 40 is # received msgs */ 735 /* Reg 108 is # of posted requests sent on VG20 */ 736 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 737 EVENT0_SEL, 40); 738 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 739 EVENT1_SEL, 108); 740 741 /* Write to enable desired perf counters */ 742 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 743 /* Zero out and enable the perf counters 744 * Write 0x5: 745 * Bit 0 = Start all counters(1) 746 * Bit 2 = Global counter reset enable(1) 747 */ 748 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 749 750 msleep(1000); 751 752 /* Load the shadow and disable the perf counters 753 * Write 0x2: 754 * Bit 0 = Stop counters(0) 755 * Bit 1 = Load the shadow counters(1) 756 */ 757 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 758 759 /* Read register values to get any >32bit overflow */ 760 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 761 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 762 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 763 764 /* Get the values and add the overflow */ 765 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 766 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 767 } 768 769 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 770 { 771 u32 sol_reg; 772 773 /* CP hangs in IGT reloading test on RN, reset to WA */ 774 if (adev->asic_type == CHIP_RENOIR) 775 return true; 776 777 /* Just return false for soc15 GPUs. Reset does not seem to 778 * be necessary. 779 */ 780 if (!amdgpu_passthrough(adev)) 781 return false; 782 783 if (adev->flags & AMD_IS_APU) 784 return false; 785 786 /* Check sOS sign of life register to confirm sys driver and sOS 787 * are already been loaded. 788 */ 789 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 790 if (sol_reg) 791 return true; 792 793 return false; 794 } 795 796 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 797 { 798 uint64_t nak_r, nak_g; 799 800 /* Get the number of NAKs received and generated */ 801 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 802 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 803 804 /* Add the total number of NAKs, i.e the number of replays */ 805 return (nak_r + nak_g); 806 } 807 808 static void soc15_pre_asic_init(struct amdgpu_device *adev) 809 { 810 gmc_v9_0_restore_registers(adev); 811 } 812 813 static const struct amdgpu_asic_funcs soc15_asic_funcs = 814 { 815 .read_disabled_bios = &soc15_read_disabled_bios, 816 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 817 .read_register = &soc15_read_register, 818 .reset = &soc15_asic_reset, 819 .reset_method = &soc15_asic_reset_method, 820 .set_vga_state = &soc15_vga_set_state, 821 .get_xclk = &soc15_get_xclk, 822 .set_uvd_clocks = &soc15_set_uvd_clocks, 823 .set_vce_clocks = &soc15_set_vce_clocks, 824 .get_config_memsize = &soc15_get_config_memsize, 825 .need_full_reset = &soc15_need_full_reset, 826 .init_doorbell_index = &vega10_doorbell_index_init, 827 .get_pcie_usage = &soc15_get_pcie_usage, 828 .need_reset_on_init = &soc15_need_reset_on_init, 829 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 830 .supports_baco = &soc15_supports_baco, 831 .pre_asic_init = &soc15_pre_asic_init, 832 .query_video_codecs = &soc15_query_video_codecs, 833 }; 834 835 static const struct amdgpu_asic_funcs vega20_asic_funcs = 836 { 837 .read_disabled_bios = &soc15_read_disabled_bios, 838 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 839 .read_register = &soc15_read_register, 840 .reset = &soc15_asic_reset, 841 .reset_method = &soc15_asic_reset_method, 842 .set_vga_state = &soc15_vga_set_state, 843 .get_xclk = &soc15_get_xclk, 844 .set_uvd_clocks = &soc15_set_uvd_clocks, 845 .set_vce_clocks = &soc15_set_vce_clocks, 846 .get_config_memsize = &soc15_get_config_memsize, 847 .need_full_reset = &soc15_need_full_reset, 848 .init_doorbell_index = &vega20_doorbell_index_init, 849 .get_pcie_usage = &vega20_get_pcie_usage, 850 .need_reset_on_init = &soc15_need_reset_on_init, 851 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 852 .supports_baco = &soc15_supports_baco, 853 .pre_asic_init = &soc15_pre_asic_init, 854 .query_video_codecs = &soc15_query_video_codecs, 855 }; 856 857 static int soc15_common_early_init(void *handle) 858 { 859 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 860 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 861 862 if (!amdgpu_sriov_vf(adev)) { 863 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 864 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 865 } 866 adev->smc_rreg = NULL; 867 adev->smc_wreg = NULL; 868 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 869 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 870 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 871 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 872 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 873 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 874 adev->didt_rreg = &soc15_didt_rreg; 875 adev->didt_wreg = &soc15_didt_wreg; 876 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 877 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 878 adev->se_cac_rreg = &soc15_se_cac_rreg; 879 adev->se_cac_wreg = &soc15_se_cac_wreg; 880 881 adev->rev_id = amdgpu_device_get_rev_id(adev); 882 adev->external_rev_id = 0xFF; 883 /* TODO: split the GC and PG flags based on the relevant IP version for which 884 * they are relevant. 885 */ 886 switch (adev->ip_versions[GC_HWIP][0]) { 887 case IP_VERSION(9, 0, 1): 888 adev->asic_funcs = &soc15_asic_funcs; 889 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 890 AMD_CG_SUPPORT_GFX_MGLS | 891 AMD_CG_SUPPORT_GFX_RLC_LS | 892 AMD_CG_SUPPORT_GFX_CP_LS | 893 AMD_CG_SUPPORT_GFX_3D_CGCG | 894 AMD_CG_SUPPORT_GFX_3D_CGLS | 895 AMD_CG_SUPPORT_GFX_CGCG | 896 AMD_CG_SUPPORT_GFX_CGLS | 897 AMD_CG_SUPPORT_BIF_MGCG | 898 AMD_CG_SUPPORT_BIF_LS | 899 AMD_CG_SUPPORT_HDP_LS | 900 AMD_CG_SUPPORT_DRM_MGCG | 901 AMD_CG_SUPPORT_DRM_LS | 902 AMD_CG_SUPPORT_ROM_MGCG | 903 AMD_CG_SUPPORT_DF_MGCG | 904 AMD_CG_SUPPORT_SDMA_MGCG | 905 AMD_CG_SUPPORT_SDMA_LS | 906 AMD_CG_SUPPORT_MC_MGCG | 907 AMD_CG_SUPPORT_MC_LS; 908 adev->pg_flags = 0; 909 adev->external_rev_id = 0x1; 910 break; 911 case IP_VERSION(9, 2, 1): 912 adev->asic_funcs = &soc15_asic_funcs; 913 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 914 AMD_CG_SUPPORT_GFX_MGLS | 915 AMD_CG_SUPPORT_GFX_CGCG | 916 AMD_CG_SUPPORT_GFX_CGLS | 917 AMD_CG_SUPPORT_GFX_3D_CGCG | 918 AMD_CG_SUPPORT_GFX_3D_CGLS | 919 AMD_CG_SUPPORT_GFX_CP_LS | 920 AMD_CG_SUPPORT_MC_LS | 921 AMD_CG_SUPPORT_MC_MGCG | 922 AMD_CG_SUPPORT_SDMA_MGCG | 923 AMD_CG_SUPPORT_SDMA_LS | 924 AMD_CG_SUPPORT_BIF_MGCG | 925 AMD_CG_SUPPORT_BIF_LS | 926 AMD_CG_SUPPORT_HDP_MGCG | 927 AMD_CG_SUPPORT_HDP_LS | 928 AMD_CG_SUPPORT_ROM_MGCG | 929 AMD_CG_SUPPORT_VCE_MGCG | 930 AMD_CG_SUPPORT_UVD_MGCG; 931 adev->pg_flags = 0; 932 adev->external_rev_id = adev->rev_id + 0x14; 933 break; 934 case IP_VERSION(9, 4, 0): 935 adev->asic_funcs = &vega20_asic_funcs; 936 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 937 AMD_CG_SUPPORT_GFX_MGLS | 938 AMD_CG_SUPPORT_GFX_CGCG | 939 AMD_CG_SUPPORT_GFX_CGLS | 940 AMD_CG_SUPPORT_GFX_3D_CGCG | 941 AMD_CG_SUPPORT_GFX_3D_CGLS | 942 AMD_CG_SUPPORT_GFX_CP_LS | 943 AMD_CG_SUPPORT_MC_LS | 944 AMD_CG_SUPPORT_MC_MGCG | 945 AMD_CG_SUPPORT_SDMA_MGCG | 946 AMD_CG_SUPPORT_SDMA_LS | 947 AMD_CG_SUPPORT_BIF_MGCG | 948 AMD_CG_SUPPORT_BIF_LS | 949 AMD_CG_SUPPORT_HDP_MGCG | 950 AMD_CG_SUPPORT_HDP_LS | 951 AMD_CG_SUPPORT_ROM_MGCG | 952 AMD_CG_SUPPORT_VCE_MGCG | 953 AMD_CG_SUPPORT_UVD_MGCG; 954 adev->pg_flags = 0; 955 adev->external_rev_id = adev->rev_id + 0x28; 956 break; 957 case IP_VERSION(9, 1, 0): 958 case IP_VERSION(9, 2, 2): 959 adev->asic_funcs = &soc15_asic_funcs; 960 961 if (adev->rev_id >= 0x8) 962 adev->apu_flags |= AMD_APU_IS_RAVEN2; 963 964 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 965 adev->external_rev_id = adev->rev_id + 0x79; 966 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 967 adev->external_rev_id = adev->rev_id + 0x41; 968 else if (adev->rev_id == 1) 969 adev->external_rev_id = adev->rev_id + 0x20; 970 else 971 adev->external_rev_id = adev->rev_id + 0x01; 972 973 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 974 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 975 AMD_CG_SUPPORT_GFX_MGLS | 976 AMD_CG_SUPPORT_GFX_CP_LS | 977 AMD_CG_SUPPORT_GFX_3D_CGCG | 978 AMD_CG_SUPPORT_GFX_3D_CGLS | 979 AMD_CG_SUPPORT_GFX_CGCG | 980 AMD_CG_SUPPORT_GFX_CGLS | 981 AMD_CG_SUPPORT_BIF_LS | 982 AMD_CG_SUPPORT_HDP_LS | 983 AMD_CG_SUPPORT_MC_MGCG | 984 AMD_CG_SUPPORT_MC_LS | 985 AMD_CG_SUPPORT_SDMA_MGCG | 986 AMD_CG_SUPPORT_SDMA_LS | 987 AMD_CG_SUPPORT_VCN_MGCG; 988 989 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 990 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { 991 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 992 AMD_CG_SUPPORT_GFX_MGLS | 993 AMD_CG_SUPPORT_GFX_CP_LS | 994 AMD_CG_SUPPORT_GFX_3D_CGLS | 995 AMD_CG_SUPPORT_GFX_CGCG | 996 AMD_CG_SUPPORT_GFX_CGLS | 997 AMD_CG_SUPPORT_BIF_LS | 998 AMD_CG_SUPPORT_HDP_LS | 999 AMD_CG_SUPPORT_MC_MGCG | 1000 AMD_CG_SUPPORT_MC_LS | 1001 AMD_CG_SUPPORT_SDMA_MGCG | 1002 AMD_CG_SUPPORT_SDMA_LS | 1003 AMD_CG_SUPPORT_VCN_MGCG; 1004 1005 /* 1006 * MMHUB PG needs to be disabled for Picasso for 1007 * stability reasons. 1008 */ 1009 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1010 AMD_PG_SUPPORT_VCN; 1011 } else { 1012 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1013 AMD_CG_SUPPORT_GFX_MGLS | 1014 AMD_CG_SUPPORT_GFX_RLC_LS | 1015 AMD_CG_SUPPORT_GFX_CP_LS | 1016 AMD_CG_SUPPORT_GFX_3D_CGLS | 1017 AMD_CG_SUPPORT_GFX_CGCG | 1018 AMD_CG_SUPPORT_GFX_CGLS | 1019 AMD_CG_SUPPORT_BIF_MGCG | 1020 AMD_CG_SUPPORT_BIF_LS | 1021 AMD_CG_SUPPORT_HDP_MGCG | 1022 AMD_CG_SUPPORT_HDP_LS | 1023 AMD_CG_SUPPORT_DRM_MGCG | 1024 AMD_CG_SUPPORT_DRM_LS | 1025 AMD_CG_SUPPORT_MC_MGCG | 1026 AMD_CG_SUPPORT_MC_LS | 1027 AMD_CG_SUPPORT_SDMA_MGCG | 1028 AMD_CG_SUPPORT_SDMA_LS | 1029 AMD_CG_SUPPORT_VCN_MGCG; 1030 1031 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1032 } 1033 break; 1034 case IP_VERSION(9, 4, 1): 1035 adev->asic_funcs = &vega20_asic_funcs; 1036 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1037 AMD_CG_SUPPORT_GFX_MGLS | 1038 AMD_CG_SUPPORT_GFX_CGCG | 1039 AMD_CG_SUPPORT_GFX_CGLS | 1040 AMD_CG_SUPPORT_GFX_CP_LS | 1041 AMD_CG_SUPPORT_HDP_MGCG | 1042 AMD_CG_SUPPORT_HDP_LS | 1043 AMD_CG_SUPPORT_SDMA_MGCG | 1044 AMD_CG_SUPPORT_SDMA_LS | 1045 AMD_CG_SUPPORT_MC_MGCG | 1046 AMD_CG_SUPPORT_MC_LS | 1047 AMD_CG_SUPPORT_IH_CG | 1048 AMD_CG_SUPPORT_VCN_MGCG | 1049 AMD_CG_SUPPORT_JPEG_MGCG; 1050 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; 1051 adev->external_rev_id = adev->rev_id + 0x32; 1052 break; 1053 case IP_VERSION(9, 3, 0): 1054 adev->asic_funcs = &soc15_asic_funcs; 1055 1056 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1057 adev->external_rev_id = adev->rev_id + 0x91; 1058 else 1059 adev->external_rev_id = adev->rev_id + 0xa1; 1060 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1061 AMD_CG_SUPPORT_GFX_MGLS | 1062 AMD_CG_SUPPORT_GFX_3D_CGCG | 1063 AMD_CG_SUPPORT_GFX_3D_CGLS | 1064 AMD_CG_SUPPORT_GFX_CGCG | 1065 AMD_CG_SUPPORT_GFX_CGLS | 1066 AMD_CG_SUPPORT_GFX_CP_LS | 1067 AMD_CG_SUPPORT_MC_MGCG | 1068 AMD_CG_SUPPORT_MC_LS | 1069 AMD_CG_SUPPORT_SDMA_MGCG | 1070 AMD_CG_SUPPORT_SDMA_LS | 1071 AMD_CG_SUPPORT_BIF_LS | 1072 AMD_CG_SUPPORT_HDP_LS | 1073 AMD_CG_SUPPORT_VCN_MGCG | 1074 AMD_CG_SUPPORT_JPEG_MGCG | 1075 AMD_CG_SUPPORT_IH_CG | 1076 AMD_CG_SUPPORT_ATHUB_LS | 1077 AMD_CG_SUPPORT_ATHUB_MGCG | 1078 AMD_CG_SUPPORT_DF_MGCG; 1079 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1080 AMD_PG_SUPPORT_VCN | 1081 AMD_PG_SUPPORT_JPEG | 1082 AMD_PG_SUPPORT_VCN_DPG; 1083 break; 1084 case IP_VERSION(9, 4, 2): 1085 adev->asic_funcs = &vega20_asic_funcs; 1086 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1087 AMD_CG_SUPPORT_GFX_MGLS | 1088 AMD_CG_SUPPORT_GFX_CP_LS | 1089 AMD_CG_SUPPORT_HDP_LS | 1090 AMD_CG_SUPPORT_SDMA_MGCG | 1091 AMD_CG_SUPPORT_SDMA_LS | 1092 AMD_CG_SUPPORT_IH_CG | 1093 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; 1094 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 1095 adev->external_rev_id = adev->rev_id + 0x3c; 1096 break; 1097 case IP_VERSION(9, 4, 3): 1098 adev->asic_funcs = &vega20_asic_funcs; 1099 adev->cg_flags = 0; 1100 adev->pg_flags = 0; 1101 break; 1102 default: 1103 /* FIXME: not supported yet */ 1104 return -EINVAL; 1105 } 1106 1107 if (amdgpu_sriov_vf(adev)) { 1108 amdgpu_virt_init_setting(adev); 1109 xgpu_ai_mailbox_set_irq_funcs(adev); 1110 } 1111 1112 return 0; 1113 } 1114 1115 static int soc15_common_late_init(void *handle) 1116 { 1117 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1118 1119 if (amdgpu_sriov_vf(adev)) 1120 xgpu_ai_mailbox_get_irq(adev); 1121 1122 /* Enable selfring doorbell aperture late because doorbell BAR 1123 * aperture will change if resize BAR successfully in gmc sw_init. 1124 */ 1125 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 1126 1127 return 0; 1128 } 1129 1130 static int soc15_common_sw_init(void *handle) 1131 { 1132 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1133 1134 if (amdgpu_sriov_vf(adev)) 1135 xgpu_ai_mailbox_add_irq_id(adev); 1136 1137 if (adev->df.funcs && 1138 adev->df.funcs->sw_init) 1139 adev->df.funcs->sw_init(adev); 1140 1141 return 0; 1142 } 1143 1144 static int soc15_common_sw_fini(void *handle) 1145 { 1146 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1147 1148 if (adev->df.funcs && 1149 adev->df.funcs->sw_fini) 1150 adev->df.funcs->sw_fini(adev); 1151 return 0; 1152 } 1153 1154 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev) 1155 { 1156 int i; 1157 1158 /* sdma doorbell range is programed by hypervisor */ 1159 if (!amdgpu_sriov_vf(adev)) { 1160 for (i = 0; i < adev->sdma.num_instances; i++) { 1161 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1162 true, adev->doorbell_index.sdma_engine[i] << 1, 1163 adev->doorbell_index.sdma_doorbell_range); 1164 } 1165 } 1166 } 1167 1168 static int soc15_common_hw_init(void *handle) 1169 { 1170 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1171 1172 /* enable aspm */ 1173 soc15_program_aspm(adev); 1174 /* setup nbio registers */ 1175 adev->nbio.funcs->init_registers(adev); 1176 /* remap HDP registers to a hole in mmio space, 1177 * for the purpose of expose those registers 1178 * to process space 1179 */ 1180 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1181 adev->nbio.funcs->remap_hdp_registers(adev); 1182 1183 /* enable the doorbell aperture */ 1184 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1185 1186 /* HW doorbell routing policy: doorbell writing not 1187 * in SDMA/IH/MM/ACV range will be routed to CP. So 1188 * we need to init SDMA doorbell range prior 1189 * to CP ip block init and ring test. IH already 1190 * happens before CP. 1191 */ 1192 soc15_sdma_doorbell_range_init(adev); 1193 1194 return 0; 1195 } 1196 1197 static int soc15_common_hw_fini(void *handle) 1198 { 1199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1200 1201 /* Disable the doorbell aperture and selfring doorbell aperture 1202 * separately in hw_fini because soc15_enable_doorbell_aperture 1203 * has been removed and there is no need to delay disabling 1204 * selfring doorbell. 1205 */ 1206 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1207 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1208 1209 if (amdgpu_sriov_vf(adev)) 1210 xgpu_ai_mailbox_put_irq(adev); 1211 1212 if (adev->nbio.ras_if && 1213 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1214 if (adev->nbio.ras && 1215 adev->nbio.ras->init_ras_controller_interrupt) 1216 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1217 if (adev->nbio.ras && 1218 adev->nbio.ras->init_ras_err_event_athub_interrupt) 1219 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1220 } 1221 1222 return 0; 1223 } 1224 1225 static int soc15_common_suspend(void *handle) 1226 { 1227 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1228 1229 return soc15_common_hw_fini(adev); 1230 } 1231 1232 static int soc15_common_resume(void *handle) 1233 { 1234 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1235 1236 return soc15_common_hw_init(adev); 1237 } 1238 1239 static bool soc15_common_is_idle(void *handle) 1240 { 1241 return true; 1242 } 1243 1244 static int soc15_common_wait_for_idle(void *handle) 1245 { 1246 return 0; 1247 } 1248 1249 static int soc15_common_soft_reset(void *handle) 1250 { 1251 return 0; 1252 } 1253 1254 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1255 { 1256 uint32_t def, data; 1257 1258 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1259 1260 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1261 data &= ~(0x01000000 | 1262 0x02000000 | 1263 0x04000000 | 1264 0x08000000 | 1265 0x10000000 | 1266 0x20000000 | 1267 0x40000000 | 1268 0x80000000); 1269 else 1270 data |= (0x01000000 | 1271 0x02000000 | 1272 0x04000000 | 1273 0x08000000 | 1274 0x10000000 | 1275 0x20000000 | 1276 0x40000000 | 1277 0x80000000); 1278 1279 if (def != data) 1280 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1281 } 1282 1283 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1284 { 1285 uint32_t def, data; 1286 1287 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1288 1289 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1290 data |= 1; 1291 else 1292 data &= ~1; 1293 1294 if (def != data) 1295 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1296 } 1297 1298 static int soc15_common_set_clockgating_state(void *handle, 1299 enum amd_clockgating_state state) 1300 { 1301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1302 1303 if (amdgpu_sriov_vf(adev)) 1304 return 0; 1305 1306 switch (adev->ip_versions[NBIO_HWIP][0]) { 1307 case IP_VERSION(6, 1, 0): 1308 case IP_VERSION(6, 2, 0): 1309 case IP_VERSION(7, 4, 0): 1310 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1311 state == AMD_CG_STATE_GATE); 1312 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1313 state == AMD_CG_STATE_GATE); 1314 adev->hdp.funcs->update_clock_gating(adev, 1315 state == AMD_CG_STATE_GATE); 1316 soc15_update_drm_clock_gating(adev, 1317 state == AMD_CG_STATE_GATE); 1318 soc15_update_drm_light_sleep(adev, 1319 state == AMD_CG_STATE_GATE); 1320 adev->smuio.funcs->update_rom_clock_gating(adev, 1321 state == AMD_CG_STATE_GATE); 1322 adev->df.funcs->update_medium_grain_clock_gating(adev, 1323 state == AMD_CG_STATE_GATE); 1324 break; 1325 case IP_VERSION(7, 0, 0): 1326 case IP_VERSION(7, 0, 1): 1327 case IP_VERSION(2, 5, 0): 1328 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1329 state == AMD_CG_STATE_GATE); 1330 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1331 state == AMD_CG_STATE_GATE); 1332 adev->hdp.funcs->update_clock_gating(adev, 1333 state == AMD_CG_STATE_GATE); 1334 soc15_update_drm_clock_gating(adev, 1335 state == AMD_CG_STATE_GATE); 1336 soc15_update_drm_light_sleep(adev, 1337 state == AMD_CG_STATE_GATE); 1338 break; 1339 case IP_VERSION(7, 4, 1): 1340 case IP_VERSION(7, 4, 4): 1341 adev->hdp.funcs->update_clock_gating(adev, 1342 state == AMD_CG_STATE_GATE); 1343 break; 1344 default: 1345 break; 1346 } 1347 return 0; 1348 } 1349 1350 static void soc15_common_get_clockgating_state(void *handle, u64 *flags) 1351 { 1352 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1353 int data; 1354 1355 if (amdgpu_sriov_vf(adev)) 1356 *flags = 0; 1357 1358 adev->nbio.funcs->get_clockgating_state(adev, flags); 1359 1360 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1361 1362 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) { 1363 1364 /* AMD_CG_SUPPORT_DRM_MGCG */ 1365 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1366 if (!(data & 0x01000000)) 1367 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1368 1369 /* AMD_CG_SUPPORT_DRM_LS */ 1370 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1371 if (data & 0x1) 1372 *flags |= AMD_CG_SUPPORT_DRM_LS; 1373 } 1374 1375 /* AMD_CG_SUPPORT_ROM_MGCG */ 1376 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1377 1378 adev->df.funcs->get_clockgating_state(adev, flags); 1379 } 1380 1381 static int soc15_common_set_powergating_state(void *handle, 1382 enum amd_powergating_state state) 1383 { 1384 /* todo */ 1385 return 0; 1386 } 1387 1388 static const struct amd_ip_funcs soc15_common_ip_funcs = { 1389 .name = "soc15_common", 1390 .early_init = soc15_common_early_init, 1391 .late_init = soc15_common_late_init, 1392 .sw_init = soc15_common_sw_init, 1393 .sw_fini = soc15_common_sw_fini, 1394 .hw_init = soc15_common_hw_init, 1395 .hw_fini = soc15_common_hw_fini, 1396 .suspend = soc15_common_suspend, 1397 .resume = soc15_common_resume, 1398 .is_idle = soc15_common_is_idle, 1399 .wait_for_idle = soc15_common_wait_for_idle, 1400 .soft_reset = soc15_common_soft_reset, 1401 .set_clockgating_state = soc15_common_set_clockgating_state, 1402 .set_powergating_state = soc15_common_set_powergating_state, 1403 .get_clockgating_state= soc15_common_get_clockgating_state, 1404 }; 1405