1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_atombios.h" 29 #include "amdgpu_ih.h" 30 #include "amdgpu_uvd.h" 31 #include "amdgpu_vce.h" 32 #include "amdgpu_ucode.h" 33 #include "amdgpu_psp.h" 34 #include "atom.h" 35 #include "amd_pcie.h" 36 37 #include "uvd/uvd_7_0_offset.h" 38 #include "gc/gc_9_0_offset.h" 39 #include "gc/gc_9_0_sh_mask.h" 40 #include "sdma0/sdma0_4_0_offset.h" 41 #include "sdma1/sdma1_4_0_offset.h" 42 #include "hdp/hdp_4_0_offset.h" 43 #include "hdp/hdp_4_0_sh_mask.h" 44 #include "smuio/smuio_9_0_offset.h" 45 #include "smuio/smuio_9_0_sh_mask.h" 46 #include "nbio/nbio_7_0_default.h" 47 #include "nbio/nbio_7_0_sh_mask.h" 48 #include "nbio/nbio_7_0_smn.h" 49 #include "mp/mp_9_0_offset.h" 50 51 #include "soc15.h" 52 #include "soc15_common.h" 53 #include "gfx_v9_0.h" 54 #include "gmc_v9_0.h" 55 #include "gfxhub_v1_0.h" 56 #include "mmhub_v1_0.h" 57 #include "df_v1_7.h" 58 #include "df_v3_6.h" 59 #include "vega10_ih.h" 60 #include "sdma_v4_0.h" 61 #include "uvd_v7_0.h" 62 #include "vce_v4_0.h" 63 #include "vcn_v1_0.h" 64 #include "dce_virtual.h" 65 #include "mxgpu_ai.h" 66 #include "amdgpu_smu.h" 67 68 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 69 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 70 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 71 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 72 73 /* for Vega20 register name change */ 74 #define mmHDP_MEM_POWER_CTRL 0x00d4 75 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 76 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 77 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 78 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 79 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 80 /* 81 * Indirect registers accessor 82 */ 83 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 84 { 85 unsigned long flags, address, data; 86 u32 r; 87 address = adev->nbio_funcs->get_pcie_index_offset(adev); 88 data = adev->nbio_funcs->get_pcie_data_offset(adev); 89 90 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 91 WREG32(address, reg); 92 (void)RREG32(address); 93 r = RREG32(data); 94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 95 return r; 96 } 97 98 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 99 { 100 unsigned long flags, address, data; 101 102 address = adev->nbio_funcs->get_pcie_index_offset(adev); 103 data = adev->nbio_funcs->get_pcie_data_offset(adev); 104 105 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 106 WREG32(address, reg); 107 (void)RREG32(address); 108 WREG32(data, v); 109 (void)RREG32(data); 110 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 111 } 112 113 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 114 { 115 unsigned long flags, address, data; 116 u32 r; 117 118 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 119 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 120 121 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 122 WREG32(address, ((reg) & 0x1ff)); 123 r = RREG32(data); 124 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 125 return r; 126 } 127 128 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 129 { 130 unsigned long flags, address, data; 131 132 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 133 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 134 135 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 136 WREG32(address, ((reg) & 0x1ff)); 137 WREG32(data, (v)); 138 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 139 } 140 141 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 142 { 143 unsigned long flags, address, data; 144 u32 r; 145 146 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 147 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 148 149 spin_lock_irqsave(&adev->didt_idx_lock, flags); 150 WREG32(address, (reg)); 151 r = RREG32(data); 152 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 153 return r; 154 } 155 156 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 157 { 158 unsigned long flags, address, data; 159 160 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 161 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 162 163 spin_lock_irqsave(&adev->didt_idx_lock, flags); 164 WREG32(address, (reg)); 165 WREG32(data, (v)); 166 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 167 } 168 169 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 170 { 171 unsigned long flags; 172 u32 r; 173 174 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 175 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 176 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 177 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 178 return r; 179 } 180 181 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 182 { 183 unsigned long flags; 184 185 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 186 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 187 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 188 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 189 } 190 191 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 192 { 193 unsigned long flags; 194 u32 r; 195 196 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 197 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 198 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 199 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 200 return r; 201 } 202 203 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 204 { 205 unsigned long flags; 206 207 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 208 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 209 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 210 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 211 } 212 213 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 214 { 215 return adev->nbio_funcs->get_memsize(adev); 216 } 217 218 static u32 soc15_get_xclk(struct amdgpu_device *adev) 219 { 220 return adev->clock.spll.reference_freq; 221 } 222 223 224 void soc15_grbm_select(struct amdgpu_device *adev, 225 u32 me, u32 pipe, u32 queue, u32 vmid) 226 { 227 u32 grbm_gfx_cntl = 0; 228 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 229 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 230 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 231 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 232 233 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 234 } 235 236 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 237 { 238 /* todo */ 239 } 240 241 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 242 { 243 /* todo */ 244 return false; 245 } 246 247 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 248 u8 *bios, u32 length_bytes) 249 { 250 u32 *dw_ptr; 251 u32 i, length_dw; 252 253 if (bios == NULL) 254 return false; 255 if (length_bytes == 0) 256 return false; 257 /* APU vbios image is part of sbios image */ 258 if (adev->flags & AMD_IS_APU) 259 return false; 260 261 dw_ptr = (u32 *)bios; 262 length_dw = ALIGN(length_bytes, 4) / 4; 263 264 /* set rom index to 0 */ 265 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 266 /* read out the rom data */ 267 for (i = 0; i < length_dw; i++) 268 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 269 270 return true; 271 } 272 273 struct soc15_allowed_register_entry { 274 uint32_t hwip; 275 uint32_t inst; 276 uint32_t seg; 277 uint32_t reg_offset; 278 bool grbm_indexed; 279 }; 280 281 282 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 283 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 284 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 285 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 286 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 287 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 288 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 289 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 290 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 291 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 292 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 293 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 294 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 295 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 296 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 297 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 298 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 299 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 300 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 301 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 302 }; 303 304 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 305 u32 sh_num, u32 reg_offset) 306 { 307 uint32_t val; 308 309 mutex_lock(&adev->grbm_idx_mutex); 310 if (se_num != 0xffffffff || sh_num != 0xffffffff) 311 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 312 313 val = RREG32(reg_offset); 314 315 if (se_num != 0xffffffff || sh_num != 0xffffffff) 316 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 317 mutex_unlock(&adev->grbm_idx_mutex); 318 return val; 319 } 320 321 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 322 bool indexed, u32 se_num, 323 u32 sh_num, u32 reg_offset) 324 { 325 if (indexed) { 326 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 327 } else { 328 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 329 return adev->gfx.config.gb_addr_config; 330 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 331 return adev->gfx.config.db_debug2; 332 return RREG32(reg_offset); 333 } 334 } 335 336 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 337 u32 sh_num, u32 reg_offset, u32 *value) 338 { 339 uint32_t i; 340 struct soc15_allowed_register_entry *en; 341 342 *value = 0; 343 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 344 en = &soc15_allowed_read_registers[i]; 345 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 346 + en->reg_offset)) 347 continue; 348 349 *value = soc15_get_register_value(adev, 350 soc15_allowed_read_registers[i].grbm_indexed, 351 se_num, sh_num, reg_offset); 352 return 0; 353 } 354 return -EINVAL; 355 } 356 357 358 /** 359 * soc15_program_register_sequence - program an array of registers. 360 * 361 * @adev: amdgpu_device pointer 362 * @regs: pointer to the register array 363 * @array_size: size of the register array 364 * 365 * Programs an array or registers with and and or masks. 366 * This is a helper for setting golden registers. 367 */ 368 369 void soc15_program_register_sequence(struct amdgpu_device *adev, 370 const struct soc15_reg_golden *regs, 371 const u32 array_size) 372 { 373 const struct soc15_reg_golden *entry; 374 u32 tmp, reg; 375 int i; 376 377 for (i = 0; i < array_size; ++i) { 378 entry = ®s[i]; 379 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 380 381 if (entry->and_mask == 0xffffffff) { 382 tmp = entry->or_mask; 383 } else { 384 tmp = RREG32(reg); 385 tmp &= ~(entry->and_mask); 386 tmp |= entry->or_mask; 387 } 388 WREG32(reg, tmp); 389 } 390 391 } 392 393 static int soc15_asic_mode1_reset(struct amdgpu_device *adev) 394 { 395 u32 i; 396 int ret = 0; 397 398 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 399 400 dev_info(adev->dev, "GPU mode1 reset\n"); 401 402 /* disable BM */ 403 pci_clear_master(adev->pdev); 404 405 pci_save_state(adev->pdev); 406 407 ret = psp_gpu_reset(adev); 408 if (ret) 409 dev_err(adev->dev, "GPU mode1 reset failed\n"); 410 411 pci_restore_state(adev->pdev); 412 413 /* wait for asic to come out of reset */ 414 for (i = 0; i < adev->usec_timeout; i++) { 415 u32 memsize = adev->nbio_funcs->get_memsize(adev); 416 417 if (memsize != 0xffffffff) 418 break; 419 udelay(1); 420 } 421 422 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 423 424 return ret; 425 } 426 427 static int soc15_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap) 428 { 429 void *pp_handle = adev->powerplay.pp_handle; 430 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 431 432 if (!pp_funcs || !pp_funcs->get_asic_baco_capability) { 433 *cap = false; 434 return -ENOENT; 435 } 436 437 return pp_funcs->get_asic_baco_capability(pp_handle, cap); 438 } 439 440 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 441 { 442 void *pp_handle = adev->powerplay.pp_handle; 443 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; 444 445 if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state) 446 return -ENOENT; 447 448 /* enter BACO state */ 449 if (pp_funcs->set_asic_baco_state(pp_handle, 1)) 450 return -EIO; 451 452 /* exit BACO state */ 453 if (pp_funcs->set_asic_baco_state(pp_handle, 0)) 454 return -EIO; 455 456 dev_info(adev->dev, "GPU BACO reset\n"); 457 458 adev->in_baco_reset = 1; 459 460 return 0; 461 } 462 463 static int soc15_asic_reset(struct amdgpu_device *adev) 464 { 465 int ret; 466 bool baco_reset; 467 468 switch (adev->asic_type) { 469 case CHIP_VEGA10: 470 case CHIP_VEGA12: 471 soc15_asic_get_baco_capability(adev, &baco_reset); 472 break; 473 case CHIP_VEGA20: 474 if (adev->psp.sos_fw_version >= 0x80067) 475 soc15_asic_get_baco_capability(adev, &baco_reset); 476 else 477 baco_reset = false; 478 break; 479 default: 480 baco_reset = false; 481 break; 482 } 483 484 if (baco_reset) 485 ret = soc15_asic_baco_reset(adev); 486 else 487 ret = soc15_asic_mode1_reset(adev); 488 489 return ret; 490 } 491 492 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 493 u32 cntl_reg, u32 status_reg) 494 { 495 return 0; 496 }*/ 497 498 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 499 { 500 /*int r; 501 502 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 503 if (r) 504 return r; 505 506 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 507 */ 508 return 0; 509 } 510 511 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 512 { 513 /* todo */ 514 515 return 0; 516 } 517 518 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 519 { 520 if (pci_is_root_bus(adev->pdev->bus)) 521 return; 522 523 if (amdgpu_pcie_gen2 == 0) 524 return; 525 526 if (adev->flags & AMD_IS_APU) 527 return; 528 529 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 530 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 531 return; 532 533 /* todo */ 534 } 535 536 static void soc15_program_aspm(struct amdgpu_device *adev) 537 { 538 539 if (amdgpu_aspm == 0) 540 return; 541 542 /* todo */ 543 } 544 545 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 546 bool enable) 547 { 548 adev->nbio_funcs->enable_doorbell_aperture(adev, enable); 549 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable); 550 } 551 552 static const struct amdgpu_ip_block_version vega10_common_ip_block = 553 { 554 .type = AMD_IP_BLOCK_TYPE_COMMON, 555 .major = 2, 556 .minor = 0, 557 .rev = 0, 558 .funcs = &soc15_common_ip_funcs, 559 }; 560 561 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 562 { 563 return adev->nbio_funcs->get_rev_id(adev); 564 } 565 566 int soc15_set_ip_blocks(struct amdgpu_device *adev) 567 { 568 /* Set IP register base before any HW register access */ 569 switch (adev->asic_type) { 570 case CHIP_VEGA10: 571 case CHIP_VEGA12: 572 case CHIP_RAVEN: 573 vega10_reg_base_init(adev); 574 break; 575 case CHIP_VEGA20: 576 vega20_reg_base_init(adev); 577 break; 578 default: 579 return -EINVAL; 580 } 581 582 if (adev->asic_type == CHIP_VEGA20) 583 adev->gmc.xgmi.supported = true; 584 585 if (adev->flags & AMD_IS_APU) 586 adev->nbio_funcs = &nbio_v7_0_funcs; 587 else if (adev->asic_type == CHIP_VEGA20) 588 adev->nbio_funcs = &nbio_v7_4_funcs; 589 else 590 adev->nbio_funcs = &nbio_v6_1_funcs; 591 592 if (adev->asic_type == CHIP_VEGA20) 593 adev->df_funcs = &df_v3_6_funcs; 594 else 595 adev->df_funcs = &df_v1_7_funcs; 596 597 adev->rev_id = soc15_get_rev_id(adev); 598 adev->nbio_funcs->detect_hw_virt(adev); 599 600 if (amdgpu_sriov_vf(adev)) 601 adev->virt.ops = &xgpu_ai_virt_ops; 602 603 switch (adev->asic_type) { 604 case CHIP_VEGA10: 605 case CHIP_VEGA12: 606 case CHIP_VEGA20: 607 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 608 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 609 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 610 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 611 if (adev->asic_type == CHIP_VEGA20) 612 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 613 else 614 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 615 } 616 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 617 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 618 if (!amdgpu_sriov_vf(adev)) { 619 if (is_support_sw_smu(adev)) 620 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 621 else 622 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 623 } 624 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 625 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 626 #if defined(CONFIG_DRM_AMD_DC) 627 else if (amdgpu_device_has_dc_support(adev)) 628 amdgpu_device_ip_block_add(adev, &dm_ip_block); 629 #else 630 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." 631 #endif 632 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { 633 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 634 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 635 } 636 break; 637 case CHIP_RAVEN: 638 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 639 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 640 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 641 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 642 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 643 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 644 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 645 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 646 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 647 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 648 #if defined(CONFIG_DRM_AMD_DC) 649 else if (amdgpu_device_has_dc_support(adev)) 650 amdgpu_device_ip_block_add(adev, &dm_ip_block); 651 #else 652 # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." 653 #endif 654 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 655 break; 656 default: 657 return -EINVAL; 658 } 659 660 return 0; 661 } 662 663 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 664 { 665 adev->nbio_funcs->hdp_flush(adev, ring); 666 } 667 668 static void soc15_invalidate_hdp(struct amdgpu_device *adev, 669 struct amdgpu_ring *ring) 670 { 671 if (!ring || !ring->funcs->emit_wreg) 672 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 673 else 674 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 675 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 676 } 677 678 static bool soc15_need_full_reset(struct amdgpu_device *adev) 679 { 680 /* change this when we implement soft reset */ 681 return true; 682 } 683 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 684 uint64_t *count1) 685 { 686 uint32_t perfctr = 0; 687 uint64_t cnt0_of, cnt1_of; 688 int tmp; 689 690 /* This reports 0 on APUs, so return to avoid writing/reading registers 691 * that may or may not be different from their GPU counterparts 692 */ 693 if (adev->flags & AMD_IS_APU) 694 return; 695 696 /* Set the 2 events that we wish to watch, defined above */ 697 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ 698 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 699 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 700 701 /* Write to enable desired perf counters */ 702 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 703 /* Zero out and enable the perf counters 704 * Write 0x5: 705 * Bit 0 = Start all counters(1) 706 * Bit 2 = Global counter reset enable(1) 707 */ 708 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 709 710 msleep(1000); 711 712 /* Load the shadow and disable the perf counters 713 * Write 0x2: 714 * Bit 0 = Stop counters(0) 715 * Bit 1 = Load the shadow counters(1) 716 */ 717 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 718 719 /* Read register values to get any >32bit overflow */ 720 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 721 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 722 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 723 724 /* Get the values and add the overflow */ 725 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 726 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 727 } 728 729 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 730 { 731 u32 sol_reg; 732 733 /* Just return false for soc15 GPUs. Reset does not seem to 734 * be necessary. 735 */ 736 return false; 737 738 if (adev->flags & AMD_IS_APU) 739 return false; 740 741 /* Check sOS sign of life register to confirm sys driver and sOS 742 * are already been loaded. 743 */ 744 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 745 if (sol_reg) 746 return true; 747 748 return false; 749 } 750 751 static const struct amdgpu_asic_funcs soc15_asic_funcs = 752 { 753 .read_disabled_bios = &soc15_read_disabled_bios, 754 .read_bios_from_rom = &soc15_read_bios_from_rom, 755 .read_register = &soc15_read_register, 756 .reset = &soc15_asic_reset, 757 .set_vga_state = &soc15_vga_set_state, 758 .get_xclk = &soc15_get_xclk, 759 .set_uvd_clocks = &soc15_set_uvd_clocks, 760 .set_vce_clocks = &soc15_set_vce_clocks, 761 .get_config_memsize = &soc15_get_config_memsize, 762 .flush_hdp = &soc15_flush_hdp, 763 .invalidate_hdp = &soc15_invalidate_hdp, 764 .need_full_reset = &soc15_need_full_reset, 765 .init_doorbell_index = &vega10_doorbell_index_init, 766 .get_pcie_usage = &soc15_get_pcie_usage, 767 .need_reset_on_init = &soc15_need_reset_on_init, 768 }; 769 770 static const struct amdgpu_asic_funcs vega20_asic_funcs = 771 { 772 .read_disabled_bios = &soc15_read_disabled_bios, 773 .read_bios_from_rom = &soc15_read_bios_from_rom, 774 .read_register = &soc15_read_register, 775 .reset = &soc15_asic_reset, 776 .set_vga_state = &soc15_vga_set_state, 777 .get_xclk = &soc15_get_xclk, 778 .set_uvd_clocks = &soc15_set_uvd_clocks, 779 .set_vce_clocks = &soc15_set_vce_clocks, 780 .get_config_memsize = &soc15_get_config_memsize, 781 .flush_hdp = &soc15_flush_hdp, 782 .invalidate_hdp = &soc15_invalidate_hdp, 783 .need_full_reset = &soc15_need_full_reset, 784 .init_doorbell_index = &vega20_doorbell_index_init, 785 .get_pcie_usage = &soc15_get_pcie_usage, 786 .need_reset_on_init = &soc15_need_reset_on_init, 787 }; 788 789 static int soc15_common_early_init(void *handle) 790 { 791 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 792 793 adev->smc_rreg = NULL; 794 adev->smc_wreg = NULL; 795 adev->pcie_rreg = &soc15_pcie_rreg; 796 adev->pcie_wreg = &soc15_pcie_wreg; 797 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 798 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 799 adev->didt_rreg = &soc15_didt_rreg; 800 adev->didt_wreg = &soc15_didt_wreg; 801 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 802 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 803 adev->se_cac_rreg = &soc15_se_cac_rreg; 804 adev->se_cac_wreg = &soc15_se_cac_wreg; 805 806 807 adev->external_rev_id = 0xFF; 808 switch (adev->asic_type) { 809 case CHIP_VEGA10: 810 adev->asic_funcs = &soc15_asic_funcs; 811 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 812 AMD_CG_SUPPORT_GFX_MGLS | 813 AMD_CG_SUPPORT_GFX_RLC_LS | 814 AMD_CG_SUPPORT_GFX_CP_LS | 815 AMD_CG_SUPPORT_GFX_3D_CGCG | 816 AMD_CG_SUPPORT_GFX_3D_CGLS | 817 AMD_CG_SUPPORT_GFX_CGCG | 818 AMD_CG_SUPPORT_GFX_CGLS | 819 AMD_CG_SUPPORT_BIF_MGCG | 820 AMD_CG_SUPPORT_BIF_LS | 821 AMD_CG_SUPPORT_HDP_LS | 822 AMD_CG_SUPPORT_DRM_MGCG | 823 AMD_CG_SUPPORT_DRM_LS | 824 AMD_CG_SUPPORT_ROM_MGCG | 825 AMD_CG_SUPPORT_DF_MGCG | 826 AMD_CG_SUPPORT_SDMA_MGCG | 827 AMD_CG_SUPPORT_SDMA_LS | 828 AMD_CG_SUPPORT_MC_MGCG | 829 AMD_CG_SUPPORT_MC_LS; 830 adev->pg_flags = 0; 831 adev->external_rev_id = 0x1; 832 break; 833 case CHIP_VEGA12: 834 adev->asic_funcs = &soc15_asic_funcs; 835 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 836 AMD_CG_SUPPORT_GFX_MGLS | 837 AMD_CG_SUPPORT_GFX_CGCG | 838 AMD_CG_SUPPORT_GFX_CGLS | 839 AMD_CG_SUPPORT_GFX_3D_CGCG | 840 AMD_CG_SUPPORT_GFX_3D_CGLS | 841 AMD_CG_SUPPORT_GFX_CP_LS | 842 AMD_CG_SUPPORT_MC_LS | 843 AMD_CG_SUPPORT_MC_MGCG | 844 AMD_CG_SUPPORT_SDMA_MGCG | 845 AMD_CG_SUPPORT_SDMA_LS | 846 AMD_CG_SUPPORT_BIF_MGCG | 847 AMD_CG_SUPPORT_BIF_LS | 848 AMD_CG_SUPPORT_HDP_MGCG | 849 AMD_CG_SUPPORT_HDP_LS | 850 AMD_CG_SUPPORT_ROM_MGCG | 851 AMD_CG_SUPPORT_VCE_MGCG | 852 AMD_CG_SUPPORT_UVD_MGCG; 853 adev->pg_flags = 0; 854 adev->external_rev_id = adev->rev_id + 0x14; 855 break; 856 case CHIP_VEGA20: 857 adev->asic_funcs = &vega20_asic_funcs; 858 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 859 AMD_CG_SUPPORT_GFX_MGLS | 860 AMD_CG_SUPPORT_GFX_CGCG | 861 AMD_CG_SUPPORT_GFX_CGLS | 862 AMD_CG_SUPPORT_GFX_3D_CGCG | 863 AMD_CG_SUPPORT_GFX_3D_CGLS | 864 AMD_CG_SUPPORT_GFX_CP_LS | 865 AMD_CG_SUPPORT_MC_LS | 866 AMD_CG_SUPPORT_MC_MGCG | 867 AMD_CG_SUPPORT_SDMA_MGCG | 868 AMD_CG_SUPPORT_SDMA_LS | 869 AMD_CG_SUPPORT_BIF_MGCG | 870 AMD_CG_SUPPORT_BIF_LS | 871 AMD_CG_SUPPORT_HDP_MGCG | 872 AMD_CG_SUPPORT_HDP_LS | 873 AMD_CG_SUPPORT_ROM_MGCG | 874 AMD_CG_SUPPORT_VCE_MGCG | 875 AMD_CG_SUPPORT_UVD_MGCG; 876 adev->pg_flags = 0; 877 adev->external_rev_id = adev->rev_id + 0x28; 878 break; 879 case CHIP_RAVEN: 880 adev->asic_funcs = &soc15_asic_funcs; 881 if (adev->rev_id >= 0x8) 882 adev->external_rev_id = adev->rev_id + 0x79; 883 else if (adev->pdev->device == 0x15d8) 884 adev->external_rev_id = adev->rev_id + 0x41; 885 else if (adev->rev_id == 1) 886 adev->external_rev_id = adev->rev_id + 0x20; 887 else 888 adev->external_rev_id = adev->rev_id + 0x01; 889 890 if (adev->rev_id >= 0x8) { 891 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 892 AMD_CG_SUPPORT_GFX_MGLS | 893 AMD_CG_SUPPORT_GFX_CP_LS | 894 AMD_CG_SUPPORT_GFX_3D_CGCG | 895 AMD_CG_SUPPORT_GFX_3D_CGLS | 896 AMD_CG_SUPPORT_GFX_CGCG | 897 AMD_CG_SUPPORT_GFX_CGLS | 898 AMD_CG_SUPPORT_BIF_LS | 899 AMD_CG_SUPPORT_HDP_LS | 900 AMD_CG_SUPPORT_ROM_MGCG | 901 AMD_CG_SUPPORT_MC_MGCG | 902 AMD_CG_SUPPORT_MC_LS | 903 AMD_CG_SUPPORT_SDMA_MGCG | 904 AMD_CG_SUPPORT_SDMA_LS | 905 AMD_CG_SUPPORT_VCN_MGCG; 906 907 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 908 } else if (adev->pdev->device == 0x15d8) { 909 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 910 AMD_CG_SUPPORT_GFX_MGLS | 911 AMD_CG_SUPPORT_GFX_CP_LS | 912 AMD_CG_SUPPORT_GFX_3D_CGCG | 913 AMD_CG_SUPPORT_GFX_3D_CGLS | 914 AMD_CG_SUPPORT_GFX_CGCG | 915 AMD_CG_SUPPORT_GFX_CGLS | 916 AMD_CG_SUPPORT_BIF_LS | 917 AMD_CG_SUPPORT_HDP_LS | 918 AMD_CG_SUPPORT_ROM_MGCG | 919 AMD_CG_SUPPORT_MC_MGCG | 920 AMD_CG_SUPPORT_MC_LS | 921 AMD_CG_SUPPORT_SDMA_MGCG | 922 AMD_CG_SUPPORT_SDMA_LS; 923 924 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 925 AMD_PG_SUPPORT_MMHUB | 926 AMD_PG_SUPPORT_VCN | 927 AMD_PG_SUPPORT_VCN_DPG; 928 } else { 929 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 930 AMD_CG_SUPPORT_GFX_MGLS | 931 AMD_CG_SUPPORT_GFX_RLC_LS | 932 AMD_CG_SUPPORT_GFX_CP_LS | 933 AMD_CG_SUPPORT_GFX_3D_CGCG | 934 AMD_CG_SUPPORT_GFX_3D_CGLS | 935 AMD_CG_SUPPORT_GFX_CGCG | 936 AMD_CG_SUPPORT_GFX_CGLS | 937 AMD_CG_SUPPORT_BIF_MGCG | 938 AMD_CG_SUPPORT_BIF_LS | 939 AMD_CG_SUPPORT_HDP_MGCG | 940 AMD_CG_SUPPORT_HDP_LS | 941 AMD_CG_SUPPORT_DRM_MGCG | 942 AMD_CG_SUPPORT_DRM_LS | 943 AMD_CG_SUPPORT_ROM_MGCG | 944 AMD_CG_SUPPORT_MC_MGCG | 945 AMD_CG_SUPPORT_MC_LS | 946 AMD_CG_SUPPORT_SDMA_MGCG | 947 AMD_CG_SUPPORT_SDMA_LS | 948 AMD_CG_SUPPORT_VCN_MGCG; 949 950 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 951 } 952 953 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 954 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 955 AMD_PG_SUPPORT_CP | 956 AMD_PG_SUPPORT_RLC_SMU_HS; 957 break; 958 default: 959 /* FIXME: not supported yet */ 960 return -EINVAL; 961 } 962 963 if (amdgpu_sriov_vf(adev)) { 964 amdgpu_virt_init_setting(adev); 965 xgpu_ai_mailbox_set_irq_funcs(adev); 966 } 967 968 return 0; 969 } 970 971 static int soc15_common_late_init(void *handle) 972 { 973 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 974 975 if (amdgpu_sriov_vf(adev)) 976 xgpu_ai_mailbox_get_irq(adev); 977 978 return 0; 979 } 980 981 static int soc15_common_sw_init(void *handle) 982 { 983 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 984 985 if (amdgpu_sriov_vf(adev)) 986 xgpu_ai_mailbox_add_irq_id(adev); 987 988 return 0; 989 } 990 991 static int soc15_common_sw_fini(void *handle) 992 { 993 return 0; 994 } 995 996 static void soc15_doorbell_range_init(struct amdgpu_device *adev) 997 { 998 int i; 999 struct amdgpu_ring *ring; 1000 1001 for (i = 0; i < adev->sdma.num_instances; i++) { 1002 ring = &adev->sdma.instance[i].ring; 1003 adev->nbio_funcs->sdma_doorbell_range(adev, i, 1004 ring->use_doorbell, ring->doorbell_index, 1005 adev->doorbell_index.sdma_doorbell_range); 1006 } 1007 1008 adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 1009 adev->irq.ih.doorbell_index); 1010 } 1011 1012 static int soc15_common_hw_init(void *handle) 1013 { 1014 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1015 1016 /* enable pcie gen2/3 link */ 1017 soc15_pcie_gen3_enable(adev); 1018 /* enable aspm */ 1019 soc15_program_aspm(adev); 1020 /* setup nbio registers */ 1021 adev->nbio_funcs->init_registers(adev); 1022 /* enable the doorbell aperture */ 1023 soc15_enable_doorbell_aperture(adev, true); 1024 /* HW doorbell routing policy: doorbell writing not 1025 * in SDMA/IH/MM/ACV range will be routed to CP. So 1026 * we need to init SDMA/IH/MM/ACV doorbell range prior 1027 * to CP ip block init and ring test. 1028 */ 1029 soc15_doorbell_range_init(adev); 1030 1031 return 0; 1032 } 1033 1034 static int soc15_common_hw_fini(void *handle) 1035 { 1036 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1037 1038 /* disable the doorbell aperture */ 1039 soc15_enable_doorbell_aperture(adev, false); 1040 if (amdgpu_sriov_vf(adev)) 1041 xgpu_ai_mailbox_put_irq(adev); 1042 1043 return 0; 1044 } 1045 1046 static int soc15_common_suspend(void *handle) 1047 { 1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1049 1050 return soc15_common_hw_fini(adev); 1051 } 1052 1053 static int soc15_common_resume(void *handle) 1054 { 1055 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1056 1057 return soc15_common_hw_init(adev); 1058 } 1059 1060 static bool soc15_common_is_idle(void *handle) 1061 { 1062 return true; 1063 } 1064 1065 static int soc15_common_wait_for_idle(void *handle) 1066 { 1067 return 0; 1068 } 1069 1070 static int soc15_common_soft_reset(void *handle) 1071 { 1072 return 0; 1073 } 1074 1075 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) 1076 { 1077 uint32_t def, data; 1078 1079 if (adev->asic_type == CHIP_VEGA20) { 1080 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); 1081 1082 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1083 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1084 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1085 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1086 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; 1087 else 1088 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1089 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1090 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1091 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); 1092 1093 if (def != data) 1094 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); 1095 } else { 1096 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1097 1098 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1099 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1100 else 1101 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1102 1103 if (def != data) 1104 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 1105 } 1106 } 1107 1108 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1109 { 1110 uint32_t def, data; 1111 1112 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1113 1114 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1115 data &= ~(0x01000000 | 1116 0x02000000 | 1117 0x04000000 | 1118 0x08000000 | 1119 0x10000000 | 1120 0x20000000 | 1121 0x40000000 | 1122 0x80000000); 1123 else 1124 data |= (0x01000000 | 1125 0x02000000 | 1126 0x04000000 | 1127 0x08000000 | 1128 0x10000000 | 1129 0x20000000 | 1130 0x40000000 | 1131 0x80000000); 1132 1133 if (def != data) 1134 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1135 } 1136 1137 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1138 { 1139 uint32_t def, data; 1140 1141 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1142 1143 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1144 data |= 1; 1145 else 1146 data &= ~1; 1147 1148 if (def != data) 1149 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1150 } 1151 1152 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1153 bool enable) 1154 { 1155 uint32_t def, data; 1156 1157 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1158 1159 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1160 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1161 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1162 else 1163 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1164 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1165 1166 if (def != data) 1167 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); 1168 } 1169 1170 static int soc15_common_set_clockgating_state(void *handle, 1171 enum amd_clockgating_state state) 1172 { 1173 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1174 1175 if (amdgpu_sriov_vf(adev)) 1176 return 0; 1177 1178 switch (adev->asic_type) { 1179 case CHIP_VEGA10: 1180 case CHIP_VEGA12: 1181 case CHIP_VEGA20: 1182 adev->nbio_funcs->update_medium_grain_clock_gating(adev, 1183 state == AMD_CG_STATE_GATE ? true : false); 1184 adev->nbio_funcs->update_medium_grain_light_sleep(adev, 1185 state == AMD_CG_STATE_GATE ? true : false); 1186 soc15_update_hdp_light_sleep(adev, 1187 state == AMD_CG_STATE_GATE ? true : false); 1188 soc15_update_drm_clock_gating(adev, 1189 state == AMD_CG_STATE_GATE ? true : false); 1190 soc15_update_drm_light_sleep(adev, 1191 state == AMD_CG_STATE_GATE ? true : false); 1192 soc15_update_rom_medium_grain_clock_gating(adev, 1193 state == AMD_CG_STATE_GATE ? true : false); 1194 adev->df_funcs->update_medium_grain_clock_gating(adev, 1195 state == AMD_CG_STATE_GATE ? true : false); 1196 break; 1197 case CHIP_RAVEN: 1198 adev->nbio_funcs->update_medium_grain_clock_gating(adev, 1199 state == AMD_CG_STATE_GATE ? true : false); 1200 adev->nbio_funcs->update_medium_grain_light_sleep(adev, 1201 state == AMD_CG_STATE_GATE ? true : false); 1202 soc15_update_hdp_light_sleep(adev, 1203 state == AMD_CG_STATE_GATE ? true : false); 1204 soc15_update_drm_clock_gating(adev, 1205 state == AMD_CG_STATE_GATE ? true : false); 1206 soc15_update_drm_light_sleep(adev, 1207 state == AMD_CG_STATE_GATE ? true : false); 1208 soc15_update_rom_medium_grain_clock_gating(adev, 1209 state == AMD_CG_STATE_GATE ? true : false); 1210 break; 1211 default: 1212 break; 1213 } 1214 return 0; 1215 } 1216 1217 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1218 { 1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1220 int data; 1221 1222 if (amdgpu_sriov_vf(adev)) 1223 *flags = 0; 1224 1225 adev->nbio_funcs->get_clockgating_state(adev, flags); 1226 1227 /* AMD_CG_SUPPORT_HDP_LS */ 1228 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1229 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 1230 *flags |= AMD_CG_SUPPORT_HDP_LS; 1231 1232 /* AMD_CG_SUPPORT_DRM_MGCG */ 1233 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1234 if (!(data & 0x01000000)) 1235 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1236 1237 /* AMD_CG_SUPPORT_DRM_LS */ 1238 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1239 if (data & 0x1) 1240 *flags |= AMD_CG_SUPPORT_DRM_LS; 1241 1242 /* AMD_CG_SUPPORT_ROM_MGCG */ 1243 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1244 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 1245 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 1246 1247 adev->df_funcs->get_clockgating_state(adev, flags); 1248 } 1249 1250 static int soc15_common_set_powergating_state(void *handle, 1251 enum amd_powergating_state state) 1252 { 1253 /* todo */ 1254 return 0; 1255 } 1256 1257 const struct amd_ip_funcs soc15_common_ip_funcs = { 1258 .name = "soc15_common", 1259 .early_init = soc15_common_early_init, 1260 .late_init = soc15_common_late_init, 1261 .sw_init = soc15_common_sw_init, 1262 .sw_fini = soc15_common_sw_fini, 1263 .hw_init = soc15_common_hw_init, 1264 .hw_fini = soc15_common_hw_fini, 1265 .suspend = soc15_common_suspend, 1266 .resume = soc15_common_resume, 1267 .is_idle = soc15_common_is_idle, 1268 .wait_for_idle = soc15_common_wait_for_idle, 1269 .soft_reset = soc15_common_soft_reset, 1270 .set_clockgating_state = soc15_common_set_clockgating_state, 1271 .set_powergating_state = soc15_common_set_powergating_state, 1272 .get_clockgating_state= soc15_common_get_clockgating_state, 1273 }; 1274