1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "uvd/uvd_7_0_offset.h" 41 #include "gc/gc_9_0_offset.h" 42 #include "gc/gc_9_0_sh_mask.h" 43 #include "sdma0/sdma0_4_0_offset.h" 44 #include "sdma1/sdma1_4_0_offset.h" 45 #include "nbio/nbio_7_0_default.h" 46 #include "nbio/nbio_7_0_offset.h" 47 #include "nbio/nbio_7_0_sh_mask.h" 48 #include "nbio/nbio_7_0_smn.h" 49 #include "mp/mp_9_0_offset.h" 50 51 #include "soc15.h" 52 #include "soc15_common.h" 53 #include "gfx_v9_0.h" 54 #include "gmc_v9_0.h" 55 #include "gfxhub_v1_0.h" 56 #include "mmhub_v1_0.h" 57 #include "df_v1_7.h" 58 #include "df_v3_6.h" 59 #include "nbio_v6_1.h" 60 #include "nbio_v7_0.h" 61 #include "nbio_v7_4.h" 62 #include "hdp_v4_0.h" 63 #include "vega10_ih.h" 64 #include "vega20_ih.h" 65 #include "navi10_ih.h" 66 #include "sdma_v4_0.h" 67 #include "uvd_v7_0.h" 68 #include "vce_v4_0.h" 69 #include "vcn_v1_0.h" 70 #include "vcn_v2_0.h" 71 #include "jpeg_v2_0.h" 72 #include "vcn_v2_5.h" 73 #include "jpeg_v2_5.h" 74 #include "smuio_v9_0.h" 75 #include "smuio_v11_0.h" 76 #include "dce_virtual.h" 77 #include "mxgpu_ai.h" 78 #include "amdgpu_smu.h" 79 #include "amdgpu_ras.h" 80 #include "amdgpu_xgmi.h" 81 #include <uapi/linux/kfd_ioctl.h> 82 83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 87 88 /* Vega, Raven, Arcturus */ 89 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = 90 { 91 { 92 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 93 .max_width = 4096, 94 .max_height = 2304, 95 .max_pixels_per_frame = 4096 * 2304, 96 .max_level = 0, 97 }, 98 { 99 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 100 .max_width = 4096, 101 .max_height = 2304, 102 .max_pixels_per_frame = 4096 * 2304, 103 .max_level = 0, 104 }, 105 }; 106 107 static const struct amdgpu_video_codecs vega_video_codecs_encode = 108 { 109 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), 110 .codec_array = vega_video_codecs_encode_array, 111 }; 112 113 /* Vega */ 114 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = 115 { 116 { 117 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 118 .max_width = 4096, 119 .max_height = 4096, 120 .max_pixels_per_frame = 4096 * 4096, 121 .max_level = 3, 122 }, 123 { 124 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 125 .max_width = 4096, 126 .max_height = 4096, 127 .max_pixels_per_frame = 4096 * 4096, 128 .max_level = 5, 129 }, 130 { 131 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 132 .max_width = 4096, 133 .max_height = 4096, 134 .max_pixels_per_frame = 4096 * 4096, 135 .max_level = 52, 136 }, 137 { 138 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 139 .max_width = 4096, 140 .max_height = 4096, 141 .max_pixels_per_frame = 4096 * 4096, 142 .max_level = 4, 143 }, 144 { 145 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 146 .max_width = 4096, 147 .max_height = 4096, 148 .max_pixels_per_frame = 4096 * 4096, 149 .max_level = 186, 150 }, 151 { 152 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 153 .max_width = 4096, 154 .max_height = 4096, 155 .max_pixels_per_frame = 4096 * 4096, 156 .max_level = 0, 157 }, 158 }; 159 160 static const struct amdgpu_video_codecs vega_video_codecs_decode = 161 { 162 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), 163 .codec_array = vega_video_codecs_decode_array, 164 }; 165 166 /* Raven */ 167 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = 168 { 169 { 170 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 171 .max_width = 4096, 172 .max_height = 4096, 173 .max_pixels_per_frame = 4096 * 4096, 174 .max_level = 3, 175 }, 176 { 177 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 178 .max_width = 4096, 179 .max_height = 4096, 180 .max_pixels_per_frame = 4096 * 4096, 181 .max_level = 5, 182 }, 183 { 184 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 185 .max_width = 4096, 186 .max_height = 4096, 187 .max_pixels_per_frame = 4096 * 4096, 188 .max_level = 52, 189 }, 190 { 191 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 192 .max_width = 4096, 193 .max_height = 4096, 194 .max_pixels_per_frame = 4096 * 4096, 195 .max_level = 4, 196 }, 197 { 198 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 199 .max_width = 4096, 200 .max_height = 4096, 201 .max_pixels_per_frame = 4096 * 4096, 202 .max_level = 186, 203 }, 204 { 205 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 206 .max_width = 4096, 207 .max_height = 4096, 208 .max_pixels_per_frame = 4096 * 4096, 209 .max_level = 0, 210 }, 211 { 212 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 213 .max_width = 4096, 214 .max_height = 4096, 215 .max_pixels_per_frame = 4096 * 4096, 216 .max_level = 0, 217 }, 218 }; 219 220 static const struct amdgpu_video_codecs rv_video_codecs_decode = 221 { 222 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), 223 .codec_array = rv_video_codecs_decode_array, 224 }; 225 226 /* Renoir, Arcturus */ 227 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = 228 { 229 { 230 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 231 .max_width = 4096, 232 .max_height = 4096, 233 .max_pixels_per_frame = 4096 * 4096, 234 .max_level = 3, 235 }, 236 { 237 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 238 .max_width = 4096, 239 .max_height = 4096, 240 .max_pixels_per_frame = 4096 * 4096, 241 .max_level = 5, 242 }, 243 { 244 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 245 .max_width = 4096, 246 .max_height = 4096, 247 .max_pixels_per_frame = 4096 * 4096, 248 .max_level = 52, 249 }, 250 { 251 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 252 .max_width = 4096, 253 .max_height = 4096, 254 .max_pixels_per_frame = 4096 * 4096, 255 .max_level = 4, 256 }, 257 { 258 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 259 .max_width = 8192, 260 .max_height = 4352, 261 .max_pixels_per_frame = 4096 * 4096, 262 .max_level = 186, 263 }, 264 { 265 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 266 .max_width = 4096, 267 .max_height = 4096, 268 .max_pixels_per_frame = 4096 * 4096, 269 .max_level = 0, 270 }, 271 { 272 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 273 .max_width = 8192, 274 .max_height = 4352, 275 .max_pixels_per_frame = 4096 * 4096, 276 .max_level = 0, 277 }, 278 }; 279 280 static const struct amdgpu_video_codecs rn_video_codecs_decode = 281 { 282 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), 283 .codec_array = rn_video_codecs_decode_array, 284 }; 285 286 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, 287 const struct amdgpu_video_codecs **codecs) 288 { 289 switch (adev->asic_type) { 290 case CHIP_VEGA20: 291 case CHIP_VEGA10: 292 case CHIP_VEGA12: 293 if (encode) 294 *codecs = &vega_video_codecs_encode; 295 else 296 *codecs = &vega_video_codecs_decode; 297 return 0; 298 case CHIP_RAVEN: 299 if (encode) 300 *codecs = &vega_video_codecs_encode; 301 else 302 *codecs = &rv_video_codecs_decode; 303 return 0; 304 case CHIP_ARCTURUS: 305 case CHIP_RENOIR: 306 if (encode) 307 *codecs = &vega_video_codecs_encode; 308 else 309 *codecs = &rn_video_codecs_decode; 310 return 0; 311 default: 312 return -EINVAL; 313 } 314 } 315 316 /* 317 * Indirect registers accessor 318 */ 319 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 320 { 321 unsigned long address, data; 322 address = adev->nbio.funcs->get_pcie_index_offset(adev); 323 data = adev->nbio.funcs->get_pcie_data_offset(adev); 324 325 return amdgpu_device_indirect_rreg(adev, address, data, reg); 326 } 327 328 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 329 { 330 unsigned long address, data; 331 332 address = adev->nbio.funcs->get_pcie_index_offset(adev); 333 data = adev->nbio.funcs->get_pcie_data_offset(adev); 334 335 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 336 } 337 338 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 339 { 340 unsigned long address, data; 341 address = adev->nbio.funcs->get_pcie_index_offset(adev); 342 data = adev->nbio.funcs->get_pcie_data_offset(adev); 343 344 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 345 } 346 347 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 348 { 349 unsigned long address, data; 350 351 address = adev->nbio.funcs->get_pcie_index_offset(adev); 352 data = adev->nbio.funcs->get_pcie_data_offset(adev); 353 354 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 355 } 356 357 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 358 { 359 unsigned long flags, address, data; 360 u32 r; 361 362 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 363 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 364 365 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 366 WREG32(address, ((reg) & 0x1ff)); 367 r = RREG32(data); 368 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 369 return r; 370 } 371 372 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 373 { 374 unsigned long flags, address, data; 375 376 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 377 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 378 379 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 380 WREG32(address, ((reg) & 0x1ff)); 381 WREG32(data, (v)); 382 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 383 } 384 385 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 386 { 387 unsigned long flags, address, data; 388 u32 r; 389 390 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 391 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 392 393 spin_lock_irqsave(&adev->didt_idx_lock, flags); 394 WREG32(address, (reg)); 395 r = RREG32(data); 396 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 397 return r; 398 } 399 400 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 401 { 402 unsigned long flags, address, data; 403 404 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 405 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 406 407 spin_lock_irqsave(&adev->didt_idx_lock, flags); 408 WREG32(address, (reg)); 409 WREG32(data, (v)); 410 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 411 } 412 413 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 414 { 415 unsigned long flags; 416 u32 r; 417 418 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 419 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 420 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 421 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 422 return r; 423 } 424 425 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 426 { 427 unsigned long flags; 428 429 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 430 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 431 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 432 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 433 } 434 435 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 436 { 437 unsigned long flags; 438 u32 r; 439 440 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 441 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 442 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 443 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 444 return r; 445 } 446 447 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 448 { 449 unsigned long flags; 450 451 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 452 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 453 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 454 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 455 } 456 457 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 458 { 459 return adev->nbio.funcs->get_memsize(adev); 460 } 461 462 static u32 soc15_get_xclk(struct amdgpu_device *adev) 463 { 464 u32 reference_clock = adev->clock.spll.reference_freq; 465 466 if (adev->asic_type == CHIP_RENOIR) 467 return 10000; 468 if (adev->asic_type == CHIP_RAVEN) 469 return reference_clock / 4; 470 471 return reference_clock; 472 } 473 474 475 void soc15_grbm_select(struct amdgpu_device *adev, 476 u32 me, u32 pipe, u32 queue, u32 vmid) 477 { 478 u32 grbm_gfx_cntl = 0; 479 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 480 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 481 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 482 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 483 484 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 485 } 486 487 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 488 { 489 /* todo */ 490 } 491 492 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 493 { 494 /* todo */ 495 return false; 496 } 497 498 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 499 u8 *bios, u32 length_bytes) 500 { 501 u32 *dw_ptr; 502 u32 i, length_dw; 503 uint32_t rom_index_offset; 504 uint32_t rom_data_offset; 505 506 if (bios == NULL) 507 return false; 508 if (length_bytes == 0) 509 return false; 510 /* APU vbios image is part of sbios image */ 511 if (adev->flags & AMD_IS_APU) 512 return false; 513 514 dw_ptr = (u32 *)bios; 515 length_dw = ALIGN(length_bytes, 4) / 4; 516 517 rom_index_offset = 518 adev->smuio.funcs->get_rom_index_offset(adev); 519 rom_data_offset = 520 adev->smuio.funcs->get_rom_data_offset(adev); 521 522 /* set rom index to 0 */ 523 WREG32(rom_index_offset, 0); 524 /* read out the rom data */ 525 for (i = 0; i < length_dw; i++) 526 dw_ptr[i] = RREG32(rom_data_offset); 527 528 return true; 529 } 530 531 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 532 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 533 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 534 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 535 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 536 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 537 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 538 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 539 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 540 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 541 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 542 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 543 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 544 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 545 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 546 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 547 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 548 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 549 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 550 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 551 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 552 }; 553 554 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 555 u32 sh_num, u32 reg_offset) 556 { 557 uint32_t val; 558 559 mutex_lock(&adev->grbm_idx_mutex); 560 if (se_num != 0xffffffff || sh_num != 0xffffffff) 561 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 562 563 val = RREG32(reg_offset); 564 565 if (se_num != 0xffffffff || sh_num != 0xffffffff) 566 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 567 mutex_unlock(&adev->grbm_idx_mutex); 568 return val; 569 } 570 571 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 572 bool indexed, u32 se_num, 573 u32 sh_num, u32 reg_offset) 574 { 575 if (indexed) { 576 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 577 } else { 578 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 579 return adev->gfx.config.gb_addr_config; 580 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 581 return adev->gfx.config.db_debug2; 582 return RREG32(reg_offset); 583 } 584 } 585 586 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 587 u32 sh_num, u32 reg_offset, u32 *value) 588 { 589 uint32_t i; 590 struct soc15_allowed_register_entry *en; 591 592 *value = 0; 593 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 594 en = &soc15_allowed_read_registers[i]; 595 if (adev->reg_offset[en->hwip][en->inst] && 596 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 597 + en->reg_offset)) 598 continue; 599 600 *value = soc15_get_register_value(adev, 601 soc15_allowed_read_registers[i].grbm_indexed, 602 se_num, sh_num, reg_offset); 603 return 0; 604 } 605 return -EINVAL; 606 } 607 608 609 /** 610 * soc15_program_register_sequence - program an array of registers. 611 * 612 * @adev: amdgpu_device pointer 613 * @regs: pointer to the register array 614 * @array_size: size of the register array 615 * 616 * Programs an array or registers with and and or masks. 617 * This is a helper for setting golden registers. 618 */ 619 620 void soc15_program_register_sequence(struct amdgpu_device *adev, 621 const struct soc15_reg_golden *regs, 622 const u32 array_size) 623 { 624 const struct soc15_reg_golden *entry; 625 u32 tmp, reg; 626 int i; 627 628 for (i = 0; i < array_size; ++i) { 629 entry = ®s[i]; 630 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 631 632 if (entry->and_mask == 0xffffffff) { 633 tmp = entry->or_mask; 634 } else { 635 tmp = RREG32(reg); 636 tmp &= ~(entry->and_mask); 637 tmp |= (entry->or_mask & entry->and_mask); 638 } 639 640 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 641 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 642 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 643 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 644 WREG32_RLC(reg, tmp); 645 else 646 WREG32(reg, tmp); 647 648 } 649 650 } 651 652 static int soc15_asic_mode1_reset(struct amdgpu_device *adev) 653 { 654 u32 i; 655 int ret = 0; 656 657 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 658 659 dev_info(adev->dev, "GPU mode1 reset\n"); 660 661 /* disable BM */ 662 pci_clear_master(adev->pdev); 663 664 amdgpu_device_cache_pci_state(adev->pdev); 665 666 ret = psp_gpu_reset(adev); 667 if (ret) 668 dev_err(adev->dev, "GPU mode1 reset failed\n"); 669 670 amdgpu_device_load_pci_state(adev->pdev); 671 672 /* wait for asic to come out of reset */ 673 for (i = 0; i < adev->usec_timeout; i++) { 674 u32 memsize = adev->nbio.funcs->get_memsize(adev); 675 676 if (memsize != 0xffffffff) 677 break; 678 udelay(1); 679 } 680 681 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 682 683 return ret; 684 } 685 686 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 687 { 688 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 689 int ret = 0; 690 691 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 692 if (ras && ras->supported) 693 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 694 695 ret = amdgpu_dpm_baco_reset(adev); 696 if (ret) 697 return ret; 698 699 /* re-enable doorbell interrupt after BACO exit */ 700 if (ras && ras->supported) 701 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 702 703 return 0; 704 } 705 706 static enum amd_reset_method 707 soc15_asic_reset_method(struct amdgpu_device *adev) 708 { 709 bool baco_reset = false; 710 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 711 712 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 713 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 714 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 715 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 716 return amdgpu_reset_method; 717 718 if (amdgpu_reset_method != -1) 719 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 720 amdgpu_reset_method); 721 722 switch (adev->asic_type) { 723 case CHIP_RAVEN: 724 case CHIP_RENOIR: 725 return AMD_RESET_METHOD_MODE2; 726 case CHIP_VEGA10: 727 case CHIP_VEGA12: 728 case CHIP_ARCTURUS: 729 baco_reset = amdgpu_dpm_is_baco_supported(adev); 730 break; 731 case CHIP_VEGA20: 732 if (adev->psp.sos_fw_version >= 0x80067) 733 baco_reset = amdgpu_dpm_is_baco_supported(adev); 734 735 /* 736 * 1. PMFW version > 0x284300: all cases use baco 737 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 738 */ 739 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400) 740 baco_reset = false; 741 break; 742 default: 743 break; 744 } 745 746 if (baco_reset) 747 return AMD_RESET_METHOD_BACO; 748 else 749 return AMD_RESET_METHOD_MODE1; 750 } 751 752 static int soc15_asic_reset(struct amdgpu_device *adev) 753 { 754 /* original raven doesn't have full asic reset */ 755 if ((adev->apu_flags & AMD_APU_IS_RAVEN) && 756 !(adev->apu_flags & AMD_APU_IS_RAVEN2)) 757 return 0; 758 759 switch (soc15_asic_reset_method(adev)) { 760 case AMD_RESET_METHOD_PCI: 761 dev_info(adev->dev, "PCI reset\n"); 762 return amdgpu_device_pci_reset(adev); 763 case AMD_RESET_METHOD_BACO: 764 dev_info(adev->dev, "BACO reset\n"); 765 return soc15_asic_baco_reset(adev); 766 case AMD_RESET_METHOD_MODE2: 767 dev_info(adev->dev, "MODE2 reset\n"); 768 return amdgpu_dpm_mode2_reset(adev); 769 default: 770 dev_info(adev->dev, "MODE1 reset\n"); 771 return soc15_asic_mode1_reset(adev); 772 } 773 } 774 775 static bool soc15_supports_baco(struct amdgpu_device *adev) 776 { 777 switch (adev->asic_type) { 778 case CHIP_VEGA10: 779 case CHIP_VEGA12: 780 case CHIP_ARCTURUS: 781 return amdgpu_dpm_is_baco_supported(adev); 782 case CHIP_VEGA20: 783 if (adev->psp.sos_fw_version >= 0x80067) 784 return amdgpu_dpm_is_baco_supported(adev); 785 return false; 786 default: 787 return false; 788 } 789 } 790 791 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 792 u32 cntl_reg, u32 status_reg) 793 { 794 return 0; 795 }*/ 796 797 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 798 { 799 /*int r; 800 801 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 802 if (r) 803 return r; 804 805 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 806 */ 807 return 0; 808 } 809 810 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 811 { 812 /* todo */ 813 814 return 0; 815 } 816 817 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 818 { 819 if (pci_is_root_bus(adev->pdev->bus)) 820 return; 821 822 if (amdgpu_pcie_gen2 == 0) 823 return; 824 825 if (adev->flags & AMD_IS_APU) 826 return; 827 828 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 829 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 830 return; 831 832 /* todo */ 833 } 834 835 static void soc15_program_aspm(struct amdgpu_device *adev) 836 { 837 838 if (amdgpu_aspm == 0) 839 return; 840 841 /* todo */ 842 } 843 844 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 845 bool enable) 846 { 847 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 848 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 849 } 850 851 static const struct amdgpu_ip_block_version vega10_common_ip_block = 852 { 853 .type = AMD_IP_BLOCK_TYPE_COMMON, 854 .major = 2, 855 .minor = 0, 856 .rev = 0, 857 .funcs = &soc15_common_ip_funcs, 858 }; 859 860 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 861 { 862 return adev->nbio.funcs->get_rev_id(adev); 863 } 864 865 static void soc15_reg_base_init(struct amdgpu_device *adev) 866 { 867 int r; 868 869 /* Set IP register base before any HW register access */ 870 switch (adev->asic_type) { 871 case CHIP_VEGA10: 872 case CHIP_VEGA12: 873 case CHIP_RAVEN: 874 vega10_reg_base_init(adev); 875 break; 876 case CHIP_RENOIR: 877 /* It's safe to do ip discovery here for Renior, 878 * it doesn't support SRIOV. */ 879 if (amdgpu_discovery) { 880 r = amdgpu_discovery_reg_base_init(adev); 881 if (r == 0) 882 break; 883 DRM_WARN("failed to init reg base from ip discovery table, " 884 "fallback to legacy init method\n"); 885 } 886 vega10_reg_base_init(adev); 887 break; 888 case CHIP_VEGA20: 889 vega20_reg_base_init(adev); 890 break; 891 case CHIP_ARCTURUS: 892 arct_reg_base_init(adev); 893 break; 894 default: 895 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); 896 break; 897 } 898 } 899 900 void soc15_set_virt_ops(struct amdgpu_device *adev) 901 { 902 adev->virt.ops = &xgpu_ai_virt_ops; 903 904 /* init soc15 reg base early enough so we can 905 * request request full access for sriov before 906 * set_ip_blocks. */ 907 soc15_reg_base_init(adev); 908 } 909 910 int soc15_set_ip_blocks(struct amdgpu_device *adev) 911 { 912 /* for bare metal case */ 913 if (!amdgpu_sriov_vf(adev)) 914 soc15_reg_base_init(adev); 915 916 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 917 adev->gmc.xgmi.supported = true; 918 919 if (adev->flags & AMD_IS_APU) { 920 adev->nbio.funcs = &nbio_v7_0_funcs; 921 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 922 } else if (adev->asic_type == CHIP_VEGA20 || 923 adev->asic_type == CHIP_ARCTURUS) { 924 adev->nbio.funcs = &nbio_v7_4_funcs; 925 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 926 } else { 927 adev->nbio.funcs = &nbio_v6_1_funcs; 928 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 929 } 930 adev->hdp.funcs = &hdp_v4_0_funcs; 931 932 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 933 adev->df.funcs = &df_v3_6_funcs; 934 else 935 adev->df.funcs = &df_v1_7_funcs; 936 937 if (adev->asic_type == CHIP_VEGA20 || 938 adev->asic_type == CHIP_ARCTURUS) 939 adev->smuio.funcs = &smuio_v11_0_funcs; 940 else 941 adev->smuio.funcs = &smuio_v9_0_funcs; 942 943 adev->rev_id = soc15_get_rev_id(adev); 944 945 switch (adev->asic_type) { 946 case CHIP_VEGA10: 947 case CHIP_VEGA12: 948 case CHIP_VEGA20: 949 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 950 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 951 952 /* For Vega10 SR-IOV, PSP need to be initialized before IH */ 953 if (amdgpu_sriov_vf(adev)) { 954 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 955 if (adev->asic_type == CHIP_VEGA20) 956 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 957 else 958 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 959 } 960 if (adev->asic_type == CHIP_VEGA20) 961 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 962 else 963 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 964 } else { 965 if (adev->asic_type == CHIP_VEGA20) 966 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 967 else 968 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 969 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 970 if (adev->asic_type == CHIP_VEGA20) 971 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 972 else 973 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 974 } 975 } 976 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 977 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 978 if (is_support_sw_smu(adev)) { 979 if (!amdgpu_sriov_vf(adev)) 980 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 981 } else { 982 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 983 } 984 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 985 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 986 #if defined(CONFIG_DRM_AMD_DC) 987 else if (amdgpu_device_has_dc_support(adev)) 988 amdgpu_device_ip_block_add(adev, &dm_ip_block); 989 #endif 990 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { 991 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 992 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 993 } 994 break; 995 case CHIP_RAVEN: 996 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 997 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 998 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 999 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 1000 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 1001 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1002 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1003 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 1004 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 1005 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 1006 #if defined(CONFIG_DRM_AMD_DC) 1007 else if (amdgpu_device_has_dc_support(adev)) 1008 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1009 #endif 1010 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 1011 break; 1012 case CHIP_ARCTURUS: 1013 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1014 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1015 1016 if (amdgpu_sriov_vf(adev)) { 1017 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 1018 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1019 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1020 } else { 1021 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 1022 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 1023 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 1024 } 1025 1026 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 1027 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 1028 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1029 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1030 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 1031 1032 if (amdgpu_sriov_vf(adev)) { 1033 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 1034 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 1035 } else { 1036 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 1037 } 1038 if (!amdgpu_sriov_vf(adev)) 1039 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 1040 break; 1041 case CHIP_RENOIR: 1042 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 1043 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 1044 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 1045 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 1046 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 1047 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 1048 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 1049 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 1050 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 1051 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 1052 #if defined(CONFIG_DRM_AMD_DC) 1053 else if (amdgpu_device_has_dc_support(adev)) 1054 amdgpu_device_ip_block_add(adev, &dm_ip_block); 1055 #endif 1056 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 1057 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 1058 break; 1059 default: 1060 return -EINVAL; 1061 } 1062 1063 return 0; 1064 } 1065 1066 static bool soc15_need_full_reset(struct amdgpu_device *adev) 1067 { 1068 /* change this when we implement soft reset */ 1069 return true; 1070 } 1071 1072 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 1073 uint64_t *count1) 1074 { 1075 uint32_t perfctr = 0; 1076 uint64_t cnt0_of, cnt1_of; 1077 int tmp; 1078 1079 /* This reports 0 on APUs, so return to avoid writing/reading registers 1080 * that may or may not be different from their GPU counterparts 1081 */ 1082 if (adev->flags & AMD_IS_APU) 1083 return; 1084 1085 /* Set the 2 events that we wish to watch, defined above */ 1086 /* Reg 40 is # received msgs */ 1087 /* Reg 104 is # of posted requests sent */ 1088 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 1089 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 1090 1091 /* Write to enable desired perf counters */ 1092 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 1093 /* Zero out and enable the perf counters 1094 * Write 0x5: 1095 * Bit 0 = Start all counters(1) 1096 * Bit 2 = Global counter reset enable(1) 1097 */ 1098 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 1099 1100 msleep(1000); 1101 1102 /* Load the shadow and disable the perf counters 1103 * Write 0x2: 1104 * Bit 0 = Stop counters(0) 1105 * Bit 1 = Load the shadow counters(1) 1106 */ 1107 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 1108 1109 /* Read register values to get any >32bit overflow */ 1110 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 1111 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 1112 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 1113 1114 /* Get the values and add the overflow */ 1115 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 1116 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 1117 } 1118 1119 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 1120 uint64_t *count1) 1121 { 1122 uint32_t perfctr = 0; 1123 uint64_t cnt0_of, cnt1_of; 1124 int tmp; 1125 1126 /* This reports 0 on APUs, so return to avoid writing/reading registers 1127 * that may or may not be different from their GPU counterparts 1128 */ 1129 if (adev->flags & AMD_IS_APU) 1130 return; 1131 1132 /* Set the 2 events that we wish to watch, defined above */ 1133 /* Reg 40 is # received msgs */ 1134 /* Reg 108 is # of posted requests sent on VG20 */ 1135 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 1136 EVENT0_SEL, 40); 1137 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 1138 EVENT1_SEL, 108); 1139 1140 /* Write to enable desired perf counters */ 1141 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 1142 /* Zero out and enable the perf counters 1143 * Write 0x5: 1144 * Bit 0 = Start all counters(1) 1145 * Bit 2 = Global counter reset enable(1) 1146 */ 1147 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 1148 1149 msleep(1000); 1150 1151 /* Load the shadow and disable the perf counters 1152 * Write 0x2: 1153 * Bit 0 = Stop counters(0) 1154 * Bit 1 = Load the shadow counters(1) 1155 */ 1156 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 1157 1158 /* Read register values to get any >32bit overflow */ 1159 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 1160 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 1161 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 1162 1163 /* Get the values and add the overflow */ 1164 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 1165 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 1166 } 1167 1168 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 1169 { 1170 u32 sol_reg; 1171 1172 /* Just return false for soc15 GPUs. Reset does not seem to 1173 * be necessary. 1174 */ 1175 if (!amdgpu_passthrough(adev)) 1176 return false; 1177 1178 if (adev->flags & AMD_IS_APU) 1179 return false; 1180 1181 /* Check sOS sign of life register to confirm sys driver and sOS 1182 * are already been loaded. 1183 */ 1184 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 1185 if (sol_reg) 1186 return true; 1187 1188 return false; 1189 } 1190 1191 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 1192 { 1193 uint64_t nak_r, nak_g; 1194 1195 /* Get the number of NAKs received and generated */ 1196 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 1197 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 1198 1199 /* Add the total number of NAKs, i.e the number of replays */ 1200 return (nak_r + nak_g); 1201 } 1202 1203 static void soc15_pre_asic_init(struct amdgpu_device *adev) 1204 { 1205 gmc_v9_0_restore_registers(adev); 1206 } 1207 1208 static const struct amdgpu_asic_funcs soc15_asic_funcs = 1209 { 1210 .read_disabled_bios = &soc15_read_disabled_bios, 1211 .read_bios_from_rom = &soc15_read_bios_from_rom, 1212 .read_register = &soc15_read_register, 1213 .reset = &soc15_asic_reset, 1214 .reset_method = &soc15_asic_reset_method, 1215 .set_vga_state = &soc15_vga_set_state, 1216 .get_xclk = &soc15_get_xclk, 1217 .set_uvd_clocks = &soc15_set_uvd_clocks, 1218 .set_vce_clocks = &soc15_set_vce_clocks, 1219 .get_config_memsize = &soc15_get_config_memsize, 1220 .need_full_reset = &soc15_need_full_reset, 1221 .init_doorbell_index = &vega10_doorbell_index_init, 1222 .get_pcie_usage = &soc15_get_pcie_usage, 1223 .need_reset_on_init = &soc15_need_reset_on_init, 1224 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1225 .supports_baco = &soc15_supports_baco, 1226 .pre_asic_init = &soc15_pre_asic_init, 1227 .query_video_codecs = &soc15_query_video_codecs, 1228 }; 1229 1230 static const struct amdgpu_asic_funcs vega20_asic_funcs = 1231 { 1232 .read_disabled_bios = &soc15_read_disabled_bios, 1233 .read_bios_from_rom = &soc15_read_bios_from_rom, 1234 .read_register = &soc15_read_register, 1235 .reset = &soc15_asic_reset, 1236 .reset_method = &soc15_asic_reset_method, 1237 .set_vga_state = &soc15_vga_set_state, 1238 .get_xclk = &soc15_get_xclk, 1239 .set_uvd_clocks = &soc15_set_uvd_clocks, 1240 .set_vce_clocks = &soc15_set_vce_clocks, 1241 .get_config_memsize = &soc15_get_config_memsize, 1242 .need_full_reset = &soc15_need_full_reset, 1243 .init_doorbell_index = &vega20_doorbell_index_init, 1244 .get_pcie_usage = &vega20_get_pcie_usage, 1245 .need_reset_on_init = &soc15_need_reset_on_init, 1246 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1247 .supports_baco = &soc15_supports_baco, 1248 .pre_asic_init = &soc15_pre_asic_init, 1249 .query_video_codecs = &soc15_query_video_codecs, 1250 }; 1251 1252 static int soc15_common_early_init(void *handle) 1253 { 1254 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 1255 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1256 1257 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 1258 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 1259 adev->smc_rreg = NULL; 1260 adev->smc_wreg = NULL; 1261 adev->pcie_rreg = &soc15_pcie_rreg; 1262 adev->pcie_wreg = &soc15_pcie_wreg; 1263 adev->pcie_rreg64 = &soc15_pcie_rreg64; 1264 adev->pcie_wreg64 = &soc15_pcie_wreg64; 1265 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 1266 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 1267 adev->didt_rreg = &soc15_didt_rreg; 1268 adev->didt_wreg = &soc15_didt_wreg; 1269 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 1270 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 1271 adev->se_cac_rreg = &soc15_se_cac_rreg; 1272 adev->se_cac_wreg = &soc15_se_cac_wreg; 1273 1274 1275 adev->external_rev_id = 0xFF; 1276 switch (adev->asic_type) { 1277 case CHIP_VEGA10: 1278 adev->asic_funcs = &soc15_asic_funcs; 1279 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1280 AMD_CG_SUPPORT_GFX_MGLS | 1281 AMD_CG_SUPPORT_GFX_RLC_LS | 1282 AMD_CG_SUPPORT_GFX_CP_LS | 1283 AMD_CG_SUPPORT_GFX_3D_CGCG | 1284 AMD_CG_SUPPORT_GFX_3D_CGLS | 1285 AMD_CG_SUPPORT_GFX_CGCG | 1286 AMD_CG_SUPPORT_GFX_CGLS | 1287 AMD_CG_SUPPORT_BIF_MGCG | 1288 AMD_CG_SUPPORT_BIF_LS | 1289 AMD_CG_SUPPORT_HDP_LS | 1290 AMD_CG_SUPPORT_DRM_MGCG | 1291 AMD_CG_SUPPORT_DRM_LS | 1292 AMD_CG_SUPPORT_ROM_MGCG | 1293 AMD_CG_SUPPORT_DF_MGCG | 1294 AMD_CG_SUPPORT_SDMA_MGCG | 1295 AMD_CG_SUPPORT_SDMA_LS | 1296 AMD_CG_SUPPORT_MC_MGCG | 1297 AMD_CG_SUPPORT_MC_LS; 1298 adev->pg_flags = 0; 1299 adev->external_rev_id = 0x1; 1300 break; 1301 case CHIP_VEGA12: 1302 adev->asic_funcs = &soc15_asic_funcs; 1303 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1304 AMD_CG_SUPPORT_GFX_MGLS | 1305 AMD_CG_SUPPORT_GFX_CGCG | 1306 AMD_CG_SUPPORT_GFX_CGLS | 1307 AMD_CG_SUPPORT_GFX_3D_CGCG | 1308 AMD_CG_SUPPORT_GFX_3D_CGLS | 1309 AMD_CG_SUPPORT_GFX_CP_LS | 1310 AMD_CG_SUPPORT_MC_LS | 1311 AMD_CG_SUPPORT_MC_MGCG | 1312 AMD_CG_SUPPORT_SDMA_MGCG | 1313 AMD_CG_SUPPORT_SDMA_LS | 1314 AMD_CG_SUPPORT_BIF_MGCG | 1315 AMD_CG_SUPPORT_BIF_LS | 1316 AMD_CG_SUPPORT_HDP_MGCG | 1317 AMD_CG_SUPPORT_HDP_LS | 1318 AMD_CG_SUPPORT_ROM_MGCG | 1319 AMD_CG_SUPPORT_VCE_MGCG | 1320 AMD_CG_SUPPORT_UVD_MGCG; 1321 adev->pg_flags = 0; 1322 adev->external_rev_id = adev->rev_id + 0x14; 1323 break; 1324 case CHIP_VEGA20: 1325 adev->asic_funcs = &vega20_asic_funcs; 1326 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1327 AMD_CG_SUPPORT_GFX_MGLS | 1328 AMD_CG_SUPPORT_GFX_CGCG | 1329 AMD_CG_SUPPORT_GFX_CGLS | 1330 AMD_CG_SUPPORT_GFX_3D_CGCG | 1331 AMD_CG_SUPPORT_GFX_3D_CGLS | 1332 AMD_CG_SUPPORT_GFX_CP_LS | 1333 AMD_CG_SUPPORT_MC_LS | 1334 AMD_CG_SUPPORT_MC_MGCG | 1335 AMD_CG_SUPPORT_SDMA_MGCG | 1336 AMD_CG_SUPPORT_SDMA_LS | 1337 AMD_CG_SUPPORT_BIF_MGCG | 1338 AMD_CG_SUPPORT_BIF_LS | 1339 AMD_CG_SUPPORT_HDP_MGCG | 1340 AMD_CG_SUPPORT_HDP_LS | 1341 AMD_CG_SUPPORT_ROM_MGCG | 1342 AMD_CG_SUPPORT_VCE_MGCG | 1343 AMD_CG_SUPPORT_UVD_MGCG; 1344 adev->pg_flags = 0; 1345 adev->external_rev_id = adev->rev_id + 0x28; 1346 break; 1347 case CHIP_RAVEN: 1348 adev->asic_funcs = &soc15_asic_funcs; 1349 if (adev->pdev->device == 0x15dd) 1350 adev->apu_flags |= AMD_APU_IS_RAVEN; 1351 if (adev->pdev->device == 0x15d8) 1352 adev->apu_flags |= AMD_APU_IS_PICASSO; 1353 if (adev->rev_id >= 0x8) 1354 adev->apu_flags |= AMD_APU_IS_RAVEN2; 1355 1356 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1357 adev->external_rev_id = adev->rev_id + 0x79; 1358 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1359 adev->external_rev_id = adev->rev_id + 0x41; 1360 else if (adev->rev_id == 1) 1361 adev->external_rev_id = adev->rev_id + 0x20; 1362 else 1363 adev->external_rev_id = adev->rev_id + 0x01; 1364 1365 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1366 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1367 AMD_CG_SUPPORT_GFX_MGLS | 1368 AMD_CG_SUPPORT_GFX_CP_LS | 1369 AMD_CG_SUPPORT_GFX_3D_CGCG | 1370 AMD_CG_SUPPORT_GFX_3D_CGLS | 1371 AMD_CG_SUPPORT_GFX_CGCG | 1372 AMD_CG_SUPPORT_GFX_CGLS | 1373 AMD_CG_SUPPORT_BIF_LS | 1374 AMD_CG_SUPPORT_HDP_LS | 1375 AMD_CG_SUPPORT_MC_MGCG | 1376 AMD_CG_SUPPORT_MC_LS | 1377 AMD_CG_SUPPORT_SDMA_MGCG | 1378 AMD_CG_SUPPORT_SDMA_LS | 1379 AMD_CG_SUPPORT_VCN_MGCG; 1380 1381 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1382 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { 1383 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1384 AMD_CG_SUPPORT_GFX_MGLS | 1385 AMD_CG_SUPPORT_GFX_CP_LS | 1386 AMD_CG_SUPPORT_GFX_3D_CGCG | 1387 AMD_CG_SUPPORT_GFX_3D_CGLS | 1388 AMD_CG_SUPPORT_GFX_CGCG | 1389 AMD_CG_SUPPORT_GFX_CGLS | 1390 AMD_CG_SUPPORT_BIF_LS | 1391 AMD_CG_SUPPORT_HDP_LS | 1392 AMD_CG_SUPPORT_MC_MGCG | 1393 AMD_CG_SUPPORT_MC_LS | 1394 AMD_CG_SUPPORT_SDMA_MGCG | 1395 AMD_CG_SUPPORT_SDMA_LS; 1396 1397 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1398 AMD_PG_SUPPORT_MMHUB | 1399 AMD_PG_SUPPORT_VCN; 1400 } else { 1401 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1402 AMD_CG_SUPPORT_GFX_MGLS | 1403 AMD_CG_SUPPORT_GFX_RLC_LS | 1404 AMD_CG_SUPPORT_GFX_CP_LS | 1405 AMD_CG_SUPPORT_GFX_3D_CGCG | 1406 AMD_CG_SUPPORT_GFX_3D_CGLS | 1407 AMD_CG_SUPPORT_GFX_CGCG | 1408 AMD_CG_SUPPORT_GFX_CGLS | 1409 AMD_CG_SUPPORT_BIF_MGCG | 1410 AMD_CG_SUPPORT_BIF_LS | 1411 AMD_CG_SUPPORT_HDP_MGCG | 1412 AMD_CG_SUPPORT_HDP_LS | 1413 AMD_CG_SUPPORT_DRM_MGCG | 1414 AMD_CG_SUPPORT_DRM_LS | 1415 AMD_CG_SUPPORT_MC_MGCG | 1416 AMD_CG_SUPPORT_MC_LS | 1417 AMD_CG_SUPPORT_SDMA_MGCG | 1418 AMD_CG_SUPPORT_SDMA_LS | 1419 AMD_CG_SUPPORT_VCN_MGCG; 1420 1421 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1422 } 1423 break; 1424 case CHIP_ARCTURUS: 1425 adev->asic_funcs = &vega20_asic_funcs; 1426 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1427 AMD_CG_SUPPORT_GFX_MGLS | 1428 AMD_CG_SUPPORT_GFX_CGCG | 1429 AMD_CG_SUPPORT_GFX_CGLS | 1430 AMD_CG_SUPPORT_GFX_CP_LS | 1431 AMD_CG_SUPPORT_HDP_MGCG | 1432 AMD_CG_SUPPORT_HDP_LS | 1433 AMD_CG_SUPPORT_SDMA_MGCG | 1434 AMD_CG_SUPPORT_SDMA_LS | 1435 AMD_CG_SUPPORT_MC_MGCG | 1436 AMD_CG_SUPPORT_MC_LS | 1437 AMD_CG_SUPPORT_IH_CG | 1438 AMD_CG_SUPPORT_VCN_MGCG | 1439 AMD_CG_SUPPORT_JPEG_MGCG; 1440 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; 1441 adev->external_rev_id = adev->rev_id + 0x32; 1442 break; 1443 case CHIP_RENOIR: 1444 adev->asic_funcs = &soc15_asic_funcs; 1445 if ((adev->pdev->device == 0x1636) || 1446 (adev->pdev->device == 0x164c)) 1447 adev->apu_flags |= AMD_APU_IS_RENOIR; 1448 else 1449 adev->apu_flags |= AMD_APU_IS_GREEN_SARDINE; 1450 1451 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1452 adev->external_rev_id = adev->rev_id + 0x91; 1453 else 1454 adev->external_rev_id = adev->rev_id + 0xa1; 1455 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1456 AMD_CG_SUPPORT_GFX_MGLS | 1457 AMD_CG_SUPPORT_GFX_3D_CGCG | 1458 AMD_CG_SUPPORT_GFX_3D_CGLS | 1459 AMD_CG_SUPPORT_GFX_CGCG | 1460 AMD_CG_SUPPORT_GFX_CGLS | 1461 AMD_CG_SUPPORT_GFX_CP_LS | 1462 AMD_CG_SUPPORT_MC_MGCG | 1463 AMD_CG_SUPPORT_MC_LS | 1464 AMD_CG_SUPPORT_SDMA_MGCG | 1465 AMD_CG_SUPPORT_SDMA_LS | 1466 AMD_CG_SUPPORT_BIF_LS | 1467 AMD_CG_SUPPORT_HDP_LS | 1468 AMD_CG_SUPPORT_VCN_MGCG | 1469 AMD_CG_SUPPORT_JPEG_MGCG | 1470 AMD_CG_SUPPORT_IH_CG | 1471 AMD_CG_SUPPORT_ATHUB_LS | 1472 AMD_CG_SUPPORT_ATHUB_MGCG | 1473 AMD_CG_SUPPORT_DF_MGCG; 1474 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1475 AMD_PG_SUPPORT_VCN | 1476 AMD_PG_SUPPORT_JPEG | 1477 AMD_PG_SUPPORT_VCN_DPG; 1478 break; 1479 default: 1480 /* FIXME: not supported yet */ 1481 return -EINVAL; 1482 } 1483 1484 if (amdgpu_sriov_vf(adev)) { 1485 amdgpu_virt_init_setting(adev); 1486 xgpu_ai_mailbox_set_irq_funcs(adev); 1487 } 1488 1489 return 0; 1490 } 1491 1492 static int soc15_common_late_init(void *handle) 1493 { 1494 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1495 int r = 0; 1496 1497 if (amdgpu_sriov_vf(adev)) 1498 xgpu_ai_mailbox_get_irq(adev); 1499 1500 if (adev->hdp.funcs->reset_ras_error_count) 1501 adev->hdp.funcs->reset_ras_error_count(adev); 1502 1503 if (adev->nbio.funcs->ras_late_init) 1504 r = adev->nbio.funcs->ras_late_init(adev); 1505 1506 return r; 1507 } 1508 1509 static int soc15_common_sw_init(void *handle) 1510 { 1511 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1512 1513 if (amdgpu_sriov_vf(adev)) 1514 xgpu_ai_mailbox_add_irq_id(adev); 1515 1516 adev->df.funcs->sw_init(adev); 1517 1518 return 0; 1519 } 1520 1521 static int soc15_common_sw_fini(void *handle) 1522 { 1523 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1524 1525 amdgpu_nbio_ras_fini(adev); 1526 adev->df.funcs->sw_fini(adev); 1527 return 0; 1528 } 1529 1530 static void soc15_doorbell_range_init(struct amdgpu_device *adev) 1531 { 1532 int i; 1533 struct amdgpu_ring *ring; 1534 1535 /* sdma/ih doorbell range are programed by hypervisor */ 1536 if (!amdgpu_sriov_vf(adev)) { 1537 for (i = 0; i < adev->sdma.num_instances; i++) { 1538 ring = &adev->sdma.instance[i].ring; 1539 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1540 ring->use_doorbell, ring->doorbell_index, 1541 adev->doorbell_index.sdma_doorbell_range); 1542 } 1543 1544 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 1545 adev->irq.ih.doorbell_index); 1546 } 1547 } 1548 1549 static int soc15_common_hw_init(void *handle) 1550 { 1551 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1552 1553 /* enable pcie gen2/3 link */ 1554 soc15_pcie_gen3_enable(adev); 1555 /* enable aspm */ 1556 soc15_program_aspm(adev); 1557 /* setup nbio registers */ 1558 adev->nbio.funcs->init_registers(adev); 1559 /* remap HDP registers to a hole in mmio space, 1560 * for the purpose of expose those registers 1561 * to process space 1562 */ 1563 if (adev->nbio.funcs->remap_hdp_registers) 1564 adev->nbio.funcs->remap_hdp_registers(adev); 1565 1566 /* enable the doorbell aperture */ 1567 soc15_enable_doorbell_aperture(adev, true); 1568 /* HW doorbell routing policy: doorbell writing not 1569 * in SDMA/IH/MM/ACV range will be routed to CP. So 1570 * we need to init SDMA/IH/MM/ACV doorbell range prior 1571 * to CP ip block init and ring test. 1572 */ 1573 soc15_doorbell_range_init(adev); 1574 1575 return 0; 1576 } 1577 1578 static int soc15_common_hw_fini(void *handle) 1579 { 1580 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1581 1582 /* disable the doorbell aperture */ 1583 soc15_enable_doorbell_aperture(adev, false); 1584 if (amdgpu_sriov_vf(adev)) 1585 xgpu_ai_mailbox_put_irq(adev); 1586 1587 if (adev->nbio.ras_if && 1588 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1589 if (adev->nbio.funcs->init_ras_controller_interrupt) 1590 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1591 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) 1592 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1593 } 1594 1595 return 0; 1596 } 1597 1598 static int soc15_common_suspend(void *handle) 1599 { 1600 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1601 1602 return soc15_common_hw_fini(adev); 1603 } 1604 1605 static int soc15_common_resume(void *handle) 1606 { 1607 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1608 1609 return soc15_common_hw_init(adev); 1610 } 1611 1612 static bool soc15_common_is_idle(void *handle) 1613 { 1614 return true; 1615 } 1616 1617 static int soc15_common_wait_for_idle(void *handle) 1618 { 1619 return 0; 1620 } 1621 1622 static int soc15_common_soft_reset(void *handle) 1623 { 1624 return 0; 1625 } 1626 1627 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1628 { 1629 uint32_t def, data; 1630 1631 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1632 1633 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1634 data &= ~(0x01000000 | 1635 0x02000000 | 1636 0x04000000 | 1637 0x08000000 | 1638 0x10000000 | 1639 0x20000000 | 1640 0x40000000 | 1641 0x80000000); 1642 else 1643 data |= (0x01000000 | 1644 0x02000000 | 1645 0x04000000 | 1646 0x08000000 | 1647 0x10000000 | 1648 0x20000000 | 1649 0x40000000 | 1650 0x80000000); 1651 1652 if (def != data) 1653 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1654 } 1655 1656 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1657 { 1658 uint32_t def, data; 1659 1660 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1661 1662 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1663 data |= 1; 1664 else 1665 data &= ~1; 1666 1667 if (def != data) 1668 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1669 } 1670 1671 static int soc15_common_set_clockgating_state(void *handle, 1672 enum amd_clockgating_state state) 1673 { 1674 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1675 1676 if (amdgpu_sriov_vf(adev)) 1677 return 0; 1678 1679 switch (adev->asic_type) { 1680 case CHIP_VEGA10: 1681 case CHIP_VEGA12: 1682 case CHIP_VEGA20: 1683 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1684 state == AMD_CG_STATE_GATE); 1685 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1686 state == AMD_CG_STATE_GATE); 1687 adev->hdp.funcs->update_clock_gating(adev, 1688 state == AMD_CG_STATE_GATE); 1689 soc15_update_drm_clock_gating(adev, 1690 state == AMD_CG_STATE_GATE); 1691 soc15_update_drm_light_sleep(adev, 1692 state == AMD_CG_STATE_GATE); 1693 adev->smuio.funcs->update_rom_clock_gating(adev, 1694 state == AMD_CG_STATE_GATE); 1695 adev->df.funcs->update_medium_grain_clock_gating(adev, 1696 state == AMD_CG_STATE_GATE); 1697 break; 1698 case CHIP_RAVEN: 1699 case CHIP_RENOIR: 1700 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1701 state == AMD_CG_STATE_GATE); 1702 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1703 state == AMD_CG_STATE_GATE); 1704 adev->hdp.funcs->update_clock_gating(adev, 1705 state == AMD_CG_STATE_GATE); 1706 soc15_update_drm_clock_gating(adev, 1707 state == AMD_CG_STATE_GATE); 1708 soc15_update_drm_light_sleep(adev, 1709 state == AMD_CG_STATE_GATE); 1710 break; 1711 case CHIP_ARCTURUS: 1712 adev->hdp.funcs->update_clock_gating(adev, 1713 state == AMD_CG_STATE_GATE); 1714 break; 1715 default: 1716 break; 1717 } 1718 return 0; 1719 } 1720 1721 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1722 { 1723 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1724 int data; 1725 1726 if (amdgpu_sriov_vf(adev)) 1727 *flags = 0; 1728 1729 adev->nbio.funcs->get_clockgating_state(adev, flags); 1730 1731 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1732 1733 /* AMD_CG_SUPPORT_DRM_MGCG */ 1734 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1735 if (!(data & 0x01000000)) 1736 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1737 1738 /* AMD_CG_SUPPORT_DRM_LS */ 1739 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1740 if (data & 0x1) 1741 *flags |= AMD_CG_SUPPORT_DRM_LS; 1742 1743 /* AMD_CG_SUPPORT_ROM_MGCG */ 1744 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1745 1746 adev->df.funcs->get_clockgating_state(adev, flags); 1747 } 1748 1749 static int soc15_common_set_powergating_state(void *handle, 1750 enum amd_powergating_state state) 1751 { 1752 /* todo */ 1753 return 0; 1754 } 1755 1756 const struct amd_ip_funcs soc15_common_ip_funcs = { 1757 .name = "soc15_common", 1758 .early_init = soc15_common_early_init, 1759 .late_init = soc15_common_late_init, 1760 .sw_init = soc15_common_sw_init, 1761 .sw_fini = soc15_common_sw_fini, 1762 .hw_init = soc15_common_hw_init, 1763 .hw_fini = soc15_common_hw_fini, 1764 .suspend = soc15_common_suspend, 1765 .resume = soc15_common_resume, 1766 .is_idle = soc15_common_is_idle, 1767 .wait_for_idle = soc15_common_wait_for_idle, 1768 .soft_reset = soc15_common_soft_reset, 1769 .set_clockgating_state = soc15_common_set_clockgating_state, 1770 .set_powergating_state = soc15_common_set_powergating_state, 1771 .get_clockgating_state= soc15_common_get_clockgating_state, 1772 }; 1773