1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "atom.h" 36 #include "amd_pcie.h" 37 38 #include "uvd/uvd_7_0_offset.h" 39 #include "gc/gc_9_0_offset.h" 40 #include "gc/gc_9_0_sh_mask.h" 41 #include "sdma0/sdma0_4_0_offset.h" 42 #include "sdma1/sdma1_4_0_offset.h" 43 #include "hdp/hdp_4_0_offset.h" 44 #include "hdp/hdp_4_0_sh_mask.h" 45 #include "smuio/smuio_9_0_offset.h" 46 #include "smuio/smuio_9_0_sh_mask.h" 47 #include "nbio/nbio_7_0_default.h" 48 #include "nbio/nbio_7_0_offset.h" 49 #include "nbio/nbio_7_0_sh_mask.h" 50 #include "nbio/nbio_7_0_smn.h" 51 #include "mp/mp_9_0_offset.h" 52 53 #include "soc15.h" 54 #include "soc15_common.h" 55 #include "gfx_v9_0.h" 56 #include "gmc_v9_0.h" 57 #include "gfxhub_v1_0.h" 58 #include "mmhub_v1_0.h" 59 #include "df_v1_7.h" 60 #include "df_v3_6.h" 61 #include "nbio_v6_1.h" 62 #include "nbio_v7_0.h" 63 #include "nbio_v7_4.h" 64 #include "vega10_ih.h" 65 #include "sdma_v4_0.h" 66 #include "uvd_v7_0.h" 67 #include "vce_v4_0.h" 68 #include "vcn_v1_0.h" 69 #include "vcn_v2_0.h" 70 #include "jpeg_v2_0.h" 71 #include "vcn_v2_5.h" 72 #include "jpeg_v2_5.h" 73 #include "dce_virtual.h" 74 #include "mxgpu_ai.h" 75 #include "amdgpu_smu.h" 76 #include "amdgpu_ras.h" 77 #include "amdgpu_xgmi.h" 78 #include <uapi/linux/kfd_ioctl.h> 79 80 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 81 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 82 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 84 85 /* for Vega20 register name change */ 86 #define mmHDP_MEM_POWER_CTRL 0x00d4 87 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 89 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 91 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 92 93 /* for Vega20/arcturus regiter offset change */ 94 #define mmROM_INDEX_VG20 0x00e4 95 #define mmROM_INDEX_VG20_BASE_IDX 0 96 #define mmROM_DATA_VG20 0x00e5 97 #define mmROM_DATA_VG20_BASE_IDX 0 98 99 /* 100 * Indirect registers accessor 101 */ 102 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 103 { 104 unsigned long flags, address, data; 105 u32 r; 106 address = adev->nbio.funcs->get_pcie_index_offset(adev); 107 data = adev->nbio.funcs->get_pcie_data_offset(adev); 108 109 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 110 WREG32(address, reg); 111 (void)RREG32(address); 112 r = RREG32(data); 113 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 114 return r; 115 } 116 117 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 118 { 119 unsigned long flags, address, data; 120 121 address = adev->nbio.funcs->get_pcie_index_offset(adev); 122 data = adev->nbio.funcs->get_pcie_data_offset(adev); 123 124 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 125 WREG32(address, reg); 126 (void)RREG32(address); 127 WREG32(data, v); 128 (void)RREG32(data); 129 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 130 } 131 132 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 133 { 134 unsigned long flags, address, data; 135 u64 r; 136 address = adev->nbio.funcs->get_pcie_index_offset(adev); 137 data = adev->nbio.funcs->get_pcie_data_offset(adev); 138 139 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 140 /* read low 32 bit */ 141 WREG32(address, reg); 142 (void)RREG32(address); 143 r = RREG32(data); 144 145 /* read high 32 bit*/ 146 WREG32(address, reg + 4); 147 (void)RREG32(address); 148 r |= ((u64)RREG32(data) << 32); 149 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 150 return r; 151 } 152 153 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 154 { 155 unsigned long flags, address, data; 156 157 address = adev->nbio.funcs->get_pcie_index_offset(adev); 158 data = adev->nbio.funcs->get_pcie_data_offset(adev); 159 160 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 161 /* write low 32 bit */ 162 WREG32(address, reg); 163 (void)RREG32(address); 164 WREG32(data, (u32)(v & 0xffffffffULL)); 165 (void)RREG32(data); 166 167 /* write high 32 bit */ 168 WREG32(address, reg + 4); 169 (void)RREG32(address); 170 WREG32(data, (u32)(v >> 32)); 171 (void)RREG32(data); 172 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 173 } 174 175 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 176 { 177 unsigned long flags, address, data; 178 u32 r; 179 180 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 181 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 182 183 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 184 WREG32(address, ((reg) & 0x1ff)); 185 r = RREG32(data); 186 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 187 return r; 188 } 189 190 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 191 { 192 unsigned long flags, address, data; 193 194 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 195 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 196 197 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 198 WREG32(address, ((reg) & 0x1ff)); 199 WREG32(data, (v)); 200 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 201 } 202 203 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 204 { 205 unsigned long flags, address, data; 206 u32 r; 207 208 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 209 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 210 211 spin_lock_irqsave(&adev->didt_idx_lock, flags); 212 WREG32(address, (reg)); 213 r = RREG32(data); 214 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 215 return r; 216 } 217 218 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 219 { 220 unsigned long flags, address, data; 221 222 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 223 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 224 225 spin_lock_irqsave(&adev->didt_idx_lock, flags); 226 WREG32(address, (reg)); 227 WREG32(data, (v)); 228 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 229 } 230 231 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 232 { 233 unsigned long flags; 234 u32 r; 235 236 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 237 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 238 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 239 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 240 return r; 241 } 242 243 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 244 { 245 unsigned long flags; 246 247 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 248 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 249 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 250 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 251 } 252 253 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 254 { 255 unsigned long flags; 256 u32 r; 257 258 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 259 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 260 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 261 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 262 return r; 263 } 264 265 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 266 { 267 unsigned long flags; 268 269 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 270 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 271 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 272 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 273 } 274 275 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 276 { 277 return adev->nbio.funcs->get_memsize(adev); 278 } 279 280 static u32 soc15_get_xclk(struct amdgpu_device *adev) 281 { 282 u32 reference_clock = adev->clock.spll.reference_freq; 283 284 if (adev->asic_type == CHIP_RAVEN) 285 return reference_clock / 4; 286 287 return reference_clock; 288 } 289 290 291 void soc15_grbm_select(struct amdgpu_device *adev, 292 u32 me, u32 pipe, u32 queue, u32 vmid) 293 { 294 u32 grbm_gfx_cntl = 0; 295 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 296 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 297 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 298 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 299 300 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 301 } 302 303 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 304 { 305 /* todo */ 306 } 307 308 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 309 { 310 /* todo */ 311 return false; 312 } 313 314 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 315 u8 *bios, u32 length_bytes) 316 { 317 u32 *dw_ptr; 318 u32 i, length_dw; 319 uint32_t rom_index_offset; 320 uint32_t rom_data_offset; 321 322 if (bios == NULL) 323 return false; 324 if (length_bytes == 0) 325 return false; 326 /* APU vbios image is part of sbios image */ 327 if (adev->flags & AMD_IS_APU) 328 return false; 329 330 dw_ptr = (u32 *)bios; 331 length_dw = ALIGN(length_bytes, 4) / 4; 332 333 switch (adev->asic_type) { 334 case CHIP_VEGA20: 335 case CHIP_ARCTURUS: 336 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20); 337 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20); 338 break; 339 default: 340 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX); 341 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA); 342 break; 343 } 344 345 /* set rom index to 0 */ 346 WREG32(rom_index_offset, 0); 347 /* read out the rom data */ 348 for (i = 0; i < length_dw; i++) 349 dw_ptr[i] = RREG32(rom_data_offset); 350 351 return true; 352 } 353 354 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 355 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 356 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 357 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 358 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 359 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 360 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 361 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 362 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 363 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 364 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 365 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 366 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 367 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 368 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 369 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 370 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 371 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 372 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 373 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 374 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 375 }; 376 377 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 378 u32 sh_num, u32 reg_offset) 379 { 380 uint32_t val; 381 382 mutex_lock(&adev->grbm_idx_mutex); 383 if (se_num != 0xffffffff || sh_num != 0xffffffff) 384 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 385 386 val = RREG32(reg_offset); 387 388 if (se_num != 0xffffffff || sh_num != 0xffffffff) 389 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 390 mutex_unlock(&adev->grbm_idx_mutex); 391 return val; 392 } 393 394 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 395 bool indexed, u32 se_num, 396 u32 sh_num, u32 reg_offset) 397 { 398 if (indexed) { 399 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 400 } else { 401 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 402 return adev->gfx.config.gb_addr_config; 403 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 404 return adev->gfx.config.db_debug2; 405 return RREG32(reg_offset); 406 } 407 } 408 409 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 410 u32 sh_num, u32 reg_offset, u32 *value) 411 { 412 uint32_t i; 413 struct soc15_allowed_register_entry *en; 414 415 *value = 0; 416 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 417 en = &soc15_allowed_read_registers[i]; 418 if (adev->reg_offset[en->hwip][en->inst] && 419 reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 420 + en->reg_offset)) 421 continue; 422 423 *value = soc15_get_register_value(adev, 424 soc15_allowed_read_registers[i].grbm_indexed, 425 se_num, sh_num, reg_offset); 426 return 0; 427 } 428 return -EINVAL; 429 } 430 431 432 /** 433 * soc15_program_register_sequence - program an array of registers. 434 * 435 * @adev: amdgpu_device pointer 436 * @regs: pointer to the register array 437 * @array_size: size of the register array 438 * 439 * Programs an array or registers with and and or masks. 440 * This is a helper for setting golden registers. 441 */ 442 443 void soc15_program_register_sequence(struct amdgpu_device *adev, 444 const struct soc15_reg_golden *regs, 445 const u32 array_size) 446 { 447 const struct soc15_reg_golden *entry; 448 u32 tmp, reg; 449 int i; 450 451 for (i = 0; i < array_size; ++i) { 452 entry = ®s[i]; 453 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 454 455 if (entry->and_mask == 0xffffffff) { 456 tmp = entry->or_mask; 457 } else { 458 tmp = RREG32(reg); 459 tmp &= ~(entry->and_mask); 460 tmp |= (entry->or_mask & entry->and_mask); 461 } 462 463 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 464 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 465 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 466 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 467 WREG32_RLC(reg, tmp); 468 else 469 WREG32(reg, tmp); 470 471 } 472 473 } 474 475 static int soc15_asic_mode1_reset(struct amdgpu_device *adev) 476 { 477 u32 i; 478 int ret = 0; 479 480 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 481 482 dev_info(adev->dev, "GPU mode1 reset\n"); 483 484 /* disable BM */ 485 pci_clear_master(adev->pdev); 486 487 pci_save_state(adev->pdev); 488 489 ret = psp_gpu_reset(adev); 490 if (ret) 491 dev_err(adev->dev, "GPU mode1 reset failed\n"); 492 493 pci_restore_state(adev->pdev); 494 495 /* wait for asic to come out of reset */ 496 for (i = 0; i < adev->usec_timeout; i++) { 497 u32 memsize = adev->nbio.funcs->get_memsize(adev); 498 499 if (memsize != 0xffffffff) 500 break; 501 udelay(1); 502 } 503 504 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 505 506 return ret; 507 } 508 509 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 510 { 511 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 512 int ret = 0; 513 514 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 515 if (ras && ras->supported) 516 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 517 518 ret = amdgpu_dpm_baco_reset(adev); 519 if (ret) 520 return ret; 521 522 /* re-enable doorbell interrupt after BACO exit */ 523 if (ras && ras->supported) 524 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 525 526 return 0; 527 } 528 529 static enum amd_reset_method 530 soc15_asic_reset_method(struct amdgpu_device *adev) 531 { 532 bool baco_reset = false; 533 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 534 535 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 536 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 537 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 538 return amdgpu_reset_method; 539 540 if (amdgpu_reset_method != -1) 541 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 542 amdgpu_reset_method); 543 544 switch (adev->asic_type) { 545 case CHIP_RAVEN: 546 case CHIP_RENOIR: 547 return AMD_RESET_METHOD_MODE2; 548 case CHIP_VEGA10: 549 case CHIP_VEGA12: 550 case CHIP_ARCTURUS: 551 baco_reset = amdgpu_dpm_is_baco_supported(adev); 552 break; 553 case CHIP_VEGA20: 554 if (adev->psp.sos_fw_version >= 0x80067) 555 baco_reset = amdgpu_dpm_is_baco_supported(adev); 556 557 /* 558 * 1. PMFW version > 0x284300: all cases use baco 559 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 560 */ 561 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400) 562 baco_reset = false; 563 break; 564 default: 565 break; 566 } 567 568 if (baco_reset) 569 return AMD_RESET_METHOD_BACO; 570 else 571 return AMD_RESET_METHOD_MODE1; 572 } 573 574 static int soc15_asic_reset(struct amdgpu_device *adev) 575 { 576 /* original raven doesn't have full asic reset */ 577 if ((adev->apu_flags & AMD_APU_IS_RAVEN) && 578 !(adev->apu_flags & AMD_APU_IS_RAVEN2)) 579 return 0; 580 581 switch (soc15_asic_reset_method(adev)) { 582 case AMD_RESET_METHOD_BACO: 583 dev_info(adev->dev, "BACO reset\n"); 584 return soc15_asic_baco_reset(adev); 585 case AMD_RESET_METHOD_MODE2: 586 dev_info(adev->dev, "MODE2 reset\n"); 587 return amdgpu_dpm_mode2_reset(adev); 588 default: 589 dev_info(adev->dev, "MODE1 reset\n"); 590 return soc15_asic_mode1_reset(adev); 591 } 592 } 593 594 static bool soc15_supports_baco(struct amdgpu_device *adev) 595 { 596 switch (adev->asic_type) { 597 case CHIP_VEGA10: 598 case CHIP_VEGA12: 599 case CHIP_ARCTURUS: 600 return amdgpu_dpm_is_baco_supported(adev); 601 case CHIP_VEGA20: 602 if (adev->psp.sos_fw_version >= 0x80067) 603 return amdgpu_dpm_is_baco_supported(adev); 604 return false; 605 default: 606 return false; 607 } 608 } 609 610 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 611 u32 cntl_reg, u32 status_reg) 612 { 613 return 0; 614 }*/ 615 616 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 617 { 618 /*int r; 619 620 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 621 if (r) 622 return r; 623 624 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 625 */ 626 return 0; 627 } 628 629 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 630 { 631 /* todo */ 632 633 return 0; 634 } 635 636 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 637 { 638 if (pci_is_root_bus(adev->pdev->bus)) 639 return; 640 641 if (amdgpu_pcie_gen2 == 0) 642 return; 643 644 if (adev->flags & AMD_IS_APU) 645 return; 646 647 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 648 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 649 return; 650 651 /* todo */ 652 } 653 654 static void soc15_program_aspm(struct amdgpu_device *adev) 655 { 656 657 if (amdgpu_aspm == 0) 658 return; 659 660 /* todo */ 661 } 662 663 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 664 bool enable) 665 { 666 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 667 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 668 } 669 670 static const struct amdgpu_ip_block_version vega10_common_ip_block = 671 { 672 .type = AMD_IP_BLOCK_TYPE_COMMON, 673 .major = 2, 674 .minor = 0, 675 .rev = 0, 676 .funcs = &soc15_common_ip_funcs, 677 }; 678 679 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 680 { 681 return adev->nbio.funcs->get_rev_id(adev); 682 } 683 684 static void soc15_reg_base_init(struct amdgpu_device *adev) 685 { 686 int r; 687 688 /* Set IP register base before any HW register access */ 689 switch (adev->asic_type) { 690 case CHIP_VEGA10: 691 case CHIP_VEGA12: 692 case CHIP_RAVEN: 693 vega10_reg_base_init(adev); 694 break; 695 case CHIP_RENOIR: 696 /* It's safe to do ip discovery here for Renior, 697 * it doesn't support SRIOV. */ 698 if (amdgpu_discovery) { 699 r = amdgpu_discovery_reg_base_init(adev); 700 if (r) { 701 DRM_WARN("failed to init reg base from ip discovery table, " 702 "fallback to legacy init method\n"); 703 vega10_reg_base_init(adev); 704 } 705 } 706 break; 707 case CHIP_VEGA20: 708 vega20_reg_base_init(adev); 709 break; 710 case CHIP_ARCTURUS: 711 arct_reg_base_init(adev); 712 break; 713 default: 714 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); 715 break; 716 } 717 } 718 719 void soc15_set_virt_ops(struct amdgpu_device *adev) 720 { 721 adev->virt.ops = &xgpu_ai_virt_ops; 722 723 /* init soc15 reg base early enough so we can 724 * request request full access for sriov before 725 * set_ip_blocks. */ 726 soc15_reg_base_init(adev); 727 } 728 729 int soc15_set_ip_blocks(struct amdgpu_device *adev) 730 { 731 /* for bare metal case */ 732 if (!amdgpu_sriov_vf(adev)) 733 soc15_reg_base_init(adev); 734 735 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 736 adev->gmc.xgmi.supported = true; 737 738 if (adev->flags & AMD_IS_APU) { 739 adev->nbio.funcs = &nbio_v7_0_funcs; 740 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 741 } else if (adev->asic_type == CHIP_VEGA20 || 742 adev->asic_type == CHIP_ARCTURUS) { 743 adev->nbio.funcs = &nbio_v7_4_funcs; 744 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 745 } else { 746 adev->nbio.funcs = &nbio_v6_1_funcs; 747 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 748 } 749 750 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 751 adev->df.funcs = &df_v3_6_funcs; 752 else 753 adev->df.funcs = &df_v1_7_funcs; 754 755 adev->rev_id = soc15_get_rev_id(adev); 756 757 switch (adev->asic_type) { 758 case CHIP_VEGA10: 759 case CHIP_VEGA12: 760 case CHIP_VEGA20: 761 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 762 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 763 764 /* For Vega10 SR-IOV, PSP need to be initialized before IH */ 765 if (amdgpu_sriov_vf(adev)) { 766 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 767 if (adev->asic_type == CHIP_VEGA20) 768 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 769 else 770 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 771 } 772 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 773 } else { 774 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 775 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 776 if (adev->asic_type == CHIP_VEGA20) 777 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 778 else 779 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 780 } 781 } 782 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 783 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 784 if (is_support_sw_smu(adev)) { 785 if (!amdgpu_sriov_vf(adev)) 786 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 787 } else { 788 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 789 } 790 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 791 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 792 #if defined(CONFIG_DRM_AMD_DC) 793 else if (amdgpu_device_has_dc_support(adev)) 794 amdgpu_device_ip_block_add(adev, &dm_ip_block); 795 #endif 796 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { 797 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 798 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 799 } 800 break; 801 case CHIP_RAVEN: 802 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 803 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 804 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 805 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 806 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 807 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 808 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 809 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 810 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 811 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 812 #if defined(CONFIG_DRM_AMD_DC) 813 else if (amdgpu_device_has_dc_support(adev)) 814 amdgpu_device_ip_block_add(adev, &dm_ip_block); 815 #endif 816 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 817 break; 818 case CHIP_ARCTURUS: 819 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 820 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 821 822 if (amdgpu_sriov_vf(adev)) { 823 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 824 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 825 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 826 } else { 827 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 828 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 829 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 830 } 831 832 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 833 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 834 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 835 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 836 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 837 838 if (amdgpu_sriov_vf(adev)) { 839 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 840 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 841 } else { 842 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 843 } 844 if (!amdgpu_sriov_vf(adev)) 845 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 846 break; 847 case CHIP_RENOIR: 848 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 849 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 850 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 851 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 852 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 853 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 854 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 855 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 856 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 857 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 858 #if defined(CONFIG_DRM_AMD_DC) 859 else if (amdgpu_device_has_dc_support(adev)) 860 amdgpu_device_ip_block_add(adev, &dm_ip_block); 861 #endif 862 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 863 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 864 break; 865 default: 866 return -EINVAL; 867 } 868 869 return 0; 870 } 871 872 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 873 { 874 adev->nbio.funcs->hdp_flush(adev, ring); 875 } 876 877 static void soc15_invalidate_hdp(struct amdgpu_device *adev, 878 struct amdgpu_ring *ring) 879 { 880 if (!ring || !ring->funcs->emit_wreg) 881 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 882 else 883 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 884 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 885 } 886 887 static bool soc15_need_full_reset(struct amdgpu_device *adev) 888 { 889 /* change this when we implement soft reset */ 890 return true; 891 } 892 893 static void vega20_reset_hdp_ras_error_count(struct amdgpu_device *adev) 894 { 895 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP)) 896 return; 897 /*read back hdp ras counter to reset it to 0 */ 898 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); 899 } 900 901 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 902 uint64_t *count1) 903 { 904 uint32_t perfctr = 0; 905 uint64_t cnt0_of, cnt1_of; 906 int tmp; 907 908 /* This reports 0 on APUs, so return to avoid writing/reading registers 909 * that may or may not be different from their GPU counterparts 910 */ 911 if (adev->flags & AMD_IS_APU) 912 return; 913 914 /* Set the 2 events that we wish to watch, defined above */ 915 /* Reg 40 is # received msgs */ 916 /* Reg 104 is # of posted requests sent */ 917 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 918 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 919 920 /* Write to enable desired perf counters */ 921 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 922 /* Zero out and enable the perf counters 923 * Write 0x5: 924 * Bit 0 = Start all counters(1) 925 * Bit 2 = Global counter reset enable(1) 926 */ 927 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 928 929 msleep(1000); 930 931 /* Load the shadow and disable the perf counters 932 * Write 0x2: 933 * Bit 0 = Stop counters(0) 934 * Bit 1 = Load the shadow counters(1) 935 */ 936 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 937 938 /* Read register values to get any >32bit overflow */ 939 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 940 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 941 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 942 943 /* Get the values and add the overflow */ 944 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 945 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 946 } 947 948 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 949 uint64_t *count1) 950 { 951 uint32_t perfctr = 0; 952 uint64_t cnt0_of, cnt1_of; 953 int tmp; 954 955 /* This reports 0 on APUs, so return to avoid writing/reading registers 956 * that may or may not be different from their GPU counterparts 957 */ 958 if (adev->flags & AMD_IS_APU) 959 return; 960 961 /* Set the 2 events that we wish to watch, defined above */ 962 /* Reg 40 is # received msgs */ 963 /* Reg 108 is # of posted requests sent on VG20 */ 964 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 965 EVENT0_SEL, 40); 966 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 967 EVENT1_SEL, 108); 968 969 /* Write to enable desired perf counters */ 970 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 971 /* Zero out and enable the perf counters 972 * Write 0x5: 973 * Bit 0 = Start all counters(1) 974 * Bit 2 = Global counter reset enable(1) 975 */ 976 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 977 978 msleep(1000); 979 980 /* Load the shadow and disable the perf counters 981 * Write 0x2: 982 * Bit 0 = Stop counters(0) 983 * Bit 1 = Load the shadow counters(1) 984 */ 985 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 986 987 /* Read register values to get any >32bit overflow */ 988 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 989 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 990 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 991 992 /* Get the values and add the overflow */ 993 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 994 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 995 } 996 997 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 998 { 999 u32 sol_reg; 1000 1001 /* Just return false for soc15 GPUs. Reset does not seem to 1002 * be necessary. 1003 */ 1004 if (!amdgpu_passthrough(adev)) 1005 return false; 1006 1007 if (adev->flags & AMD_IS_APU) 1008 return false; 1009 1010 /* Check sOS sign of life register to confirm sys driver and sOS 1011 * are already been loaded. 1012 */ 1013 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 1014 if (sol_reg) 1015 return true; 1016 1017 return false; 1018 } 1019 1020 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 1021 { 1022 uint64_t nak_r, nak_g; 1023 1024 /* Get the number of NAKs received and generated */ 1025 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 1026 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 1027 1028 /* Add the total number of NAKs, i.e the number of replays */ 1029 return (nak_r + nak_g); 1030 } 1031 1032 static void soc15_pre_asic_init(struct amdgpu_device *adev) 1033 { 1034 gmc_v9_0_restore_registers(adev); 1035 } 1036 1037 static const struct amdgpu_asic_funcs soc15_asic_funcs = 1038 { 1039 .read_disabled_bios = &soc15_read_disabled_bios, 1040 .read_bios_from_rom = &soc15_read_bios_from_rom, 1041 .read_register = &soc15_read_register, 1042 .reset = &soc15_asic_reset, 1043 .reset_method = &soc15_asic_reset_method, 1044 .set_vga_state = &soc15_vga_set_state, 1045 .get_xclk = &soc15_get_xclk, 1046 .set_uvd_clocks = &soc15_set_uvd_clocks, 1047 .set_vce_clocks = &soc15_set_vce_clocks, 1048 .get_config_memsize = &soc15_get_config_memsize, 1049 .flush_hdp = &soc15_flush_hdp, 1050 .invalidate_hdp = &soc15_invalidate_hdp, 1051 .need_full_reset = &soc15_need_full_reset, 1052 .init_doorbell_index = &vega10_doorbell_index_init, 1053 .get_pcie_usage = &soc15_get_pcie_usage, 1054 .need_reset_on_init = &soc15_need_reset_on_init, 1055 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1056 .supports_baco = &soc15_supports_baco, 1057 .pre_asic_init = &soc15_pre_asic_init, 1058 }; 1059 1060 static const struct amdgpu_asic_funcs vega20_asic_funcs = 1061 { 1062 .read_disabled_bios = &soc15_read_disabled_bios, 1063 .read_bios_from_rom = &soc15_read_bios_from_rom, 1064 .read_register = &soc15_read_register, 1065 .reset = &soc15_asic_reset, 1066 .reset_method = &soc15_asic_reset_method, 1067 .set_vga_state = &soc15_vga_set_state, 1068 .get_xclk = &soc15_get_xclk, 1069 .set_uvd_clocks = &soc15_set_uvd_clocks, 1070 .set_vce_clocks = &soc15_set_vce_clocks, 1071 .get_config_memsize = &soc15_get_config_memsize, 1072 .flush_hdp = &soc15_flush_hdp, 1073 .invalidate_hdp = &soc15_invalidate_hdp, 1074 .reset_hdp_ras_error_count = &vega20_reset_hdp_ras_error_count, 1075 .need_full_reset = &soc15_need_full_reset, 1076 .init_doorbell_index = &vega20_doorbell_index_init, 1077 .get_pcie_usage = &vega20_get_pcie_usage, 1078 .need_reset_on_init = &soc15_need_reset_on_init, 1079 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1080 .supports_baco = &soc15_supports_baco, 1081 .pre_asic_init = &soc15_pre_asic_init, 1082 }; 1083 1084 static int soc15_common_early_init(void *handle) 1085 { 1086 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 1087 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1088 1089 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 1090 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 1091 adev->smc_rreg = NULL; 1092 adev->smc_wreg = NULL; 1093 adev->pcie_rreg = &soc15_pcie_rreg; 1094 adev->pcie_wreg = &soc15_pcie_wreg; 1095 adev->pcie_rreg64 = &soc15_pcie_rreg64; 1096 adev->pcie_wreg64 = &soc15_pcie_wreg64; 1097 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 1098 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 1099 adev->didt_rreg = &soc15_didt_rreg; 1100 adev->didt_wreg = &soc15_didt_wreg; 1101 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 1102 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 1103 adev->se_cac_rreg = &soc15_se_cac_rreg; 1104 adev->se_cac_wreg = &soc15_se_cac_wreg; 1105 1106 1107 adev->external_rev_id = 0xFF; 1108 switch (adev->asic_type) { 1109 case CHIP_VEGA10: 1110 adev->asic_funcs = &soc15_asic_funcs; 1111 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1112 AMD_CG_SUPPORT_GFX_MGLS | 1113 AMD_CG_SUPPORT_GFX_RLC_LS | 1114 AMD_CG_SUPPORT_GFX_CP_LS | 1115 AMD_CG_SUPPORT_GFX_3D_CGCG | 1116 AMD_CG_SUPPORT_GFX_3D_CGLS | 1117 AMD_CG_SUPPORT_GFX_CGCG | 1118 AMD_CG_SUPPORT_GFX_CGLS | 1119 AMD_CG_SUPPORT_BIF_MGCG | 1120 AMD_CG_SUPPORT_BIF_LS | 1121 AMD_CG_SUPPORT_HDP_LS | 1122 AMD_CG_SUPPORT_DRM_MGCG | 1123 AMD_CG_SUPPORT_DRM_LS | 1124 AMD_CG_SUPPORT_ROM_MGCG | 1125 AMD_CG_SUPPORT_DF_MGCG | 1126 AMD_CG_SUPPORT_SDMA_MGCG | 1127 AMD_CG_SUPPORT_SDMA_LS | 1128 AMD_CG_SUPPORT_MC_MGCG | 1129 AMD_CG_SUPPORT_MC_LS; 1130 adev->pg_flags = 0; 1131 adev->external_rev_id = 0x1; 1132 break; 1133 case CHIP_VEGA12: 1134 adev->asic_funcs = &soc15_asic_funcs; 1135 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1136 AMD_CG_SUPPORT_GFX_MGLS | 1137 AMD_CG_SUPPORT_GFX_CGCG | 1138 AMD_CG_SUPPORT_GFX_CGLS | 1139 AMD_CG_SUPPORT_GFX_3D_CGCG | 1140 AMD_CG_SUPPORT_GFX_3D_CGLS | 1141 AMD_CG_SUPPORT_GFX_CP_LS | 1142 AMD_CG_SUPPORT_MC_LS | 1143 AMD_CG_SUPPORT_MC_MGCG | 1144 AMD_CG_SUPPORT_SDMA_MGCG | 1145 AMD_CG_SUPPORT_SDMA_LS | 1146 AMD_CG_SUPPORT_BIF_MGCG | 1147 AMD_CG_SUPPORT_BIF_LS | 1148 AMD_CG_SUPPORT_HDP_MGCG | 1149 AMD_CG_SUPPORT_HDP_LS | 1150 AMD_CG_SUPPORT_ROM_MGCG | 1151 AMD_CG_SUPPORT_VCE_MGCG | 1152 AMD_CG_SUPPORT_UVD_MGCG; 1153 adev->pg_flags = 0; 1154 adev->external_rev_id = adev->rev_id + 0x14; 1155 break; 1156 case CHIP_VEGA20: 1157 adev->asic_funcs = &vega20_asic_funcs; 1158 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1159 AMD_CG_SUPPORT_GFX_MGLS | 1160 AMD_CG_SUPPORT_GFX_CGCG | 1161 AMD_CG_SUPPORT_GFX_CGLS | 1162 AMD_CG_SUPPORT_GFX_3D_CGCG | 1163 AMD_CG_SUPPORT_GFX_3D_CGLS | 1164 AMD_CG_SUPPORT_GFX_CP_LS | 1165 AMD_CG_SUPPORT_MC_LS | 1166 AMD_CG_SUPPORT_MC_MGCG | 1167 AMD_CG_SUPPORT_SDMA_MGCG | 1168 AMD_CG_SUPPORT_SDMA_LS | 1169 AMD_CG_SUPPORT_BIF_MGCG | 1170 AMD_CG_SUPPORT_BIF_LS | 1171 AMD_CG_SUPPORT_HDP_MGCG | 1172 AMD_CG_SUPPORT_HDP_LS | 1173 AMD_CG_SUPPORT_ROM_MGCG | 1174 AMD_CG_SUPPORT_VCE_MGCG | 1175 AMD_CG_SUPPORT_UVD_MGCG; 1176 adev->pg_flags = 0; 1177 adev->external_rev_id = adev->rev_id + 0x28; 1178 break; 1179 case CHIP_RAVEN: 1180 adev->asic_funcs = &soc15_asic_funcs; 1181 if (adev->pdev->device == 0x15dd) 1182 adev->apu_flags |= AMD_APU_IS_RAVEN; 1183 if (adev->pdev->device == 0x15d8) 1184 adev->apu_flags |= AMD_APU_IS_PICASSO; 1185 if (adev->rev_id >= 0x8) 1186 adev->apu_flags |= AMD_APU_IS_RAVEN2; 1187 1188 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1189 adev->external_rev_id = adev->rev_id + 0x79; 1190 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1191 adev->external_rev_id = adev->rev_id + 0x41; 1192 else if (adev->rev_id == 1) 1193 adev->external_rev_id = adev->rev_id + 0x20; 1194 else 1195 adev->external_rev_id = adev->rev_id + 0x01; 1196 1197 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1198 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1199 AMD_CG_SUPPORT_GFX_MGLS | 1200 AMD_CG_SUPPORT_GFX_CP_LS | 1201 AMD_CG_SUPPORT_GFX_3D_CGCG | 1202 AMD_CG_SUPPORT_GFX_3D_CGLS | 1203 AMD_CG_SUPPORT_GFX_CGCG | 1204 AMD_CG_SUPPORT_GFX_CGLS | 1205 AMD_CG_SUPPORT_BIF_LS | 1206 AMD_CG_SUPPORT_HDP_LS | 1207 AMD_CG_SUPPORT_ROM_MGCG | 1208 AMD_CG_SUPPORT_MC_MGCG | 1209 AMD_CG_SUPPORT_MC_LS | 1210 AMD_CG_SUPPORT_SDMA_MGCG | 1211 AMD_CG_SUPPORT_SDMA_LS | 1212 AMD_CG_SUPPORT_VCN_MGCG; 1213 1214 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1215 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { 1216 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1217 AMD_CG_SUPPORT_GFX_MGLS | 1218 AMD_CG_SUPPORT_GFX_CP_LS | 1219 AMD_CG_SUPPORT_GFX_3D_CGCG | 1220 AMD_CG_SUPPORT_GFX_3D_CGLS | 1221 AMD_CG_SUPPORT_GFX_CGCG | 1222 AMD_CG_SUPPORT_GFX_CGLS | 1223 AMD_CG_SUPPORT_BIF_LS | 1224 AMD_CG_SUPPORT_HDP_LS | 1225 AMD_CG_SUPPORT_ROM_MGCG | 1226 AMD_CG_SUPPORT_MC_MGCG | 1227 AMD_CG_SUPPORT_MC_LS | 1228 AMD_CG_SUPPORT_SDMA_MGCG | 1229 AMD_CG_SUPPORT_SDMA_LS; 1230 1231 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1232 AMD_PG_SUPPORT_MMHUB | 1233 AMD_PG_SUPPORT_VCN | 1234 AMD_PG_SUPPORT_VCN_DPG; 1235 } else { 1236 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1237 AMD_CG_SUPPORT_GFX_MGLS | 1238 AMD_CG_SUPPORT_GFX_RLC_LS | 1239 AMD_CG_SUPPORT_GFX_CP_LS | 1240 AMD_CG_SUPPORT_GFX_3D_CGCG | 1241 AMD_CG_SUPPORT_GFX_3D_CGLS | 1242 AMD_CG_SUPPORT_GFX_CGCG | 1243 AMD_CG_SUPPORT_GFX_CGLS | 1244 AMD_CG_SUPPORT_BIF_MGCG | 1245 AMD_CG_SUPPORT_BIF_LS | 1246 AMD_CG_SUPPORT_HDP_MGCG | 1247 AMD_CG_SUPPORT_HDP_LS | 1248 AMD_CG_SUPPORT_DRM_MGCG | 1249 AMD_CG_SUPPORT_DRM_LS | 1250 AMD_CG_SUPPORT_ROM_MGCG | 1251 AMD_CG_SUPPORT_MC_MGCG | 1252 AMD_CG_SUPPORT_MC_LS | 1253 AMD_CG_SUPPORT_SDMA_MGCG | 1254 AMD_CG_SUPPORT_SDMA_LS | 1255 AMD_CG_SUPPORT_VCN_MGCG; 1256 1257 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1258 } 1259 break; 1260 case CHIP_ARCTURUS: 1261 adev->asic_funcs = &vega20_asic_funcs; 1262 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1263 AMD_CG_SUPPORT_GFX_MGLS | 1264 AMD_CG_SUPPORT_GFX_CGCG | 1265 AMD_CG_SUPPORT_GFX_CGLS | 1266 AMD_CG_SUPPORT_GFX_CP_LS | 1267 AMD_CG_SUPPORT_HDP_MGCG | 1268 AMD_CG_SUPPORT_HDP_LS | 1269 AMD_CG_SUPPORT_SDMA_MGCG | 1270 AMD_CG_SUPPORT_SDMA_LS | 1271 AMD_CG_SUPPORT_MC_MGCG | 1272 AMD_CG_SUPPORT_MC_LS | 1273 AMD_CG_SUPPORT_IH_CG | 1274 AMD_CG_SUPPORT_VCN_MGCG | 1275 AMD_CG_SUPPORT_JPEG_MGCG; 1276 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; 1277 adev->external_rev_id = adev->rev_id + 0x32; 1278 break; 1279 case CHIP_RENOIR: 1280 adev->asic_funcs = &soc15_asic_funcs; 1281 adev->apu_flags |= AMD_APU_IS_RENOIR; 1282 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1283 AMD_CG_SUPPORT_GFX_MGLS | 1284 AMD_CG_SUPPORT_GFX_3D_CGCG | 1285 AMD_CG_SUPPORT_GFX_3D_CGLS | 1286 AMD_CG_SUPPORT_GFX_CGCG | 1287 AMD_CG_SUPPORT_GFX_CGLS | 1288 AMD_CG_SUPPORT_GFX_CP_LS | 1289 AMD_CG_SUPPORT_MC_MGCG | 1290 AMD_CG_SUPPORT_MC_LS | 1291 AMD_CG_SUPPORT_SDMA_MGCG | 1292 AMD_CG_SUPPORT_SDMA_LS | 1293 AMD_CG_SUPPORT_BIF_LS | 1294 AMD_CG_SUPPORT_HDP_LS | 1295 AMD_CG_SUPPORT_ROM_MGCG | 1296 AMD_CG_SUPPORT_VCN_MGCG | 1297 AMD_CG_SUPPORT_JPEG_MGCG | 1298 AMD_CG_SUPPORT_IH_CG | 1299 AMD_CG_SUPPORT_ATHUB_LS | 1300 AMD_CG_SUPPORT_ATHUB_MGCG | 1301 AMD_CG_SUPPORT_DF_MGCG; 1302 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1303 AMD_PG_SUPPORT_VCN | 1304 AMD_PG_SUPPORT_JPEG | 1305 AMD_PG_SUPPORT_VCN_DPG; 1306 adev->external_rev_id = adev->rev_id + 0x91; 1307 break; 1308 default: 1309 /* FIXME: not supported yet */ 1310 return -EINVAL; 1311 } 1312 1313 if (amdgpu_sriov_vf(adev)) { 1314 amdgpu_virt_init_setting(adev); 1315 xgpu_ai_mailbox_set_irq_funcs(adev); 1316 } 1317 1318 return 0; 1319 } 1320 1321 static int soc15_common_late_init(void *handle) 1322 { 1323 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1324 int r = 0; 1325 1326 if (amdgpu_sriov_vf(adev)) 1327 xgpu_ai_mailbox_get_irq(adev); 1328 1329 if (adev->asic_funcs && 1330 adev->asic_funcs->reset_hdp_ras_error_count) 1331 adev->asic_funcs->reset_hdp_ras_error_count(adev); 1332 1333 if (adev->nbio.funcs->ras_late_init) 1334 r = adev->nbio.funcs->ras_late_init(adev); 1335 1336 return r; 1337 } 1338 1339 static int soc15_common_sw_init(void *handle) 1340 { 1341 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1342 1343 if (amdgpu_sriov_vf(adev)) 1344 xgpu_ai_mailbox_add_irq_id(adev); 1345 1346 adev->df.funcs->sw_init(adev); 1347 1348 return 0; 1349 } 1350 1351 static int soc15_common_sw_fini(void *handle) 1352 { 1353 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1354 1355 amdgpu_nbio_ras_fini(adev); 1356 adev->df.funcs->sw_fini(adev); 1357 return 0; 1358 } 1359 1360 static void soc15_doorbell_range_init(struct amdgpu_device *adev) 1361 { 1362 int i; 1363 struct amdgpu_ring *ring; 1364 1365 /* sdma/ih doorbell range are programed by hypervisor */ 1366 if (!amdgpu_sriov_vf(adev)) { 1367 for (i = 0; i < adev->sdma.num_instances; i++) { 1368 ring = &adev->sdma.instance[i].ring; 1369 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1370 ring->use_doorbell, ring->doorbell_index, 1371 adev->doorbell_index.sdma_doorbell_range); 1372 } 1373 1374 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 1375 adev->irq.ih.doorbell_index); 1376 } 1377 } 1378 1379 static int soc15_common_hw_init(void *handle) 1380 { 1381 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1382 1383 /* enable pcie gen2/3 link */ 1384 soc15_pcie_gen3_enable(adev); 1385 /* enable aspm */ 1386 soc15_program_aspm(adev); 1387 /* setup nbio registers */ 1388 adev->nbio.funcs->init_registers(adev); 1389 /* remap HDP registers to a hole in mmio space, 1390 * for the purpose of expose those registers 1391 * to process space 1392 */ 1393 if (adev->nbio.funcs->remap_hdp_registers) 1394 adev->nbio.funcs->remap_hdp_registers(adev); 1395 1396 /* enable the doorbell aperture */ 1397 soc15_enable_doorbell_aperture(adev, true); 1398 /* HW doorbell routing policy: doorbell writing not 1399 * in SDMA/IH/MM/ACV range will be routed to CP. So 1400 * we need to init SDMA/IH/MM/ACV doorbell range prior 1401 * to CP ip block init and ring test. 1402 */ 1403 soc15_doorbell_range_init(adev); 1404 1405 return 0; 1406 } 1407 1408 static int soc15_common_hw_fini(void *handle) 1409 { 1410 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1411 1412 /* disable the doorbell aperture */ 1413 soc15_enable_doorbell_aperture(adev, false); 1414 if (amdgpu_sriov_vf(adev)) 1415 xgpu_ai_mailbox_put_irq(adev); 1416 1417 if (adev->nbio.ras_if && 1418 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1419 if (adev->nbio.funcs->init_ras_controller_interrupt) 1420 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1421 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) 1422 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1423 } 1424 1425 return 0; 1426 } 1427 1428 static int soc15_common_suspend(void *handle) 1429 { 1430 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1431 1432 return soc15_common_hw_fini(adev); 1433 } 1434 1435 static int soc15_common_resume(void *handle) 1436 { 1437 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1438 1439 return soc15_common_hw_init(adev); 1440 } 1441 1442 static bool soc15_common_is_idle(void *handle) 1443 { 1444 return true; 1445 } 1446 1447 static int soc15_common_wait_for_idle(void *handle) 1448 { 1449 return 0; 1450 } 1451 1452 static int soc15_common_soft_reset(void *handle) 1453 { 1454 return 0; 1455 } 1456 1457 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) 1458 { 1459 uint32_t def, data; 1460 1461 if (adev->asic_type == CHIP_VEGA20 || 1462 adev->asic_type == CHIP_ARCTURUS || 1463 adev->asic_type == CHIP_RENOIR) { 1464 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); 1465 1466 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1467 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1468 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1469 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1470 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; 1471 else 1472 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1473 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1474 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1475 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); 1476 1477 if (def != data) 1478 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); 1479 } else { 1480 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1481 1482 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1483 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1484 else 1485 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1486 1487 if (def != data) 1488 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 1489 } 1490 } 1491 1492 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1493 { 1494 uint32_t def, data; 1495 1496 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1497 1498 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1499 data &= ~(0x01000000 | 1500 0x02000000 | 1501 0x04000000 | 1502 0x08000000 | 1503 0x10000000 | 1504 0x20000000 | 1505 0x40000000 | 1506 0x80000000); 1507 else 1508 data |= (0x01000000 | 1509 0x02000000 | 1510 0x04000000 | 1511 0x08000000 | 1512 0x10000000 | 1513 0x20000000 | 1514 0x40000000 | 1515 0x80000000); 1516 1517 if (def != data) 1518 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1519 } 1520 1521 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1522 { 1523 uint32_t def, data; 1524 1525 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1526 1527 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1528 data |= 1; 1529 else 1530 data &= ~1; 1531 1532 if (def != data) 1533 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1534 } 1535 1536 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1537 bool enable) 1538 { 1539 uint32_t def, data; 1540 1541 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1542 1543 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1544 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1545 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1546 else 1547 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1548 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1549 1550 if (def != data) 1551 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); 1552 } 1553 1554 static int soc15_common_set_clockgating_state(void *handle, 1555 enum amd_clockgating_state state) 1556 { 1557 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1558 1559 if (amdgpu_sriov_vf(adev)) 1560 return 0; 1561 1562 switch (adev->asic_type) { 1563 case CHIP_VEGA10: 1564 case CHIP_VEGA12: 1565 case CHIP_VEGA20: 1566 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1567 state == AMD_CG_STATE_GATE); 1568 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1569 state == AMD_CG_STATE_GATE); 1570 soc15_update_hdp_light_sleep(adev, 1571 state == AMD_CG_STATE_GATE); 1572 soc15_update_drm_clock_gating(adev, 1573 state == AMD_CG_STATE_GATE); 1574 soc15_update_drm_light_sleep(adev, 1575 state == AMD_CG_STATE_GATE); 1576 soc15_update_rom_medium_grain_clock_gating(adev, 1577 state == AMD_CG_STATE_GATE); 1578 adev->df.funcs->update_medium_grain_clock_gating(adev, 1579 state == AMD_CG_STATE_GATE); 1580 break; 1581 case CHIP_RAVEN: 1582 case CHIP_RENOIR: 1583 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1584 state == AMD_CG_STATE_GATE); 1585 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1586 state == AMD_CG_STATE_GATE); 1587 soc15_update_hdp_light_sleep(adev, 1588 state == AMD_CG_STATE_GATE); 1589 soc15_update_drm_clock_gating(adev, 1590 state == AMD_CG_STATE_GATE); 1591 soc15_update_drm_light_sleep(adev, 1592 state == AMD_CG_STATE_GATE); 1593 soc15_update_rom_medium_grain_clock_gating(adev, 1594 state == AMD_CG_STATE_GATE); 1595 break; 1596 case CHIP_ARCTURUS: 1597 soc15_update_hdp_light_sleep(adev, 1598 state == AMD_CG_STATE_GATE); 1599 break; 1600 default: 1601 break; 1602 } 1603 return 0; 1604 } 1605 1606 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1607 { 1608 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1609 int data; 1610 1611 if (amdgpu_sriov_vf(adev)) 1612 *flags = 0; 1613 1614 adev->nbio.funcs->get_clockgating_state(adev, flags); 1615 1616 /* AMD_CG_SUPPORT_HDP_LS */ 1617 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1618 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 1619 *flags |= AMD_CG_SUPPORT_HDP_LS; 1620 1621 /* AMD_CG_SUPPORT_DRM_MGCG */ 1622 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1623 if (!(data & 0x01000000)) 1624 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1625 1626 /* AMD_CG_SUPPORT_DRM_LS */ 1627 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1628 if (data & 0x1) 1629 *flags |= AMD_CG_SUPPORT_DRM_LS; 1630 1631 /* AMD_CG_SUPPORT_ROM_MGCG */ 1632 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1633 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 1634 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 1635 1636 adev->df.funcs->get_clockgating_state(adev, flags); 1637 } 1638 1639 static int soc15_common_set_powergating_state(void *handle, 1640 enum amd_powergating_state state) 1641 { 1642 /* todo */ 1643 return 0; 1644 } 1645 1646 const struct amd_ip_funcs soc15_common_ip_funcs = { 1647 .name = "soc15_common", 1648 .early_init = soc15_common_early_init, 1649 .late_init = soc15_common_late_init, 1650 .sw_init = soc15_common_sw_init, 1651 .sw_fini = soc15_common_sw_fini, 1652 .hw_init = soc15_common_hw_init, 1653 .hw_fini = soc15_common_hw_fini, 1654 .suspend = soc15_common_suspend, 1655 .resume = soc15_common_resume, 1656 .is_idle = soc15_common_is_idle, 1657 .wait_for_idle = soc15_common_wait_for_idle, 1658 .soft_reset = soc15_common_soft_reset, 1659 .set_clockgating_state = soc15_common_set_clockgating_state, 1660 .set_powergating_state = soc15_common_set_powergating_state, 1661 .get_clockgating_state= soc15_common_get_clockgating_state, 1662 }; 1663