1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "uvd/uvd_7_0_offset.h" 41 #include "gc/gc_9_0_offset.h" 42 #include "gc/gc_9_0_sh_mask.h" 43 #include "sdma0/sdma0_4_0_offset.h" 44 #include "sdma1/sdma1_4_0_offset.h" 45 #include "nbio/nbio_7_0_default.h" 46 #include "nbio/nbio_7_0_offset.h" 47 #include "nbio/nbio_7_0_sh_mask.h" 48 #include "nbio/nbio_7_0_smn.h" 49 #include "mp/mp_9_0_offset.h" 50 51 #include "soc15.h" 52 #include "soc15_common.h" 53 #include "gfx_v9_0.h" 54 #include "gmc_v9_0.h" 55 #include "gfxhub_v1_0.h" 56 #include "mmhub_v1_0.h" 57 #include "df_v1_7.h" 58 #include "df_v3_6.h" 59 #include "nbio_v6_1.h" 60 #include "nbio_v7_0.h" 61 #include "nbio_v7_4.h" 62 #include "hdp_v4_0.h" 63 #include "vega10_ih.h" 64 #include "vega20_ih.h" 65 #include "navi10_ih.h" 66 #include "sdma_v4_0.h" 67 #include "uvd_v7_0.h" 68 #include "vce_v4_0.h" 69 #include "vcn_v1_0.h" 70 #include "vcn_v2_0.h" 71 #include "jpeg_v2_0.h" 72 #include "vcn_v2_5.h" 73 #include "jpeg_v2_5.h" 74 #include "smuio_v9_0.h" 75 #include "smuio_v11_0.h" 76 #include "smuio_v13_0.h" 77 #include "amdgpu_vkms.h" 78 #include "mxgpu_ai.h" 79 #include "amdgpu_ras.h" 80 #include "amdgpu_xgmi.h" 81 #include <uapi/linux/kfd_ioctl.h> 82 83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 87 88 static const struct amd_ip_funcs soc15_common_ip_funcs; 89 90 /* Vega, Raven, Arcturus */ 91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = 92 { 93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 94 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 95 }; 96 97 static const struct amdgpu_video_codecs vega_video_codecs_encode = 98 { 99 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), 100 .codec_array = vega_video_codecs_encode_array, 101 }; 102 103 /* Vega */ 104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = 105 { 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 112 }; 113 114 static const struct amdgpu_video_codecs vega_video_codecs_decode = 115 { 116 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), 117 .codec_array = vega_video_codecs_decode_array, 118 }; 119 120 /* Raven */ 121 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = 122 { 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)}, 130 }; 131 132 static const struct amdgpu_video_codecs rv_video_codecs_decode = 133 { 134 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), 135 .codec_array = rv_video_codecs_decode_array, 136 }; 137 138 /* Renoir, Arcturus */ 139 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = 140 { 141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 148 }; 149 150 static const struct amdgpu_video_codecs rn_video_codecs_decode = 151 { 152 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), 153 .codec_array = rn_video_codecs_decode_array, 154 }; 155 156 static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = { 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 162 }; 163 164 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = { 165 .codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array), 166 .codec_array = vcn_4_0_3_video_codecs_decode_array, 167 }; 168 169 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = { 170 .codec_count = 0, 171 .codec_array = NULL, 172 }; 173 174 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, 175 const struct amdgpu_video_codecs **codecs) 176 { 177 if (adev->ip_versions[VCE_HWIP][0]) { 178 switch (adev->ip_versions[VCE_HWIP][0]) { 179 case IP_VERSION(4, 0, 0): 180 case IP_VERSION(4, 1, 0): 181 if (encode) 182 *codecs = &vega_video_codecs_encode; 183 else 184 *codecs = &vega_video_codecs_decode; 185 return 0; 186 default: 187 return -EINVAL; 188 } 189 } else { 190 switch (adev->ip_versions[UVD_HWIP][0]) { 191 case IP_VERSION(1, 0, 0): 192 case IP_VERSION(1, 0, 1): 193 if (encode) 194 *codecs = &vega_video_codecs_encode; 195 else 196 *codecs = &rv_video_codecs_decode; 197 return 0; 198 case IP_VERSION(2, 5, 0): 199 case IP_VERSION(2, 6, 0): 200 case IP_VERSION(2, 2, 0): 201 if (encode) 202 *codecs = &vega_video_codecs_encode; 203 else 204 *codecs = &rn_video_codecs_decode; 205 return 0; 206 case IP_VERSION(4, 0, 3): 207 if (encode) 208 *codecs = &vcn_4_0_3_video_codecs_encode; 209 else 210 *codecs = &vcn_4_0_3_video_codecs_decode; 211 return 0; 212 default: 213 return -EINVAL; 214 } 215 } 216 } 217 218 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 219 { 220 unsigned long flags, address, data; 221 u32 r; 222 223 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 224 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 225 226 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 227 WREG32(address, ((reg) & 0x1ff)); 228 r = RREG32(data); 229 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 230 return r; 231 } 232 233 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 234 { 235 unsigned long flags, address, data; 236 237 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 238 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 239 240 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 241 WREG32(address, ((reg) & 0x1ff)); 242 WREG32(data, (v)); 243 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 244 } 245 246 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 247 { 248 unsigned long flags, address, data; 249 u32 r; 250 251 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 252 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 253 254 spin_lock_irqsave(&adev->didt_idx_lock, flags); 255 WREG32(address, (reg)); 256 r = RREG32(data); 257 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 258 return r; 259 } 260 261 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 262 { 263 unsigned long flags, address, data; 264 265 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 266 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 267 268 spin_lock_irqsave(&adev->didt_idx_lock, flags); 269 WREG32(address, (reg)); 270 WREG32(data, (v)); 271 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 272 } 273 274 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 275 { 276 unsigned long flags; 277 u32 r; 278 279 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 280 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 281 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 282 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 283 return r; 284 } 285 286 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 287 { 288 unsigned long flags; 289 290 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 291 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 292 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 293 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 294 } 295 296 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 297 { 298 unsigned long flags; 299 u32 r; 300 301 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 302 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 303 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 304 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 305 return r; 306 } 307 308 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 309 { 310 unsigned long flags; 311 312 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 313 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 314 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 315 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 316 } 317 318 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 319 { 320 return adev->nbio.funcs->get_memsize(adev); 321 } 322 323 static u32 soc15_get_xclk(struct amdgpu_device *adev) 324 { 325 u32 reference_clock = adev->clock.spll.reference_freq; 326 327 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) || 328 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1) || 329 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) || 330 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1)) 331 return 10000; 332 333 return reference_clock; 334 } 335 336 337 void soc15_grbm_select(struct amdgpu_device *adev, 338 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id) 339 { 340 u32 grbm_gfx_cntl = 0; 341 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 342 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 343 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 344 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 345 346 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 347 } 348 349 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 350 { 351 /* todo */ 352 return false; 353 } 354 355 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 356 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 357 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 358 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 359 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 360 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 361 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 362 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 363 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 364 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 365 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 366 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 367 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 368 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 369 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 370 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 371 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 372 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 373 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 374 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 375 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 376 }; 377 378 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 379 u32 sh_num, u32 reg_offset) 380 { 381 uint32_t val; 382 383 mutex_lock(&adev->grbm_idx_mutex); 384 if (se_num != 0xffffffff || sh_num != 0xffffffff) 385 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 386 387 val = RREG32(reg_offset); 388 389 if (se_num != 0xffffffff || sh_num != 0xffffffff) 390 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 391 mutex_unlock(&adev->grbm_idx_mutex); 392 return val; 393 } 394 395 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 396 bool indexed, u32 se_num, 397 u32 sh_num, u32 reg_offset) 398 { 399 if (indexed) { 400 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 401 } else { 402 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 403 return adev->gfx.config.gb_addr_config; 404 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 405 return adev->gfx.config.db_debug2; 406 return RREG32(reg_offset); 407 } 408 } 409 410 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 411 u32 sh_num, u32 reg_offset, u32 *value) 412 { 413 uint32_t i; 414 struct soc15_allowed_register_entry *en; 415 416 *value = 0; 417 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 418 en = &soc15_allowed_read_registers[i]; 419 if (!adev->reg_offset[en->hwip][en->inst]) 420 continue; 421 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 422 + en->reg_offset)) 423 continue; 424 425 *value = soc15_get_register_value(adev, 426 soc15_allowed_read_registers[i].grbm_indexed, 427 se_num, sh_num, reg_offset); 428 return 0; 429 } 430 return -EINVAL; 431 } 432 433 434 /** 435 * soc15_program_register_sequence - program an array of registers. 436 * 437 * @adev: amdgpu_device pointer 438 * @regs: pointer to the register array 439 * @array_size: size of the register array 440 * 441 * Programs an array or registers with and and or masks. 442 * This is a helper for setting golden registers. 443 */ 444 445 void soc15_program_register_sequence(struct amdgpu_device *adev, 446 const struct soc15_reg_golden *regs, 447 const u32 array_size) 448 { 449 const struct soc15_reg_golden *entry; 450 u32 tmp, reg; 451 int i; 452 453 for (i = 0; i < array_size; ++i) { 454 entry = ®s[i]; 455 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 456 457 if (entry->and_mask == 0xffffffff) { 458 tmp = entry->or_mask; 459 } else { 460 tmp = (entry->hwip == GC_HWIP) ? 461 RREG32_SOC15_IP(GC, reg) : RREG32(reg); 462 463 tmp &= ~(entry->and_mask); 464 tmp |= (entry->or_mask & entry->and_mask); 465 } 466 467 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 468 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 469 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 470 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 471 WREG32_RLC(reg, tmp); 472 else 473 (entry->hwip == GC_HWIP) ? 474 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); 475 476 } 477 478 } 479 480 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 481 { 482 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 483 int ret = 0; 484 485 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 486 if (ras && adev->ras_enabled) 487 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 488 489 ret = amdgpu_dpm_baco_reset(adev); 490 if (ret) 491 return ret; 492 493 /* re-enable doorbell interrupt after BACO exit */ 494 if (ras && adev->ras_enabled) 495 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 496 497 return 0; 498 } 499 500 static enum amd_reset_method 501 soc15_asic_reset_method(struct amdgpu_device *adev) 502 { 503 bool baco_reset = false; 504 bool connected_to_cpu = false; 505 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 506 507 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) 508 connected_to_cpu = true; 509 510 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 511 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 512 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 513 amdgpu_reset_method == AMD_RESET_METHOD_PCI) { 514 /* If connected to cpu, driver only support mode2 */ 515 if (connected_to_cpu) 516 return AMD_RESET_METHOD_MODE2; 517 return amdgpu_reset_method; 518 } 519 520 if (amdgpu_reset_method != -1) 521 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 522 amdgpu_reset_method); 523 524 switch (adev->ip_versions[MP1_HWIP][0]) { 525 case IP_VERSION(10, 0, 0): 526 case IP_VERSION(10, 0, 1): 527 case IP_VERSION(12, 0, 0): 528 case IP_VERSION(12, 0, 1): 529 return AMD_RESET_METHOD_MODE2; 530 case IP_VERSION(9, 0, 0): 531 case IP_VERSION(11, 0, 2): 532 if (adev->asic_type == CHIP_VEGA20) { 533 if (adev->psp.sos.fw_version >= 0x80067) 534 baco_reset = amdgpu_dpm_is_baco_supported(adev); 535 /* 536 * 1. PMFW version > 0x284300: all cases use baco 537 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 538 */ 539 if (ras && adev->ras_enabled && 540 adev->pm.fw_version <= 0x283400) 541 baco_reset = false; 542 } else { 543 baco_reset = amdgpu_dpm_is_baco_supported(adev); 544 } 545 break; 546 case IP_VERSION(13, 0, 2): 547 /* 548 * 1.connected to cpu: driver issue mode2 reset 549 * 2.discret gpu: driver issue mode1 reset 550 */ 551 if (connected_to_cpu) 552 return AMD_RESET_METHOD_MODE2; 553 break; 554 case IP_VERSION(13, 0, 6): 555 /* Use gpu_recovery param to target a reset method. 556 * Enable triggering of GPU reset only if specified 557 * by module parameter. 558 */ 559 if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5) 560 return AMD_RESET_METHOD_MODE2; 561 else 562 return AMD_RESET_METHOD_NONE; 563 default: 564 break; 565 } 566 567 if (baco_reset) 568 return AMD_RESET_METHOD_BACO; 569 else 570 return AMD_RESET_METHOD_MODE1; 571 } 572 573 static int soc15_asic_reset(struct amdgpu_device *adev) 574 { 575 /* original raven doesn't have full asic reset */ 576 if ((adev->apu_flags & AMD_APU_IS_RAVEN) || 577 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 578 return 0; 579 580 switch (soc15_asic_reset_method(adev)) { 581 case AMD_RESET_METHOD_PCI: 582 dev_info(adev->dev, "PCI reset\n"); 583 return amdgpu_device_pci_reset(adev); 584 case AMD_RESET_METHOD_BACO: 585 dev_info(adev->dev, "BACO reset\n"); 586 return soc15_asic_baco_reset(adev); 587 case AMD_RESET_METHOD_MODE2: 588 dev_info(adev->dev, "MODE2 reset\n"); 589 return amdgpu_dpm_mode2_reset(adev); 590 default: 591 dev_info(adev->dev, "MODE1 reset\n"); 592 return amdgpu_device_mode1_reset(adev); 593 } 594 } 595 596 static bool soc15_supports_baco(struct amdgpu_device *adev) 597 { 598 switch (adev->ip_versions[MP1_HWIP][0]) { 599 case IP_VERSION(9, 0, 0): 600 case IP_VERSION(11, 0, 2): 601 if (adev->asic_type == CHIP_VEGA20) { 602 if (adev->psp.sos.fw_version >= 0x80067) 603 return amdgpu_dpm_is_baco_supported(adev); 604 return false; 605 } else { 606 return amdgpu_dpm_is_baco_supported(adev); 607 } 608 break; 609 default: 610 return false; 611 } 612 } 613 614 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 615 u32 cntl_reg, u32 status_reg) 616 { 617 return 0; 618 }*/ 619 620 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 621 { 622 /*int r; 623 624 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 625 if (r) 626 return r; 627 628 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 629 */ 630 return 0; 631 } 632 633 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 634 { 635 /* todo */ 636 637 return 0; 638 } 639 640 static void soc15_program_aspm(struct amdgpu_device *adev) 641 { 642 if (!amdgpu_device_should_use_aspm(adev)) 643 return; 644 645 if (!(adev->flags & AMD_IS_APU) && 646 (adev->nbio.funcs->program_aspm)) 647 adev->nbio.funcs->program_aspm(adev); 648 } 649 650 const struct amdgpu_ip_block_version vega10_common_ip_block = 651 { 652 .type = AMD_IP_BLOCK_TYPE_COMMON, 653 .major = 2, 654 .minor = 0, 655 .rev = 0, 656 .funcs = &soc15_common_ip_funcs, 657 }; 658 659 static void soc15_reg_base_init(struct amdgpu_device *adev) 660 { 661 /* Set IP register base before any HW register access */ 662 switch (adev->asic_type) { 663 case CHIP_VEGA10: 664 case CHIP_VEGA12: 665 case CHIP_RAVEN: 666 case CHIP_RENOIR: 667 vega10_reg_base_init(adev); 668 break; 669 case CHIP_VEGA20: 670 vega20_reg_base_init(adev); 671 break; 672 case CHIP_ARCTURUS: 673 arct_reg_base_init(adev); 674 break; 675 case CHIP_ALDEBARAN: 676 aldebaran_reg_base_init(adev); 677 break; 678 default: 679 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); 680 break; 681 } 682 } 683 684 void soc15_set_virt_ops(struct amdgpu_device *adev) 685 { 686 adev->virt.ops = &xgpu_ai_virt_ops; 687 688 /* init soc15 reg base early enough so we can 689 * request request full access for sriov before 690 * set_ip_blocks. */ 691 soc15_reg_base_init(adev); 692 } 693 694 static bool soc15_need_full_reset(struct amdgpu_device *adev) 695 { 696 /* change this when we implement soft reset */ 697 return true; 698 } 699 700 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 701 uint64_t *count1) 702 { 703 uint32_t perfctr = 0; 704 uint64_t cnt0_of, cnt1_of; 705 int tmp; 706 707 /* This reports 0 on APUs, so return to avoid writing/reading registers 708 * that may or may not be different from their GPU counterparts 709 */ 710 if (adev->flags & AMD_IS_APU) 711 return; 712 713 /* Set the 2 events that we wish to watch, defined above */ 714 /* Reg 40 is # received msgs */ 715 /* Reg 104 is # of posted requests sent */ 716 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 717 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 718 719 /* Write to enable desired perf counters */ 720 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 721 /* Zero out and enable the perf counters 722 * Write 0x5: 723 * Bit 0 = Start all counters(1) 724 * Bit 2 = Global counter reset enable(1) 725 */ 726 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 727 728 msleep(1000); 729 730 /* Load the shadow and disable the perf counters 731 * Write 0x2: 732 * Bit 0 = Stop counters(0) 733 * Bit 1 = Load the shadow counters(1) 734 */ 735 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 736 737 /* Read register values to get any >32bit overflow */ 738 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 739 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 740 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 741 742 /* Get the values and add the overflow */ 743 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 744 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 745 } 746 747 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 748 uint64_t *count1) 749 { 750 uint32_t perfctr = 0; 751 uint64_t cnt0_of, cnt1_of; 752 int tmp; 753 754 /* This reports 0 on APUs, so return to avoid writing/reading registers 755 * that may or may not be different from their GPU counterparts 756 */ 757 if (adev->flags & AMD_IS_APU) 758 return; 759 760 /* Set the 2 events that we wish to watch, defined above */ 761 /* Reg 40 is # received msgs */ 762 /* Reg 108 is # of posted requests sent on VG20 */ 763 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 764 EVENT0_SEL, 40); 765 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 766 EVENT1_SEL, 108); 767 768 /* Write to enable desired perf counters */ 769 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 770 /* Zero out and enable the perf counters 771 * Write 0x5: 772 * Bit 0 = Start all counters(1) 773 * Bit 2 = Global counter reset enable(1) 774 */ 775 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 776 777 msleep(1000); 778 779 /* Load the shadow and disable the perf counters 780 * Write 0x2: 781 * Bit 0 = Stop counters(0) 782 * Bit 1 = Load the shadow counters(1) 783 */ 784 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 785 786 /* Read register values to get any >32bit overflow */ 787 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 788 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 789 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 790 791 /* Get the values and add the overflow */ 792 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 793 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 794 } 795 796 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 797 { 798 u32 sol_reg; 799 800 /* CP hangs in IGT reloading test on RN, reset to WA */ 801 if (adev->asic_type == CHIP_RENOIR) 802 return true; 803 804 /* Just return false for soc15 GPUs. Reset does not seem to 805 * be necessary. 806 */ 807 if (!amdgpu_passthrough(adev)) 808 return false; 809 810 if (adev->flags & AMD_IS_APU) 811 return false; 812 813 /* Check sOS sign of life register to confirm sys driver and sOS 814 * are already been loaded. 815 */ 816 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 817 if (sol_reg) 818 return true; 819 820 return false; 821 } 822 823 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 824 { 825 uint64_t nak_r, nak_g; 826 827 /* Get the number of NAKs received and generated */ 828 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 829 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 830 831 /* Add the total number of NAKs, i.e the number of replays */ 832 return (nak_r + nak_g); 833 } 834 835 static void soc15_pre_asic_init(struct amdgpu_device *adev) 836 { 837 gmc_v9_0_restore_registers(adev); 838 } 839 840 static const struct amdgpu_asic_funcs soc15_asic_funcs = 841 { 842 .read_disabled_bios = &soc15_read_disabled_bios, 843 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 844 .read_register = &soc15_read_register, 845 .reset = &soc15_asic_reset, 846 .reset_method = &soc15_asic_reset_method, 847 .get_xclk = &soc15_get_xclk, 848 .set_uvd_clocks = &soc15_set_uvd_clocks, 849 .set_vce_clocks = &soc15_set_vce_clocks, 850 .get_config_memsize = &soc15_get_config_memsize, 851 .need_full_reset = &soc15_need_full_reset, 852 .init_doorbell_index = &vega10_doorbell_index_init, 853 .get_pcie_usage = &soc15_get_pcie_usage, 854 .need_reset_on_init = &soc15_need_reset_on_init, 855 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 856 .supports_baco = &soc15_supports_baco, 857 .pre_asic_init = &soc15_pre_asic_init, 858 .query_video_codecs = &soc15_query_video_codecs, 859 }; 860 861 static const struct amdgpu_asic_funcs vega20_asic_funcs = 862 { 863 .read_disabled_bios = &soc15_read_disabled_bios, 864 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 865 .read_register = &soc15_read_register, 866 .reset = &soc15_asic_reset, 867 .reset_method = &soc15_asic_reset_method, 868 .get_xclk = &soc15_get_xclk, 869 .set_uvd_clocks = &soc15_set_uvd_clocks, 870 .set_vce_clocks = &soc15_set_vce_clocks, 871 .get_config_memsize = &soc15_get_config_memsize, 872 .need_full_reset = &soc15_need_full_reset, 873 .init_doorbell_index = &vega20_doorbell_index_init, 874 .get_pcie_usage = &vega20_get_pcie_usage, 875 .need_reset_on_init = &soc15_need_reset_on_init, 876 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 877 .supports_baco = &soc15_supports_baco, 878 .pre_asic_init = &soc15_pre_asic_init, 879 .query_video_codecs = &soc15_query_video_codecs, 880 }; 881 882 static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = 883 { 884 .read_disabled_bios = &soc15_read_disabled_bios, 885 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 886 .read_register = &soc15_read_register, 887 .reset = &soc15_asic_reset, 888 .reset_method = &soc15_asic_reset_method, 889 .get_xclk = &soc15_get_xclk, 890 .set_uvd_clocks = &soc15_set_uvd_clocks, 891 .set_vce_clocks = &soc15_set_vce_clocks, 892 .get_config_memsize = &soc15_get_config_memsize, 893 .need_full_reset = &soc15_need_full_reset, 894 .init_doorbell_index = &aqua_vanjaram_doorbell_index_init, 895 .get_pcie_usage = &vega20_get_pcie_usage, 896 .need_reset_on_init = &soc15_need_reset_on_init, 897 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 898 .supports_baco = &soc15_supports_baco, 899 .pre_asic_init = &soc15_pre_asic_init, 900 .query_video_codecs = &soc15_query_video_codecs, 901 .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing, 902 }; 903 904 static int soc15_common_early_init(void *handle) 905 { 906 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 907 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 908 909 if (!amdgpu_sriov_vf(adev)) { 910 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 911 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 912 } 913 adev->smc_rreg = NULL; 914 adev->smc_wreg = NULL; 915 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 916 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 917 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; 918 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; 919 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 920 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 921 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 922 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 923 adev->didt_rreg = &soc15_didt_rreg; 924 adev->didt_wreg = &soc15_didt_wreg; 925 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 926 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 927 adev->se_cac_rreg = &soc15_se_cac_rreg; 928 adev->se_cac_wreg = &soc15_se_cac_wreg; 929 930 adev->rev_id = amdgpu_device_get_rev_id(adev); 931 adev->external_rev_id = 0xFF; 932 /* TODO: split the GC and PG flags based on the relevant IP version for which 933 * they are relevant. 934 */ 935 switch (adev->ip_versions[GC_HWIP][0]) { 936 case IP_VERSION(9, 0, 1): 937 adev->asic_funcs = &soc15_asic_funcs; 938 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 939 AMD_CG_SUPPORT_GFX_MGLS | 940 AMD_CG_SUPPORT_GFX_RLC_LS | 941 AMD_CG_SUPPORT_GFX_CP_LS | 942 AMD_CG_SUPPORT_GFX_3D_CGCG | 943 AMD_CG_SUPPORT_GFX_3D_CGLS | 944 AMD_CG_SUPPORT_GFX_CGCG | 945 AMD_CG_SUPPORT_GFX_CGLS | 946 AMD_CG_SUPPORT_BIF_MGCG | 947 AMD_CG_SUPPORT_BIF_LS | 948 AMD_CG_SUPPORT_HDP_LS | 949 AMD_CG_SUPPORT_DRM_MGCG | 950 AMD_CG_SUPPORT_DRM_LS | 951 AMD_CG_SUPPORT_ROM_MGCG | 952 AMD_CG_SUPPORT_DF_MGCG | 953 AMD_CG_SUPPORT_SDMA_MGCG | 954 AMD_CG_SUPPORT_SDMA_LS | 955 AMD_CG_SUPPORT_MC_MGCG | 956 AMD_CG_SUPPORT_MC_LS; 957 adev->pg_flags = 0; 958 adev->external_rev_id = 0x1; 959 break; 960 case IP_VERSION(9, 2, 1): 961 adev->asic_funcs = &soc15_asic_funcs; 962 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 963 AMD_CG_SUPPORT_GFX_MGLS | 964 AMD_CG_SUPPORT_GFX_CGCG | 965 AMD_CG_SUPPORT_GFX_CGLS | 966 AMD_CG_SUPPORT_GFX_3D_CGCG | 967 AMD_CG_SUPPORT_GFX_3D_CGLS | 968 AMD_CG_SUPPORT_GFX_CP_LS | 969 AMD_CG_SUPPORT_MC_LS | 970 AMD_CG_SUPPORT_MC_MGCG | 971 AMD_CG_SUPPORT_SDMA_MGCG | 972 AMD_CG_SUPPORT_SDMA_LS | 973 AMD_CG_SUPPORT_BIF_MGCG | 974 AMD_CG_SUPPORT_BIF_LS | 975 AMD_CG_SUPPORT_HDP_MGCG | 976 AMD_CG_SUPPORT_HDP_LS | 977 AMD_CG_SUPPORT_ROM_MGCG | 978 AMD_CG_SUPPORT_VCE_MGCG | 979 AMD_CG_SUPPORT_UVD_MGCG; 980 adev->pg_flags = 0; 981 adev->external_rev_id = adev->rev_id + 0x14; 982 break; 983 case IP_VERSION(9, 4, 0): 984 adev->asic_funcs = &vega20_asic_funcs; 985 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 986 AMD_CG_SUPPORT_GFX_MGLS | 987 AMD_CG_SUPPORT_GFX_CGCG | 988 AMD_CG_SUPPORT_GFX_CGLS | 989 AMD_CG_SUPPORT_GFX_3D_CGCG | 990 AMD_CG_SUPPORT_GFX_3D_CGLS | 991 AMD_CG_SUPPORT_GFX_CP_LS | 992 AMD_CG_SUPPORT_MC_LS | 993 AMD_CG_SUPPORT_MC_MGCG | 994 AMD_CG_SUPPORT_SDMA_MGCG | 995 AMD_CG_SUPPORT_SDMA_LS | 996 AMD_CG_SUPPORT_BIF_MGCG | 997 AMD_CG_SUPPORT_BIF_LS | 998 AMD_CG_SUPPORT_HDP_MGCG | 999 AMD_CG_SUPPORT_HDP_LS | 1000 AMD_CG_SUPPORT_ROM_MGCG | 1001 AMD_CG_SUPPORT_VCE_MGCG | 1002 AMD_CG_SUPPORT_UVD_MGCG; 1003 adev->pg_flags = 0; 1004 adev->external_rev_id = adev->rev_id + 0x28; 1005 break; 1006 case IP_VERSION(9, 1, 0): 1007 case IP_VERSION(9, 2, 2): 1008 adev->asic_funcs = &soc15_asic_funcs; 1009 1010 if (adev->rev_id >= 0x8) 1011 adev->apu_flags |= AMD_APU_IS_RAVEN2; 1012 1013 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1014 adev->external_rev_id = adev->rev_id + 0x79; 1015 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1016 adev->external_rev_id = adev->rev_id + 0x41; 1017 else if (adev->rev_id == 1) 1018 adev->external_rev_id = adev->rev_id + 0x20; 1019 else 1020 adev->external_rev_id = adev->rev_id + 0x01; 1021 1022 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1023 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1024 AMD_CG_SUPPORT_GFX_MGLS | 1025 AMD_CG_SUPPORT_GFX_CP_LS | 1026 AMD_CG_SUPPORT_GFX_3D_CGCG | 1027 AMD_CG_SUPPORT_GFX_3D_CGLS | 1028 AMD_CG_SUPPORT_GFX_CGCG | 1029 AMD_CG_SUPPORT_GFX_CGLS | 1030 AMD_CG_SUPPORT_BIF_LS | 1031 AMD_CG_SUPPORT_HDP_LS | 1032 AMD_CG_SUPPORT_MC_MGCG | 1033 AMD_CG_SUPPORT_MC_LS | 1034 AMD_CG_SUPPORT_SDMA_MGCG | 1035 AMD_CG_SUPPORT_SDMA_LS | 1036 AMD_CG_SUPPORT_VCN_MGCG; 1037 1038 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1039 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { 1040 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1041 AMD_CG_SUPPORT_GFX_MGLS | 1042 AMD_CG_SUPPORT_GFX_CP_LS | 1043 AMD_CG_SUPPORT_GFX_3D_CGLS | 1044 AMD_CG_SUPPORT_GFX_CGCG | 1045 AMD_CG_SUPPORT_GFX_CGLS | 1046 AMD_CG_SUPPORT_BIF_LS | 1047 AMD_CG_SUPPORT_HDP_LS | 1048 AMD_CG_SUPPORT_MC_MGCG | 1049 AMD_CG_SUPPORT_MC_LS | 1050 AMD_CG_SUPPORT_SDMA_MGCG | 1051 AMD_CG_SUPPORT_SDMA_LS | 1052 AMD_CG_SUPPORT_VCN_MGCG; 1053 1054 /* 1055 * MMHUB PG needs to be disabled for Picasso for 1056 * stability reasons. 1057 */ 1058 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1059 AMD_PG_SUPPORT_VCN; 1060 } else { 1061 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1062 AMD_CG_SUPPORT_GFX_MGLS | 1063 AMD_CG_SUPPORT_GFX_RLC_LS | 1064 AMD_CG_SUPPORT_GFX_CP_LS | 1065 AMD_CG_SUPPORT_GFX_3D_CGLS | 1066 AMD_CG_SUPPORT_GFX_CGCG | 1067 AMD_CG_SUPPORT_GFX_CGLS | 1068 AMD_CG_SUPPORT_BIF_MGCG | 1069 AMD_CG_SUPPORT_BIF_LS | 1070 AMD_CG_SUPPORT_HDP_MGCG | 1071 AMD_CG_SUPPORT_HDP_LS | 1072 AMD_CG_SUPPORT_DRM_MGCG | 1073 AMD_CG_SUPPORT_DRM_LS | 1074 AMD_CG_SUPPORT_MC_MGCG | 1075 AMD_CG_SUPPORT_MC_LS | 1076 AMD_CG_SUPPORT_SDMA_MGCG | 1077 AMD_CG_SUPPORT_SDMA_LS | 1078 AMD_CG_SUPPORT_VCN_MGCG; 1079 1080 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1081 } 1082 break; 1083 case IP_VERSION(9, 4, 1): 1084 adev->asic_funcs = &vega20_asic_funcs; 1085 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1086 AMD_CG_SUPPORT_GFX_MGLS | 1087 AMD_CG_SUPPORT_GFX_CGCG | 1088 AMD_CG_SUPPORT_GFX_CGLS | 1089 AMD_CG_SUPPORT_GFX_CP_LS | 1090 AMD_CG_SUPPORT_HDP_MGCG | 1091 AMD_CG_SUPPORT_HDP_LS | 1092 AMD_CG_SUPPORT_SDMA_MGCG | 1093 AMD_CG_SUPPORT_SDMA_LS | 1094 AMD_CG_SUPPORT_MC_MGCG | 1095 AMD_CG_SUPPORT_MC_LS | 1096 AMD_CG_SUPPORT_IH_CG | 1097 AMD_CG_SUPPORT_VCN_MGCG | 1098 AMD_CG_SUPPORT_JPEG_MGCG; 1099 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; 1100 adev->external_rev_id = adev->rev_id + 0x32; 1101 break; 1102 case IP_VERSION(9, 3, 0): 1103 adev->asic_funcs = &soc15_asic_funcs; 1104 1105 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1106 adev->external_rev_id = adev->rev_id + 0x91; 1107 else 1108 adev->external_rev_id = adev->rev_id + 0xa1; 1109 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1110 AMD_CG_SUPPORT_GFX_MGLS | 1111 AMD_CG_SUPPORT_GFX_3D_CGCG | 1112 AMD_CG_SUPPORT_GFX_3D_CGLS | 1113 AMD_CG_SUPPORT_GFX_CGCG | 1114 AMD_CG_SUPPORT_GFX_CGLS | 1115 AMD_CG_SUPPORT_GFX_CP_LS | 1116 AMD_CG_SUPPORT_MC_MGCG | 1117 AMD_CG_SUPPORT_MC_LS | 1118 AMD_CG_SUPPORT_SDMA_MGCG | 1119 AMD_CG_SUPPORT_SDMA_LS | 1120 AMD_CG_SUPPORT_BIF_LS | 1121 AMD_CG_SUPPORT_HDP_LS | 1122 AMD_CG_SUPPORT_VCN_MGCG | 1123 AMD_CG_SUPPORT_JPEG_MGCG | 1124 AMD_CG_SUPPORT_IH_CG | 1125 AMD_CG_SUPPORT_ATHUB_LS | 1126 AMD_CG_SUPPORT_ATHUB_MGCG | 1127 AMD_CG_SUPPORT_DF_MGCG; 1128 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1129 AMD_PG_SUPPORT_VCN | 1130 AMD_PG_SUPPORT_JPEG | 1131 AMD_PG_SUPPORT_VCN_DPG; 1132 break; 1133 case IP_VERSION(9, 4, 2): 1134 adev->asic_funcs = &vega20_asic_funcs; 1135 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1136 AMD_CG_SUPPORT_GFX_MGLS | 1137 AMD_CG_SUPPORT_GFX_CP_LS | 1138 AMD_CG_SUPPORT_HDP_LS | 1139 AMD_CG_SUPPORT_SDMA_MGCG | 1140 AMD_CG_SUPPORT_SDMA_LS | 1141 AMD_CG_SUPPORT_IH_CG | 1142 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; 1143 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 1144 adev->external_rev_id = adev->rev_id + 0x3c; 1145 break; 1146 case IP_VERSION(9, 4, 3): 1147 adev->asic_funcs = &aqua_vanjaram_asic_funcs; 1148 adev->cg_flags = 1149 AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | 1150 AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG | 1151 AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG | 1152 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG | 1153 AMD_CG_SUPPORT_IH_CG; 1154 adev->pg_flags = 1155 AMD_PG_SUPPORT_VCN | 1156 AMD_PG_SUPPORT_VCN_DPG | 1157 AMD_PG_SUPPORT_JPEG; 1158 adev->external_rev_id = adev->rev_id + 0x46; 1159 break; 1160 default: 1161 /* FIXME: not supported yet */ 1162 return -EINVAL; 1163 } 1164 1165 if (amdgpu_sriov_vf(adev)) { 1166 amdgpu_virt_init_setting(adev); 1167 xgpu_ai_mailbox_set_irq_funcs(adev); 1168 } 1169 1170 return 0; 1171 } 1172 1173 static int soc15_common_late_init(void *handle) 1174 { 1175 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1176 1177 if (amdgpu_sriov_vf(adev)) 1178 xgpu_ai_mailbox_get_irq(adev); 1179 1180 /* Enable selfring doorbell aperture late because doorbell BAR 1181 * aperture will change if resize BAR successfully in gmc sw_init. 1182 */ 1183 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 1184 1185 return 0; 1186 } 1187 1188 static int soc15_common_sw_init(void *handle) 1189 { 1190 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1191 1192 if (amdgpu_sriov_vf(adev)) 1193 xgpu_ai_mailbox_add_irq_id(adev); 1194 1195 if (adev->df.funcs && 1196 adev->df.funcs->sw_init) 1197 adev->df.funcs->sw_init(adev); 1198 1199 return 0; 1200 } 1201 1202 static int soc15_common_sw_fini(void *handle) 1203 { 1204 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1205 1206 if (adev->df.funcs && 1207 adev->df.funcs->sw_fini) 1208 adev->df.funcs->sw_fini(adev); 1209 return 0; 1210 } 1211 1212 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev) 1213 { 1214 int i; 1215 1216 /* sdma doorbell range is programed by hypervisor */ 1217 if (!amdgpu_sriov_vf(adev)) { 1218 for (i = 0; i < adev->sdma.num_instances; i++) { 1219 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1220 true, adev->doorbell_index.sdma_engine[i] << 1, 1221 adev->doorbell_index.sdma_doorbell_range); 1222 } 1223 } 1224 } 1225 1226 static int soc15_common_hw_init(void *handle) 1227 { 1228 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1229 1230 /* enable aspm */ 1231 soc15_program_aspm(adev); 1232 /* setup nbio registers */ 1233 adev->nbio.funcs->init_registers(adev); 1234 /* remap HDP registers to a hole in mmio space, 1235 * for the purpose of expose those registers 1236 * to process space 1237 */ 1238 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1239 adev->nbio.funcs->remap_hdp_registers(adev); 1240 1241 /* enable the doorbell aperture */ 1242 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1243 1244 /* HW doorbell routing policy: doorbell writing not 1245 * in SDMA/IH/MM/ACV range will be routed to CP. So 1246 * we need to init SDMA doorbell range prior 1247 * to CP ip block init and ring test. IH already 1248 * happens before CP. 1249 */ 1250 soc15_sdma_doorbell_range_init(adev); 1251 1252 return 0; 1253 } 1254 1255 static int soc15_common_hw_fini(void *handle) 1256 { 1257 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1258 1259 /* Disable the doorbell aperture and selfring doorbell aperture 1260 * separately in hw_fini because soc15_enable_doorbell_aperture 1261 * has been removed and there is no need to delay disabling 1262 * selfring doorbell. 1263 */ 1264 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1265 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1266 1267 if (amdgpu_sriov_vf(adev)) 1268 xgpu_ai_mailbox_put_irq(adev); 1269 1270 if (adev->nbio.ras_if && 1271 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1272 if (adev->nbio.ras && 1273 adev->nbio.ras->init_ras_controller_interrupt) 1274 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1275 if (adev->nbio.ras && 1276 adev->nbio.ras->init_ras_err_event_athub_interrupt) 1277 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1278 } 1279 1280 return 0; 1281 } 1282 1283 static int soc15_common_suspend(void *handle) 1284 { 1285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1286 1287 return soc15_common_hw_fini(adev); 1288 } 1289 1290 static int soc15_common_resume(void *handle) 1291 { 1292 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1293 1294 return soc15_common_hw_init(adev); 1295 } 1296 1297 static bool soc15_common_is_idle(void *handle) 1298 { 1299 return true; 1300 } 1301 1302 static int soc15_common_wait_for_idle(void *handle) 1303 { 1304 return 0; 1305 } 1306 1307 static int soc15_common_soft_reset(void *handle) 1308 { 1309 return 0; 1310 } 1311 1312 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1313 { 1314 uint32_t def, data; 1315 1316 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1317 1318 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1319 data &= ~(0x01000000 | 1320 0x02000000 | 1321 0x04000000 | 1322 0x08000000 | 1323 0x10000000 | 1324 0x20000000 | 1325 0x40000000 | 1326 0x80000000); 1327 else 1328 data |= (0x01000000 | 1329 0x02000000 | 1330 0x04000000 | 1331 0x08000000 | 1332 0x10000000 | 1333 0x20000000 | 1334 0x40000000 | 1335 0x80000000); 1336 1337 if (def != data) 1338 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1339 } 1340 1341 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1342 { 1343 uint32_t def, data; 1344 1345 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1346 1347 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1348 data |= 1; 1349 else 1350 data &= ~1; 1351 1352 if (def != data) 1353 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1354 } 1355 1356 static int soc15_common_set_clockgating_state(void *handle, 1357 enum amd_clockgating_state state) 1358 { 1359 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1360 1361 if (amdgpu_sriov_vf(adev)) 1362 return 0; 1363 1364 switch (adev->ip_versions[NBIO_HWIP][0]) { 1365 case IP_VERSION(6, 1, 0): 1366 case IP_VERSION(6, 2, 0): 1367 case IP_VERSION(7, 4, 0): 1368 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1369 state == AMD_CG_STATE_GATE); 1370 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1371 state == AMD_CG_STATE_GATE); 1372 adev->hdp.funcs->update_clock_gating(adev, 1373 state == AMD_CG_STATE_GATE); 1374 soc15_update_drm_clock_gating(adev, 1375 state == AMD_CG_STATE_GATE); 1376 soc15_update_drm_light_sleep(adev, 1377 state == AMD_CG_STATE_GATE); 1378 adev->smuio.funcs->update_rom_clock_gating(adev, 1379 state == AMD_CG_STATE_GATE); 1380 adev->df.funcs->update_medium_grain_clock_gating(adev, 1381 state == AMD_CG_STATE_GATE); 1382 break; 1383 case IP_VERSION(7, 0, 0): 1384 case IP_VERSION(7, 0, 1): 1385 case IP_VERSION(2, 5, 0): 1386 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1387 state == AMD_CG_STATE_GATE); 1388 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1389 state == AMD_CG_STATE_GATE); 1390 adev->hdp.funcs->update_clock_gating(adev, 1391 state == AMD_CG_STATE_GATE); 1392 soc15_update_drm_clock_gating(adev, 1393 state == AMD_CG_STATE_GATE); 1394 soc15_update_drm_light_sleep(adev, 1395 state == AMD_CG_STATE_GATE); 1396 break; 1397 case IP_VERSION(7, 4, 1): 1398 case IP_VERSION(7, 4, 4): 1399 adev->hdp.funcs->update_clock_gating(adev, 1400 state == AMD_CG_STATE_GATE); 1401 break; 1402 default: 1403 break; 1404 } 1405 return 0; 1406 } 1407 1408 static void soc15_common_get_clockgating_state(void *handle, u64 *flags) 1409 { 1410 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1411 int data; 1412 1413 if (amdgpu_sriov_vf(adev)) 1414 *flags = 0; 1415 1416 adev->nbio.funcs->get_clockgating_state(adev, flags); 1417 1418 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1419 1420 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) { 1421 1422 /* AMD_CG_SUPPORT_DRM_MGCG */ 1423 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1424 if (!(data & 0x01000000)) 1425 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1426 1427 /* AMD_CG_SUPPORT_DRM_LS */ 1428 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1429 if (data & 0x1) 1430 *flags |= AMD_CG_SUPPORT_DRM_LS; 1431 } 1432 1433 /* AMD_CG_SUPPORT_ROM_MGCG */ 1434 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1435 1436 adev->df.funcs->get_clockgating_state(adev, flags); 1437 } 1438 1439 static int soc15_common_set_powergating_state(void *handle, 1440 enum amd_powergating_state state) 1441 { 1442 /* todo */ 1443 return 0; 1444 } 1445 1446 static const struct amd_ip_funcs soc15_common_ip_funcs = { 1447 .name = "soc15_common", 1448 .early_init = soc15_common_early_init, 1449 .late_init = soc15_common_late_init, 1450 .sw_init = soc15_common_sw_init, 1451 .sw_fini = soc15_common_sw_fini, 1452 .hw_init = soc15_common_hw_init, 1453 .hw_fini = soc15_common_hw_fini, 1454 .suspend = soc15_common_suspend, 1455 .resume = soc15_common_resume, 1456 .is_idle = soc15_common_is_idle, 1457 .wait_for_idle = soc15_common_wait_for_idle, 1458 .soft_reset = soc15_common_soft_reset, 1459 .set_clockgating_state = soc15_common_set_clockgating_state, 1460 .set_powergating_state = soc15_common_set_powergating_state, 1461 .get_clockgating_state= soc15_common_get_clockgating_state, 1462 }; 1463