1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "atom.h" 36 #include "amd_pcie.h" 37 38 #include "uvd/uvd_7_0_offset.h" 39 #include "gc/gc_9_0_offset.h" 40 #include "gc/gc_9_0_sh_mask.h" 41 #include "sdma0/sdma0_4_0_offset.h" 42 #include "sdma1/sdma1_4_0_offset.h" 43 #include "hdp/hdp_4_0_offset.h" 44 #include "hdp/hdp_4_0_sh_mask.h" 45 #include "smuio/smuio_9_0_offset.h" 46 #include "smuio/smuio_9_0_sh_mask.h" 47 #include "nbio/nbio_7_0_default.h" 48 #include "nbio/nbio_7_0_offset.h" 49 #include "nbio/nbio_7_0_sh_mask.h" 50 #include "nbio/nbio_7_0_smn.h" 51 #include "mp/mp_9_0_offset.h" 52 53 #include "soc15.h" 54 #include "soc15_common.h" 55 #include "gfx_v9_0.h" 56 #include "gmc_v9_0.h" 57 #include "gfxhub_v1_0.h" 58 #include "mmhub_v1_0.h" 59 #include "df_v1_7.h" 60 #include "df_v3_6.h" 61 #include "nbio_v6_1.h" 62 #include "nbio_v7_0.h" 63 #include "nbio_v7_4.h" 64 #include "vega10_ih.h" 65 #include "sdma_v4_0.h" 66 #include "uvd_v7_0.h" 67 #include "vce_v4_0.h" 68 #include "vcn_v1_0.h" 69 #include "vcn_v2_0.h" 70 #include "jpeg_v2_0.h" 71 #include "vcn_v2_5.h" 72 #include "jpeg_v2_5.h" 73 #include "dce_virtual.h" 74 #include "mxgpu_ai.h" 75 #include "amdgpu_smu.h" 76 #include "amdgpu_ras.h" 77 #include "amdgpu_xgmi.h" 78 #include <uapi/linux/kfd_ioctl.h> 79 80 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 81 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 82 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 84 85 /* for Vega20 register name change */ 86 #define mmHDP_MEM_POWER_CTRL 0x00d4 87 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 89 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 91 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 92 93 /* for Vega20/arcturus regiter offset change */ 94 #define mmROM_INDEX_VG20 0x00e4 95 #define mmROM_INDEX_VG20_BASE_IDX 0 96 #define mmROM_DATA_VG20 0x00e5 97 #define mmROM_DATA_VG20_BASE_IDX 0 98 99 /* 100 * Indirect registers accessor 101 */ 102 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 103 { 104 unsigned long flags, address, data; 105 u32 r; 106 address = adev->nbio.funcs->get_pcie_index_offset(adev); 107 data = adev->nbio.funcs->get_pcie_data_offset(adev); 108 109 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 110 WREG32(address, reg); 111 (void)RREG32(address); 112 r = RREG32(data); 113 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 114 return r; 115 } 116 117 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 118 { 119 unsigned long flags, address, data; 120 121 address = adev->nbio.funcs->get_pcie_index_offset(adev); 122 data = adev->nbio.funcs->get_pcie_data_offset(adev); 123 124 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 125 WREG32(address, reg); 126 (void)RREG32(address); 127 WREG32(data, v); 128 (void)RREG32(data); 129 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 130 } 131 132 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 133 { 134 unsigned long flags, address, data; 135 u64 r; 136 address = adev->nbio.funcs->get_pcie_index_offset(adev); 137 data = adev->nbio.funcs->get_pcie_data_offset(adev); 138 139 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 140 /* read low 32 bit */ 141 WREG32(address, reg); 142 (void)RREG32(address); 143 r = RREG32(data); 144 145 /* read high 32 bit*/ 146 WREG32(address, reg + 4); 147 (void)RREG32(address); 148 r |= ((u64)RREG32(data) << 32); 149 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 150 return r; 151 } 152 153 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 154 { 155 unsigned long flags, address, data; 156 157 address = adev->nbio.funcs->get_pcie_index_offset(adev); 158 data = adev->nbio.funcs->get_pcie_data_offset(adev); 159 160 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 161 /* write low 32 bit */ 162 WREG32(address, reg); 163 (void)RREG32(address); 164 WREG32(data, (u32)(v & 0xffffffffULL)); 165 (void)RREG32(data); 166 167 /* write high 32 bit */ 168 WREG32(address, reg + 4); 169 (void)RREG32(address); 170 WREG32(data, (u32)(v >> 32)); 171 (void)RREG32(data); 172 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 173 } 174 175 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 176 { 177 unsigned long flags, address, data; 178 u32 r; 179 180 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 181 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 182 183 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 184 WREG32(address, ((reg) & 0x1ff)); 185 r = RREG32(data); 186 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 187 return r; 188 } 189 190 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 191 { 192 unsigned long flags, address, data; 193 194 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 195 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 196 197 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 198 WREG32(address, ((reg) & 0x1ff)); 199 WREG32(data, (v)); 200 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 201 } 202 203 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 204 { 205 unsigned long flags, address, data; 206 u32 r; 207 208 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 209 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 210 211 spin_lock_irqsave(&adev->didt_idx_lock, flags); 212 WREG32(address, (reg)); 213 r = RREG32(data); 214 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 215 return r; 216 } 217 218 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 219 { 220 unsigned long flags, address, data; 221 222 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 223 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 224 225 spin_lock_irqsave(&adev->didt_idx_lock, flags); 226 WREG32(address, (reg)); 227 WREG32(data, (v)); 228 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 229 } 230 231 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 232 { 233 unsigned long flags; 234 u32 r; 235 236 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 237 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 238 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 239 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 240 return r; 241 } 242 243 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 244 { 245 unsigned long flags; 246 247 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 248 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 249 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 250 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 251 } 252 253 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 254 { 255 unsigned long flags; 256 u32 r; 257 258 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 259 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 260 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 261 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 262 return r; 263 } 264 265 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 266 { 267 unsigned long flags; 268 269 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 270 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 271 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 272 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 273 } 274 275 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 276 { 277 return adev->nbio.funcs->get_memsize(adev); 278 } 279 280 static u32 soc15_get_xclk(struct amdgpu_device *adev) 281 { 282 u32 reference_clock = adev->clock.spll.reference_freq; 283 284 if (adev->asic_type == CHIP_RAVEN) 285 return reference_clock / 4; 286 287 return reference_clock; 288 } 289 290 291 void soc15_grbm_select(struct amdgpu_device *adev, 292 u32 me, u32 pipe, u32 queue, u32 vmid) 293 { 294 u32 grbm_gfx_cntl = 0; 295 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 296 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 297 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 298 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 299 300 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 301 } 302 303 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 304 { 305 /* todo */ 306 } 307 308 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 309 { 310 /* todo */ 311 return false; 312 } 313 314 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 315 u8 *bios, u32 length_bytes) 316 { 317 u32 *dw_ptr; 318 u32 i, length_dw; 319 uint32_t rom_index_offset; 320 uint32_t rom_data_offset; 321 322 if (bios == NULL) 323 return false; 324 if (length_bytes == 0) 325 return false; 326 /* APU vbios image is part of sbios image */ 327 if (adev->flags & AMD_IS_APU) 328 return false; 329 330 dw_ptr = (u32 *)bios; 331 length_dw = ALIGN(length_bytes, 4) / 4; 332 333 switch (adev->asic_type) { 334 case CHIP_VEGA20: 335 case CHIP_ARCTURUS: 336 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX_VG20); 337 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA_VG20); 338 break; 339 default: 340 rom_index_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX); 341 rom_data_offset = SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA); 342 break; 343 } 344 345 /* set rom index to 0 */ 346 WREG32(rom_index_offset, 0); 347 /* read out the rom data */ 348 for (i = 0; i < length_dw; i++) 349 dw_ptr[i] = RREG32(rom_data_offset); 350 351 return true; 352 } 353 354 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 355 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 356 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 357 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 358 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 359 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 360 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 361 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 362 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 363 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 364 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 365 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 366 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 367 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 368 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 369 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 370 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 371 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 372 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 373 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 374 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 375 }; 376 377 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 378 u32 sh_num, u32 reg_offset) 379 { 380 uint32_t val; 381 382 mutex_lock(&adev->grbm_idx_mutex); 383 if (se_num != 0xffffffff || sh_num != 0xffffffff) 384 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 385 386 val = RREG32(reg_offset); 387 388 if (se_num != 0xffffffff || sh_num != 0xffffffff) 389 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 390 mutex_unlock(&adev->grbm_idx_mutex); 391 return val; 392 } 393 394 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 395 bool indexed, u32 se_num, 396 u32 sh_num, u32 reg_offset) 397 { 398 if (indexed) { 399 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 400 } else { 401 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 402 return adev->gfx.config.gb_addr_config; 403 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 404 return adev->gfx.config.db_debug2; 405 return RREG32(reg_offset); 406 } 407 } 408 409 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 410 u32 sh_num, u32 reg_offset, u32 *value) 411 { 412 uint32_t i; 413 struct soc15_allowed_register_entry *en; 414 415 *value = 0; 416 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 417 en = &soc15_allowed_read_registers[i]; 418 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 419 + en->reg_offset)) 420 continue; 421 422 *value = soc15_get_register_value(adev, 423 soc15_allowed_read_registers[i].grbm_indexed, 424 se_num, sh_num, reg_offset); 425 return 0; 426 } 427 return -EINVAL; 428 } 429 430 431 /** 432 * soc15_program_register_sequence - program an array of registers. 433 * 434 * @adev: amdgpu_device pointer 435 * @regs: pointer to the register array 436 * @array_size: size of the register array 437 * 438 * Programs an array or registers with and and or masks. 439 * This is a helper for setting golden registers. 440 */ 441 442 void soc15_program_register_sequence(struct amdgpu_device *adev, 443 const struct soc15_reg_golden *regs, 444 const u32 array_size) 445 { 446 const struct soc15_reg_golden *entry; 447 u32 tmp, reg; 448 int i; 449 450 for (i = 0; i < array_size; ++i) { 451 entry = ®s[i]; 452 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 453 454 if (entry->and_mask == 0xffffffff) { 455 tmp = entry->or_mask; 456 } else { 457 tmp = RREG32(reg); 458 tmp &= ~(entry->and_mask); 459 tmp |= (entry->or_mask & entry->and_mask); 460 } 461 462 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 463 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 464 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 465 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 466 WREG32_RLC(reg, tmp); 467 else 468 WREG32(reg, tmp); 469 470 } 471 472 } 473 474 static int soc15_asic_mode1_reset(struct amdgpu_device *adev) 475 { 476 u32 i; 477 int ret = 0; 478 479 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 480 481 dev_info(adev->dev, "GPU mode1 reset\n"); 482 483 /* disable BM */ 484 pci_clear_master(adev->pdev); 485 486 pci_save_state(adev->pdev); 487 488 ret = psp_gpu_reset(adev); 489 if (ret) 490 dev_err(adev->dev, "GPU mode1 reset failed\n"); 491 492 pci_restore_state(adev->pdev); 493 494 /* wait for asic to come out of reset */ 495 for (i = 0; i < adev->usec_timeout; i++) { 496 u32 memsize = adev->nbio.funcs->get_memsize(adev); 497 498 if (memsize != 0xffffffff) 499 break; 500 udelay(1); 501 } 502 503 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 504 505 return ret; 506 } 507 508 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 509 { 510 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 511 int ret = 0; 512 513 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 514 if (ras && ras->supported) 515 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 516 517 ret = amdgpu_dpm_baco_reset(adev); 518 if (ret) 519 return ret; 520 521 /* re-enable doorbell interrupt after BACO exit */ 522 if (ras && ras->supported) 523 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 524 525 return 0; 526 } 527 528 static enum amd_reset_method 529 soc15_asic_reset_method(struct amdgpu_device *adev) 530 { 531 bool baco_reset = false; 532 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 533 534 switch (adev->asic_type) { 535 case CHIP_RAVEN: 536 case CHIP_RENOIR: 537 return AMD_RESET_METHOD_MODE2; 538 case CHIP_VEGA10: 539 case CHIP_VEGA12: 540 case CHIP_ARCTURUS: 541 baco_reset = amdgpu_dpm_is_baco_supported(adev); 542 break; 543 case CHIP_VEGA20: 544 if (adev->psp.sos_fw_version >= 0x80067) 545 baco_reset = amdgpu_dpm_is_baco_supported(adev); 546 547 /* 548 * 1. PMFW version > 0x284300: all cases use baco 549 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 550 */ 551 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400) 552 baco_reset = false; 553 break; 554 default: 555 break; 556 } 557 558 if (baco_reset) 559 return AMD_RESET_METHOD_BACO; 560 else 561 return AMD_RESET_METHOD_MODE1; 562 } 563 564 static int soc15_asic_reset(struct amdgpu_device *adev) 565 { 566 /* original raven doesn't have full asic reset */ 567 if ((adev->apu_flags & AMD_APU_IS_RAVEN) && 568 !(adev->apu_flags & AMD_APU_IS_RAVEN2)) 569 return 0; 570 571 switch (soc15_asic_reset_method(adev)) { 572 case AMD_RESET_METHOD_BACO: 573 return soc15_asic_baco_reset(adev); 574 case AMD_RESET_METHOD_MODE2: 575 return amdgpu_dpm_mode2_reset(adev); 576 default: 577 return soc15_asic_mode1_reset(adev); 578 } 579 } 580 581 static bool soc15_supports_baco(struct amdgpu_device *adev) 582 { 583 switch (adev->asic_type) { 584 case CHIP_VEGA10: 585 case CHIP_VEGA12: 586 case CHIP_ARCTURUS: 587 return amdgpu_dpm_is_baco_supported(adev); 588 case CHIP_VEGA20: 589 if (adev->psp.sos_fw_version >= 0x80067) 590 return amdgpu_dpm_is_baco_supported(adev); 591 return false; 592 default: 593 return false; 594 } 595 } 596 597 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 598 u32 cntl_reg, u32 status_reg) 599 { 600 return 0; 601 }*/ 602 603 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 604 { 605 /*int r; 606 607 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 608 if (r) 609 return r; 610 611 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 612 */ 613 return 0; 614 } 615 616 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 617 { 618 /* todo */ 619 620 return 0; 621 } 622 623 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 624 { 625 if (pci_is_root_bus(adev->pdev->bus)) 626 return; 627 628 if (amdgpu_pcie_gen2 == 0) 629 return; 630 631 if (adev->flags & AMD_IS_APU) 632 return; 633 634 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 635 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 636 return; 637 638 /* todo */ 639 } 640 641 static void soc15_program_aspm(struct amdgpu_device *adev) 642 { 643 644 if (amdgpu_aspm == 0) 645 return; 646 647 /* todo */ 648 } 649 650 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 651 bool enable) 652 { 653 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 654 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 655 } 656 657 static const struct amdgpu_ip_block_version vega10_common_ip_block = 658 { 659 .type = AMD_IP_BLOCK_TYPE_COMMON, 660 .major = 2, 661 .minor = 0, 662 .rev = 0, 663 .funcs = &soc15_common_ip_funcs, 664 }; 665 666 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 667 { 668 return adev->nbio.funcs->get_rev_id(adev); 669 } 670 671 int soc15_set_ip_blocks(struct amdgpu_device *adev) 672 { 673 int r; 674 675 /* Set IP register base before any HW register access */ 676 switch (adev->asic_type) { 677 case CHIP_VEGA10: 678 case CHIP_VEGA12: 679 case CHIP_RAVEN: 680 vega10_reg_base_init(adev); 681 break; 682 case CHIP_RENOIR: 683 if (amdgpu_discovery) { 684 r = amdgpu_discovery_reg_base_init(adev); 685 if (r) { 686 DRM_WARN("failed to init reg base from ip discovery table, " 687 "fallback to legacy init method\n"); 688 vega10_reg_base_init(adev); 689 } 690 } 691 break; 692 case CHIP_VEGA20: 693 vega20_reg_base_init(adev); 694 break; 695 case CHIP_ARCTURUS: 696 arct_reg_base_init(adev); 697 break; 698 default: 699 return -EINVAL; 700 } 701 702 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 703 adev->gmc.xgmi.supported = true; 704 705 if (adev->flags & AMD_IS_APU) { 706 adev->nbio.funcs = &nbio_v7_0_funcs; 707 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 708 } else if (adev->asic_type == CHIP_VEGA20 || 709 adev->asic_type == CHIP_ARCTURUS) { 710 adev->nbio.funcs = &nbio_v7_4_funcs; 711 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 712 } else { 713 adev->nbio.funcs = &nbio_v6_1_funcs; 714 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 715 } 716 717 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 718 adev->df.funcs = &df_v3_6_funcs; 719 else 720 adev->df.funcs = &df_v1_7_funcs; 721 722 adev->rev_id = soc15_get_rev_id(adev); 723 724 if (amdgpu_sriov_vf(adev)) 725 adev->virt.ops = &xgpu_ai_virt_ops; 726 727 switch (adev->asic_type) { 728 case CHIP_VEGA10: 729 case CHIP_VEGA12: 730 case CHIP_VEGA20: 731 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 732 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 733 734 /* For Vega10 SR-IOV, PSP need to be initialized before IH */ 735 if (amdgpu_sriov_vf(adev)) { 736 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 737 if (adev->asic_type == CHIP_VEGA20) 738 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 739 else 740 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 741 } 742 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 743 } else { 744 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 745 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 746 if (adev->asic_type == CHIP_VEGA20) 747 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 748 else 749 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 750 } 751 } 752 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 753 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 754 if (is_support_sw_smu(adev)) { 755 if (!amdgpu_sriov_vf(adev)) 756 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 757 } else { 758 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 759 } 760 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 761 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 762 #if defined(CONFIG_DRM_AMD_DC) 763 else if (amdgpu_device_has_dc_support(adev)) 764 amdgpu_device_ip_block_add(adev, &dm_ip_block); 765 #endif 766 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { 767 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 768 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 769 } 770 break; 771 case CHIP_RAVEN: 772 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 773 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 774 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 775 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 776 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 777 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 778 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 779 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 780 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 781 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 782 #if defined(CONFIG_DRM_AMD_DC) 783 else if (amdgpu_device_has_dc_support(adev)) 784 amdgpu_device_ip_block_add(adev, &dm_ip_block); 785 #endif 786 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 787 break; 788 case CHIP_ARCTURUS: 789 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 790 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 791 792 if (amdgpu_sriov_vf(adev)) { 793 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 794 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 795 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 796 } else { 797 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 798 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 799 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 800 } 801 802 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 803 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 804 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 805 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 806 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 807 808 if (amdgpu_sriov_vf(adev)) { 809 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 810 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 811 } else { 812 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 813 } 814 if (!amdgpu_sriov_vf(adev)) 815 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 816 break; 817 case CHIP_RENOIR: 818 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 819 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 820 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 821 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 822 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 823 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 824 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 825 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 826 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 827 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 828 #if defined(CONFIG_DRM_AMD_DC) 829 else if (amdgpu_device_has_dc_support(adev)) 830 amdgpu_device_ip_block_add(adev, &dm_ip_block); 831 #endif 832 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 833 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 834 break; 835 default: 836 return -EINVAL; 837 } 838 839 return 0; 840 } 841 842 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 843 { 844 adev->nbio.funcs->hdp_flush(adev, ring); 845 } 846 847 static void soc15_invalidate_hdp(struct amdgpu_device *adev, 848 struct amdgpu_ring *ring) 849 { 850 if (!ring || !ring->funcs->emit_wreg) 851 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 852 else 853 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 854 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 855 } 856 857 static bool soc15_need_full_reset(struct amdgpu_device *adev) 858 { 859 /* change this when we implement soft reset */ 860 return true; 861 } 862 863 static void vega20_reset_hdp_ras_error_count(struct amdgpu_device *adev) 864 { 865 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP)) 866 return; 867 /*read back hdp ras counter to reset it to 0 */ 868 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); 869 } 870 871 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 872 uint64_t *count1) 873 { 874 uint32_t perfctr = 0; 875 uint64_t cnt0_of, cnt1_of; 876 int tmp; 877 878 /* This reports 0 on APUs, so return to avoid writing/reading registers 879 * that may or may not be different from their GPU counterparts 880 */ 881 if (adev->flags & AMD_IS_APU) 882 return; 883 884 /* Set the 2 events that we wish to watch, defined above */ 885 /* Reg 40 is # received msgs */ 886 /* Reg 104 is # of posted requests sent */ 887 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 888 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 889 890 /* Write to enable desired perf counters */ 891 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 892 /* Zero out and enable the perf counters 893 * Write 0x5: 894 * Bit 0 = Start all counters(1) 895 * Bit 2 = Global counter reset enable(1) 896 */ 897 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 898 899 msleep(1000); 900 901 /* Load the shadow and disable the perf counters 902 * Write 0x2: 903 * Bit 0 = Stop counters(0) 904 * Bit 1 = Load the shadow counters(1) 905 */ 906 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 907 908 /* Read register values to get any >32bit overflow */ 909 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 910 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 911 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 912 913 /* Get the values and add the overflow */ 914 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 915 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 916 } 917 918 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 919 uint64_t *count1) 920 { 921 uint32_t perfctr = 0; 922 uint64_t cnt0_of, cnt1_of; 923 int tmp; 924 925 /* This reports 0 on APUs, so return to avoid writing/reading registers 926 * that may or may not be different from their GPU counterparts 927 */ 928 if (adev->flags & AMD_IS_APU) 929 return; 930 931 /* Set the 2 events that we wish to watch, defined above */ 932 /* Reg 40 is # received msgs */ 933 /* Reg 108 is # of posted requests sent on VG20 */ 934 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 935 EVENT0_SEL, 40); 936 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 937 EVENT1_SEL, 108); 938 939 /* Write to enable desired perf counters */ 940 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 941 /* Zero out and enable the perf counters 942 * Write 0x5: 943 * Bit 0 = Start all counters(1) 944 * Bit 2 = Global counter reset enable(1) 945 */ 946 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 947 948 msleep(1000); 949 950 /* Load the shadow and disable the perf counters 951 * Write 0x2: 952 * Bit 0 = Stop counters(0) 953 * Bit 1 = Load the shadow counters(1) 954 */ 955 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 956 957 /* Read register values to get any >32bit overflow */ 958 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 959 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 960 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 961 962 /* Get the values and add the overflow */ 963 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 964 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 965 } 966 967 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 968 { 969 u32 sol_reg; 970 971 /* Just return false for soc15 GPUs. Reset does not seem to 972 * be necessary. 973 */ 974 if (!amdgpu_passthrough(adev)) 975 return false; 976 977 if (adev->flags & AMD_IS_APU) 978 return false; 979 980 /* Check sOS sign of life register to confirm sys driver and sOS 981 * are already been loaded. 982 */ 983 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 984 if (sol_reg) 985 return true; 986 987 return false; 988 } 989 990 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 991 { 992 uint64_t nak_r, nak_g; 993 994 /* Get the number of NAKs received and generated */ 995 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 996 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 997 998 /* Add the total number of NAKs, i.e the number of replays */ 999 return (nak_r + nak_g); 1000 } 1001 1002 static const struct amdgpu_asic_funcs soc15_asic_funcs = 1003 { 1004 .read_disabled_bios = &soc15_read_disabled_bios, 1005 .read_bios_from_rom = &soc15_read_bios_from_rom, 1006 .read_register = &soc15_read_register, 1007 .reset = &soc15_asic_reset, 1008 .reset_method = &soc15_asic_reset_method, 1009 .set_vga_state = &soc15_vga_set_state, 1010 .get_xclk = &soc15_get_xclk, 1011 .set_uvd_clocks = &soc15_set_uvd_clocks, 1012 .set_vce_clocks = &soc15_set_vce_clocks, 1013 .get_config_memsize = &soc15_get_config_memsize, 1014 .flush_hdp = &soc15_flush_hdp, 1015 .invalidate_hdp = &soc15_invalidate_hdp, 1016 .need_full_reset = &soc15_need_full_reset, 1017 .init_doorbell_index = &vega10_doorbell_index_init, 1018 .get_pcie_usage = &soc15_get_pcie_usage, 1019 .need_reset_on_init = &soc15_need_reset_on_init, 1020 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1021 .supports_baco = &soc15_supports_baco, 1022 }; 1023 1024 static const struct amdgpu_asic_funcs vega20_asic_funcs = 1025 { 1026 .read_disabled_bios = &soc15_read_disabled_bios, 1027 .read_bios_from_rom = &soc15_read_bios_from_rom, 1028 .read_register = &soc15_read_register, 1029 .reset = &soc15_asic_reset, 1030 .reset_method = &soc15_asic_reset_method, 1031 .set_vga_state = &soc15_vga_set_state, 1032 .get_xclk = &soc15_get_xclk, 1033 .set_uvd_clocks = &soc15_set_uvd_clocks, 1034 .set_vce_clocks = &soc15_set_vce_clocks, 1035 .get_config_memsize = &soc15_get_config_memsize, 1036 .flush_hdp = &soc15_flush_hdp, 1037 .invalidate_hdp = &soc15_invalidate_hdp, 1038 .reset_hdp_ras_error_count = &vega20_reset_hdp_ras_error_count, 1039 .need_full_reset = &soc15_need_full_reset, 1040 .init_doorbell_index = &vega20_doorbell_index_init, 1041 .get_pcie_usage = &vega20_get_pcie_usage, 1042 .need_reset_on_init = &soc15_need_reset_on_init, 1043 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1044 .supports_baco = &soc15_supports_baco, 1045 }; 1046 1047 static int soc15_common_early_init(void *handle) 1048 { 1049 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 1050 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1051 1052 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 1053 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 1054 adev->smc_rreg = NULL; 1055 adev->smc_wreg = NULL; 1056 adev->pcie_rreg = &soc15_pcie_rreg; 1057 adev->pcie_wreg = &soc15_pcie_wreg; 1058 adev->pcie_rreg64 = &soc15_pcie_rreg64; 1059 adev->pcie_wreg64 = &soc15_pcie_wreg64; 1060 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 1061 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 1062 adev->didt_rreg = &soc15_didt_rreg; 1063 adev->didt_wreg = &soc15_didt_wreg; 1064 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 1065 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 1066 adev->se_cac_rreg = &soc15_se_cac_rreg; 1067 adev->se_cac_wreg = &soc15_se_cac_wreg; 1068 1069 1070 adev->external_rev_id = 0xFF; 1071 switch (adev->asic_type) { 1072 case CHIP_VEGA10: 1073 adev->asic_funcs = &soc15_asic_funcs; 1074 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1075 AMD_CG_SUPPORT_GFX_MGLS | 1076 AMD_CG_SUPPORT_GFX_RLC_LS | 1077 AMD_CG_SUPPORT_GFX_CP_LS | 1078 AMD_CG_SUPPORT_GFX_3D_CGCG | 1079 AMD_CG_SUPPORT_GFX_3D_CGLS | 1080 AMD_CG_SUPPORT_GFX_CGCG | 1081 AMD_CG_SUPPORT_GFX_CGLS | 1082 AMD_CG_SUPPORT_BIF_MGCG | 1083 AMD_CG_SUPPORT_BIF_LS | 1084 AMD_CG_SUPPORT_HDP_LS | 1085 AMD_CG_SUPPORT_DRM_MGCG | 1086 AMD_CG_SUPPORT_DRM_LS | 1087 AMD_CG_SUPPORT_ROM_MGCG | 1088 AMD_CG_SUPPORT_DF_MGCG | 1089 AMD_CG_SUPPORT_SDMA_MGCG | 1090 AMD_CG_SUPPORT_SDMA_LS | 1091 AMD_CG_SUPPORT_MC_MGCG | 1092 AMD_CG_SUPPORT_MC_LS; 1093 adev->pg_flags = 0; 1094 adev->external_rev_id = 0x1; 1095 break; 1096 case CHIP_VEGA12: 1097 adev->asic_funcs = &soc15_asic_funcs; 1098 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1099 AMD_CG_SUPPORT_GFX_MGLS | 1100 AMD_CG_SUPPORT_GFX_CGCG | 1101 AMD_CG_SUPPORT_GFX_CGLS | 1102 AMD_CG_SUPPORT_GFX_3D_CGCG | 1103 AMD_CG_SUPPORT_GFX_3D_CGLS | 1104 AMD_CG_SUPPORT_GFX_CP_LS | 1105 AMD_CG_SUPPORT_MC_LS | 1106 AMD_CG_SUPPORT_MC_MGCG | 1107 AMD_CG_SUPPORT_SDMA_MGCG | 1108 AMD_CG_SUPPORT_SDMA_LS | 1109 AMD_CG_SUPPORT_BIF_MGCG | 1110 AMD_CG_SUPPORT_BIF_LS | 1111 AMD_CG_SUPPORT_HDP_MGCG | 1112 AMD_CG_SUPPORT_HDP_LS | 1113 AMD_CG_SUPPORT_ROM_MGCG | 1114 AMD_CG_SUPPORT_VCE_MGCG | 1115 AMD_CG_SUPPORT_UVD_MGCG; 1116 adev->pg_flags = 0; 1117 adev->external_rev_id = adev->rev_id + 0x14; 1118 break; 1119 case CHIP_VEGA20: 1120 adev->asic_funcs = &vega20_asic_funcs; 1121 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1122 AMD_CG_SUPPORT_GFX_MGLS | 1123 AMD_CG_SUPPORT_GFX_CGCG | 1124 AMD_CG_SUPPORT_GFX_CGLS | 1125 AMD_CG_SUPPORT_GFX_3D_CGCG | 1126 AMD_CG_SUPPORT_GFX_3D_CGLS | 1127 AMD_CG_SUPPORT_GFX_CP_LS | 1128 AMD_CG_SUPPORT_MC_LS | 1129 AMD_CG_SUPPORT_MC_MGCG | 1130 AMD_CG_SUPPORT_SDMA_MGCG | 1131 AMD_CG_SUPPORT_SDMA_LS | 1132 AMD_CG_SUPPORT_BIF_MGCG | 1133 AMD_CG_SUPPORT_BIF_LS | 1134 AMD_CG_SUPPORT_HDP_MGCG | 1135 AMD_CG_SUPPORT_HDP_LS | 1136 AMD_CG_SUPPORT_ROM_MGCG | 1137 AMD_CG_SUPPORT_VCE_MGCG | 1138 AMD_CG_SUPPORT_UVD_MGCG; 1139 adev->pg_flags = 0; 1140 adev->external_rev_id = adev->rev_id + 0x28; 1141 break; 1142 case CHIP_RAVEN: 1143 adev->asic_funcs = &soc15_asic_funcs; 1144 if (adev->pdev->device == 0x15dd) 1145 adev->apu_flags |= AMD_APU_IS_RAVEN; 1146 if (adev->pdev->device == 0x15d8) 1147 adev->apu_flags |= AMD_APU_IS_PICASSO; 1148 if (adev->rev_id >= 0x8) 1149 adev->apu_flags |= AMD_APU_IS_RAVEN2; 1150 1151 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1152 adev->external_rev_id = adev->rev_id + 0x79; 1153 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1154 adev->external_rev_id = adev->rev_id + 0x41; 1155 else if (adev->rev_id == 1) 1156 adev->external_rev_id = adev->rev_id + 0x20; 1157 else 1158 adev->external_rev_id = adev->rev_id + 0x01; 1159 1160 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1161 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1162 AMD_CG_SUPPORT_GFX_MGLS | 1163 AMD_CG_SUPPORT_GFX_CP_LS | 1164 AMD_CG_SUPPORT_GFX_3D_CGCG | 1165 AMD_CG_SUPPORT_GFX_3D_CGLS | 1166 AMD_CG_SUPPORT_GFX_CGCG | 1167 AMD_CG_SUPPORT_GFX_CGLS | 1168 AMD_CG_SUPPORT_BIF_LS | 1169 AMD_CG_SUPPORT_HDP_LS | 1170 AMD_CG_SUPPORT_ROM_MGCG | 1171 AMD_CG_SUPPORT_MC_MGCG | 1172 AMD_CG_SUPPORT_MC_LS | 1173 AMD_CG_SUPPORT_SDMA_MGCG | 1174 AMD_CG_SUPPORT_SDMA_LS | 1175 AMD_CG_SUPPORT_VCN_MGCG; 1176 1177 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1178 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { 1179 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1180 AMD_CG_SUPPORT_GFX_MGLS | 1181 AMD_CG_SUPPORT_GFX_CP_LS | 1182 AMD_CG_SUPPORT_GFX_3D_CGCG | 1183 AMD_CG_SUPPORT_GFX_3D_CGLS | 1184 AMD_CG_SUPPORT_GFX_CGCG | 1185 AMD_CG_SUPPORT_GFX_CGLS | 1186 AMD_CG_SUPPORT_BIF_LS | 1187 AMD_CG_SUPPORT_HDP_LS | 1188 AMD_CG_SUPPORT_ROM_MGCG | 1189 AMD_CG_SUPPORT_MC_MGCG | 1190 AMD_CG_SUPPORT_MC_LS | 1191 AMD_CG_SUPPORT_SDMA_MGCG | 1192 AMD_CG_SUPPORT_SDMA_LS; 1193 1194 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1195 AMD_PG_SUPPORT_MMHUB | 1196 AMD_PG_SUPPORT_VCN | 1197 AMD_PG_SUPPORT_VCN_DPG; 1198 } else { 1199 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1200 AMD_CG_SUPPORT_GFX_MGLS | 1201 AMD_CG_SUPPORT_GFX_RLC_LS | 1202 AMD_CG_SUPPORT_GFX_CP_LS | 1203 AMD_CG_SUPPORT_GFX_3D_CGCG | 1204 AMD_CG_SUPPORT_GFX_3D_CGLS | 1205 AMD_CG_SUPPORT_GFX_CGCG | 1206 AMD_CG_SUPPORT_GFX_CGLS | 1207 AMD_CG_SUPPORT_BIF_MGCG | 1208 AMD_CG_SUPPORT_BIF_LS | 1209 AMD_CG_SUPPORT_HDP_MGCG | 1210 AMD_CG_SUPPORT_HDP_LS | 1211 AMD_CG_SUPPORT_DRM_MGCG | 1212 AMD_CG_SUPPORT_DRM_LS | 1213 AMD_CG_SUPPORT_ROM_MGCG | 1214 AMD_CG_SUPPORT_MC_MGCG | 1215 AMD_CG_SUPPORT_MC_LS | 1216 AMD_CG_SUPPORT_SDMA_MGCG | 1217 AMD_CG_SUPPORT_SDMA_LS | 1218 AMD_CG_SUPPORT_VCN_MGCG; 1219 1220 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1221 } 1222 break; 1223 case CHIP_ARCTURUS: 1224 adev->asic_funcs = &vega20_asic_funcs; 1225 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1226 AMD_CG_SUPPORT_GFX_MGLS | 1227 AMD_CG_SUPPORT_GFX_CGCG | 1228 AMD_CG_SUPPORT_GFX_CGLS | 1229 AMD_CG_SUPPORT_GFX_CP_LS | 1230 AMD_CG_SUPPORT_HDP_MGCG | 1231 AMD_CG_SUPPORT_HDP_LS | 1232 AMD_CG_SUPPORT_SDMA_MGCG | 1233 AMD_CG_SUPPORT_SDMA_LS | 1234 AMD_CG_SUPPORT_MC_MGCG | 1235 AMD_CG_SUPPORT_MC_LS | 1236 AMD_CG_SUPPORT_IH_CG | 1237 AMD_CG_SUPPORT_VCN_MGCG | 1238 AMD_CG_SUPPORT_JPEG_MGCG; 1239 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; 1240 adev->external_rev_id = adev->rev_id + 0x32; 1241 break; 1242 case CHIP_RENOIR: 1243 adev->asic_funcs = &soc15_asic_funcs; 1244 adev->apu_flags |= AMD_APU_IS_RENOIR; 1245 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1246 AMD_CG_SUPPORT_GFX_MGLS | 1247 AMD_CG_SUPPORT_GFX_3D_CGCG | 1248 AMD_CG_SUPPORT_GFX_3D_CGLS | 1249 AMD_CG_SUPPORT_GFX_CGCG | 1250 AMD_CG_SUPPORT_GFX_CGLS | 1251 AMD_CG_SUPPORT_GFX_CP_LS | 1252 AMD_CG_SUPPORT_MC_MGCG | 1253 AMD_CG_SUPPORT_MC_LS | 1254 AMD_CG_SUPPORT_SDMA_MGCG | 1255 AMD_CG_SUPPORT_SDMA_LS | 1256 AMD_CG_SUPPORT_BIF_LS | 1257 AMD_CG_SUPPORT_HDP_LS | 1258 AMD_CG_SUPPORT_ROM_MGCG | 1259 AMD_CG_SUPPORT_VCN_MGCG | 1260 AMD_CG_SUPPORT_JPEG_MGCG | 1261 AMD_CG_SUPPORT_IH_CG | 1262 AMD_CG_SUPPORT_ATHUB_LS | 1263 AMD_CG_SUPPORT_ATHUB_MGCG | 1264 AMD_CG_SUPPORT_DF_MGCG; 1265 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1266 AMD_PG_SUPPORT_VCN | 1267 AMD_PG_SUPPORT_JPEG | 1268 AMD_PG_SUPPORT_VCN_DPG; 1269 adev->external_rev_id = adev->rev_id + 0x91; 1270 break; 1271 default: 1272 /* FIXME: not supported yet */ 1273 return -EINVAL; 1274 } 1275 1276 if (amdgpu_sriov_vf(adev)) { 1277 amdgpu_virt_init_setting(adev); 1278 xgpu_ai_mailbox_set_irq_funcs(adev); 1279 } 1280 1281 return 0; 1282 } 1283 1284 static int soc15_common_late_init(void *handle) 1285 { 1286 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1287 int r = 0; 1288 1289 if (amdgpu_sriov_vf(adev)) 1290 xgpu_ai_mailbox_get_irq(adev); 1291 1292 if (adev->asic_funcs && 1293 adev->asic_funcs->reset_hdp_ras_error_count) 1294 adev->asic_funcs->reset_hdp_ras_error_count(adev); 1295 1296 if (adev->nbio.funcs->ras_late_init) 1297 r = adev->nbio.funcs->ras_late_init(adev); 1298 1299 return r; 1300 } 1301 1302 static int soc15_common_sw_init(void *handle) 1303 { 1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1305 1306 if (amdgpu_sriov_vf(adev)) 1307 xgpu_ai_mailbox_add_irq_id(adev); 1308 1309 adev->df.funcs->sw_init(adev); 1310 1311 return 0; 1312 } 1313 1314 static int soc15_common_sw_fini(void *handle) 1315 { 1316 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1317 1318 amdgpu_nbio_ras_fini(adev); 1319 adev->df.funcs->sw_fini(adev); 1320 return 0; 1321 } 1322 1323 static void soc15_doorbell_range_init(struct amdgpu_device *adev) 1324 { 1325 int i; 1326 struct amdgpu_ring *ring; 1327 1328 /* sdma/ih doorbell range are programed by hypervisor */ 1329 if (!amdgpu_sriov_vf(adev)) { 1330 for (i = 0; i < adev->sdma.num_instances; i++) { 1331 ring = &adev->sdma.instance[i].ring; 1332 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1333 ring->use_doorbell, ring->doorbell_index, 1334 adev->doorbell_index.sdma_doorbell_range); 1335 } 1336 1337 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 1338 adev->irq.ih.doorbell_index); 1339 } 1340 } 1341 1342 static int soc15_common_hw_init(void *handle) 1343 { 1344 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1345 1346 /* enable pcie gen2/3 link */ 1347 soc15_pcie_gen3_enable(adev); 1348 /* enable aspm */ 1349 soc15_program_aspm(adev); 1350 /* setup nbio registers */ 1351 adev->nbio.funcs->init_registers(adev); 1352 /* remap HDP registers to a hole in mmio space, 1353 * for the purpose of expose those registers 1354 * to process space 1355 */ 1356 if (adev->nbio.funcs->remap_hdp_registers) 1357 adev->nbio.funcs->remap_hdp_registers(adev); 1358 1359 /* enable the doorbell aperture */ 1360 soc15_enable_doorbell_aperture(adev, true); 1361 /* HW doorbell routing policy: doorbell writing not 1362 * in SDMA/IH/MM/ACV range will be routed to CP. So 1363 * we need to init SDMA/IH/MM/ACV doorbell range prior 1364 * to CP ip block init and ring test. 1365 */ 1366 soc15_doorbell_range_init(adev); 1367 1368 return 0; 1369 } 1370 1371 static int soc15_common_hw_fini(void *handle) 1372 { 1373 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1374 1375 /* disable the doorbell aperture */ 1376 soc15_enable_doorbell_aperture(adev, false); 1377 if (amdgpu_sriov_vf(adev)) 1378 xgpu_ai_mailbox_put_irq(adev); 1379 1380 if (adev->nbio.ras_if && 1381 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1382 if (adev->nbio.funcs->init_ras_controller_interrupt) 1383 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1384 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) 1385 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1386 } 1387 1388 return 0; 1389 } 1390 1391 static int soc15_common_suspend(void *handle) 1392 { 1393 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1394 1395 return soc15_common_hw_fini(adev); 1396 } 1397 1398 static int soc15_common_resume(void *handle) 1399 { 1400 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1401 1402 return soc15_common_hw_init(adev); 1403 } 1404 1405 static bool soc15_common_is_idle(void *handle) 1406 { 1407 return true; 1408 } 1409 1410 static int soc15_common_wait_for_idle(void *handle) 1411 { 1412 return 0; 1413 } 1414 1415 static int soc15_common_soft_reset(void *handle) 1416 { 1417 return 0; 1418 } 1419 1420 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) 1421 { 1422 uint32_t def, data; 1423 1424 if (adev->asic_type == CHIP_VEGA20 || 1425 adev->asic_type == CHIP_ARCTURUS) { 1426 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); 1427 1428 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1429 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1430 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1431 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1432 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; 1433 else 1434 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1435 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1436 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1437 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); 1438 1439 if (def != data) 1440 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); 1441 } else { 1442 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1443 1444 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1445 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1446 else 1447 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1448 1449 if (def != data) 1450 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 1451 } 1452 } 1453 1454 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1455 { 1456 uint32_t def, data; 1457 1458 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1459 1460 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1461 data &= ~(0x01000000 | 1462 0x02000000 | 1463 0x04000000 | 1464 0x08000000 | 1465 0x10000000 | 1466 0x20000000 | 1467 0x40000000 | 1468 0x80000000); 1469 else 1470 data |= (0x01000000 | 1471 0x02000000 | 1472 0x04000000 | 1473 0x08000000 | 1474 0x10000000 | 1475 0x20000000 | 1476 0x40000000 | 1477 0x80000000); 1478 1479 if (def != data) 1480 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1481 } 1482 1483 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1484 { 1485 uint32_t def, data; 1486 1487 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1488 1489 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1490 data |= 1; 1491 else 1492 data &= ~1; 1493 1494 if (def != data) 1495 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1496 } 1497 1498 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1499 bool enable) 1500 { 1501 uint32_t def, data; 1502 1503 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1504 1505 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1506 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1507 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1508 else 1509 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1510 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1511 1512 if (def != data) 1513 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); 1514 } 1515 1516 static int soc15_common_set_clockgating_state(void *handle, 1517 enum amd_clockgating_state state) 1518 { 1519 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1520 1521 if (amdgpu_sriov_vf(adev)) 1522 return 0; 1523 1524 switch (adev->asic_type) { 1525 case CHIP_VEGA10: 1526 case CHIP_VEGA12: 1527 case CHIP_VEGA20: 1528 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1529 state == AMD_CG_STATE_GATE); 1530 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1531 state == AMD_CG_STATE_GATE); 1532 soc15_update_hdp_light_sleep(adev, 1533 state == AMD_CG_STATE_GATE); 1534 soc15_update_drm_clock_gating(adev, 1535 state == AMD_CG_STATE_GATE); 1536 soc15_update_drm_light_sleep(adev, 1537 state == AMD_CG_STATE_GATE); 1538 soc15_update_rom_medium_grain_clock_gating(adev, 1539 state == AMD_CG_STATE_GATE); 1540 adev->df.funcs->update_medium_grain_clock_gating(adev, 1541 state == AMD_CG_STATE_GATE); 1542 break; 1543 case CHIP_RAVEN: 1544 case CHIP_RENOIR: 1545 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1546 state == AMD_CG_STATE_GATE); 1547 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1548 state == AMD_CG_STATE_GATE); 1549 soc15_update_hdp_light_sleep(adev, 1550 state == AMD_CG_STATE_GATE); 1551 soc15_update_drm_clock_gating(adev, 1552 state == AMD_CG_STATE_GATE); 1553 soc15_update_drm_light_sleep(adev, 1554 state == AMD_CG_STATE_GATE); 1555 soc15_update_rom_medium_grain_clock_gating(adev, 1556 state == AMD_CG_STATE_GATE); 1557 break; 1558 case CHIP_ARCTURUS: 1559 soc15_update_hdp_light_sleep(adev, 1560 state == AMD_CG_STATE_GATE); 1561 break; 1562 default: 1563 break; 1564 } 1565 return 0; 1566 } 1567 1568 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1569 { 1570 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1571 int data; 1572 1573 if (amdgpu_sriov_vf(adev)) 1574 *flags = 0; 1575 1576 adev->nbio.funcs->get_clockgating_state(adev, flags); 1577 1578 /* AMD_CG_SUPPORT_HDP_LS */ 1579 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1580 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 1581 *flags |= AMD_CG_SUPPORT_HDP_LS; 1582 1583 /* AMD_CG_SUPPORT_DRM_MGCG */ 1584 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1585 if (!(data & 0x01000000)) 1586 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1587 1588 /* AMD_CG_SUPPORT_DRM_LS */ 1589 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1590 if (data & 0x1) 1591 *flags |= AMD_CG_SUPPORT_DRM_LS; 1592 1593 /* AMD_CG_SUPPORT_ROM_MGCG */ 1594 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1595 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 1596 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 1597 1598 adev->df.funcs->get_clockgating_state(adev, flags); 1599 } 1600 1601 static int soc15_common_set_powergating_state(void *handle, 1602 enum amd_powergating_state state) 1603 { 1604 /* todo */ 1605 return 0; 1606 } 1607 1608 const struct amd_ip_funcs soc15_common_ip_funcs = { 1609 .name = "soc15_common", 1610 .early_init = soc15_common_early_init, 1611 .late_init = soc15_common_late_init, 1612 .sw_init = soc15_common_sw_init, 1613 .sw_fini = soc15_common_sw_fini, 1614 .hw_init = soc15_common_hw_init, 1615 .hw_fini = soc15_common_hw_fini, 1616 .suspend = soc15_common_suspend, 1617 .resume = soc15_common_resume, 1618 .is_idle = soc15_common_is_idle, 1619 .wait_for_idle = soc15_common_wait_for_idle, 1620 .soft_reset = soc15_common_soft_reset, 1621 .set_clockgating_state = soc15_common_set_clockgating_state, 1622 .set_powergating_state = soc15_common_set_powergating_state, 1623 .get_clockgating_state= soc15_common_get_clockgating_state, 1624 }; 1625