1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "atom.h" 36 #include "amd_pcie.h" 37 38 #include "uvd/uvd_7_0_offset.h" 39 #include "gc/gc_9_0_offset.h" 40 #include "gc/gc_9_0_sh_mask.h" 41 #include "sdma0/sdma0_4_0_offset.h" 42 #include "sdma1/sdma1_4_0_offset.h" 43 #include "hdp/hdp_4_0_offset.h" 44 #include "hdp/hdp_4_0_sh_mask.h" 45 #include "smuio/smuio_9_0_offset.h" 46 #include "smuio/smuio_9_0_sh_mask.h" 47 #include "nbio/nbio_7_0_default.h" 48 #include "nbio/nbio_7_0_offset.h" 49 #include "nbio/nbio_7_0_sh_mask.h" 50 #include "nbio/nbio_7_0_smn.h" 51 #include "mp/mp_9_0_offset.h" 52 53 #include "soc15.h" 54 #include "soc15_common.h" 55 #include "gfx_v9_0.h" 56 #include "gmc_v9_0.h" 57 #include "gfxhub_v1_0.h" 58 #include "mmhub_v1_0.h" 59 #include "df_v1_7.h" 60 #include "df_v3_6.h" 61 #include "nbio_v6_1.h" 62 #include "nbio_v7_0.h" 63 #include "nbio_v7_4.h" 64 #include "vega10_ih.h" 65 #include "sdma_v4_0.h" 66 #include "uvd_v7_0.h" 67 #include "vce_v4_0.h" 68 #include "vcn_v1_0.h" 69 #include "vcn_v2_0.h" 70 #include "jpeg_v2_0.h" 71 #include "vcn_v2_5.h" 72 #include "jpeg_v2_5.h" 73 #include "dce_virtual.h" 74 #include "mxgpu_ai.h" 75 #include "amdgpu_smu.h" 76 #include "amdgpu_ras.h" 77 #include "amdgpu_xgmi.h" 78 #include <uapi/linux/kfd_ioctl.h> 79 80 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 81 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 82 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 83 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 84 85 /* for Vega20 register name change */ 86 #define mmHDP_MEM_POWER_CTRL 0x00d4 87 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L 88 #define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L 89 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L 90 #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L 91 #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 92 /* 93 * Indirect registers accessor 94 */ 95 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) 96 { 97 unsigned long flags, address, data; 98 u32 r; 99 address = adev->nbio.funcs->get_pcie_index_offset(adev); 100 data = adev->nbio.funcs->get_pcie_data_offset(adev); 101 102 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 103 WREG32(address, reg); 104 (void)RREG32(address); 105 r = RREG32(data); 106 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 107 return r; 108 } 109 110 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 111 { 112 unsigned long flags, address, data; 113 114 address = adev->nbio.funcs->get_pcie_index_offset(adev); 115 data = adev->nbio.funcs->get_pcie_data_offset(adev); 116 117 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 118 WREG32(address, reg); 119 (void)RREG32(address); 120 WREG32(data, v); 121 (void)RREG32(data); 122 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 123 } 124 125 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 126 { 127 unsigned long flags, address, data; 128 u64 r; 129 address = adev->nbio.funcs->get_pcie_index_offset(adev); 130 data = adev->nbio.funcs->get_pcie_data_offset(adev); 131 132 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 133 /* read low 32 bit */ 134 WREG32(address, reg); 135 (void)RREG32(address); 136 r = RREG32(data); 137 138 /* read high 32 bit*/ 139 WREG32(address, reg + 4); 140 (void)RREG32(address); 141 r |= ((u64)RREG32(data) << 32); 142 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 143 return r; 144 } 145 146 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 147 { 148 unsigned long flags, address, data; 149 150 address = adev->nbio.funcs->get_pcie_index_offset(adev); 151 data = adev->nbio.funcs->get_pcie_data_offset(adev); 152 153 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 154 /* write low 32 bit */ 155 WREG32(address, reg); 156 (void)RREG32(address); 157 WREG32(data, (u32)(v & 0xffffffffULL)); 158 (void)RREG32(data); 159 160 /* write high 32 bit */ 161 WREG32(address, reg + 4); 162 (void)RREG32(address); 163 WREG32(data, (u32)(v >> 32)); 164 (void)RREG32(data); 165 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 166 } 167 168 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 169 { 170 unsigned long flags, address, data; 171 u32 r; 172 173 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 174 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 175 176 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 177 WREG32(address, ((reg) & 0x1ff)); 178 r = RREG32(data); 179 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 180 return r; 181 } 182 183 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 184 { 185 unsigned long flags, address, data; 186 187 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 188 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 189 190 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 191 WREG32(address, ((reg) & 0x1ff)); 192 WREG32(data, (v)); 193 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 194 } 195 196 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 197 { 198 unsigned long flags, address, data; 199 u32 r; 200 201 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 202 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 203 204 spin_lock_irqsave(&adev->didt_idx_lock, flags); 205 WREG32(address, (reg)); 206 r = RREG32(data); 207 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 208 return r; 209 } 210 211 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 212 { 213 unsigned long flags, address, data; 214 215 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 216 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 217 218 spin_lock_irqsave(&adev->didt_idx_lock, flags); 219 WREG32(address, (reg)); 220 WREG32(data, (v)); 221 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 222 } 223 224 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 225 { 226 unsigned long flags; 227 u32 r; 228 229 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 230 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 231 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 232 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 233 return r; 234 } 235 236 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 237 { 238 unsigned long flags; 239 240 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 241 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 242 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 243 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 244 } 245 246 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 247 { 248 unsigned long flags; 249 u32 r; 250 251 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 252 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 253 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 254 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 255 return r; 256 } 257 258 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 259 { 260 unsigned long flags; 261 262 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 263 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 264 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 265 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 266 } 267 268 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 269 { 270 return adev->nbio.funcs->get_memsize(adev); 271 } 272 273 static u32 soc15_get_xclk(struct amdgpu_device *adev) 274 { 275 return adev->clock.spll.reference_freq; 276 } 277 278 279 void soc15_grbm_select(struct amdgpu_device *adev, 280 u32 me, u32 pipe, u32 queue, u32 vmid) 281 { 282 u32 grbm_gfx_cntl = 0; 283 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 284 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 285 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 286 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 287 288 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 289 } 290 291 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state) 292 { 293 /* todo */ 294 } 295 296 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 297 { 298 /* todo */ 299 return false; 300 } 301 302 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev, 303 u8 *bios, u32 length_bytes) 304 { 305 u32 *dw_ptr; 306 u32 i, length_dw; 307 308 if (bios == NULL) 309 return false; 310 if (length_bytes == 0) 311 return false; 312 /* APU vbios image is part of sbios image */ 313 if (adev->flags & AMD_IS_APU) 314 return false; 315 316 dw_ptr = (u32 *)bios; 317 length_dw = ALIGN(length_bytes, 4) / 4; 318 319 /* set rom index to 0 */ 320 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 321 /* read out the rom data */ 322 for (i = 0; i < length_dw; i++) 323 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 324 325 return true; 326 } 327 328 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 329 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 330 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 331 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 332 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 333 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 334 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 335 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 336 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 337 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 338 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 339 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 340 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 341 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 342 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 343 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 344 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 345 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 346 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 347 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 348 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 349 }; 350 351 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 352 u32 sh_num, u32 reg_offset) 353 { 354 uint32_t val; 355 356 mutex_lock(&adev->grbm_idx_mutex); 357 if (se_num != 0xffffffff || sh_num != 0xffffffff) 358 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 359 360 val = RREG32(reg_offset); 361 362 if (se_num != 0xffffffff || sh_num != 0xffffffff) 363 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 364 mutex_unlock(&adev->grbm_idx_mutex); 365 return val; 366 } 367 368 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 369 bool indexed, u32 se_num, 370 u32 sh_num, u32 reg_offset) 371 { 372 if (indexed) { 373 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 374 } else { 375 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 376 return adev->gfx.config.gb_addr_config; 377 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 378 return adev->gfx.config.db_debug2; 379 return RREG32(reg_offset); 380 } 381 } 382 383 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 384 u32 sh_num, u32 reg_offset, u32 *value) 385 { 386 uint32_t i; 387 struct soc15_allowed_register_entry *en; 388 389 *value = 0; 390 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 391 en = &soc15_allowed_read_registers[i]; 392 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 393 + en->reg_offset)) 394 continue; 395 396 *value = soc15_get_register_value(adev, 397 soc15_allowed_read_registers[i].grbm_indexed, 398 se_num, sh_num, reg_offset); 399 return 0; 400 } 401 return -EINVAL; 402 } 403 404 405 /** 406 * soc15_program_register_sequence - program an array of registers. 407 * 408 * @adev: amdgpu_device pointer 409 * @regs: pointer to the register array 410 * @array_size: size of the register array 411 * 412 * Programs an array or registers with and and or masks. 413 * This is a helper for setting golden registers. 414 */ 415 416 void soc15_program_register_sequence(struct amdgpu_device *adev, 417 const struct soc15_reg_golden *regs, 418 const u32 array_size) 419 { 420 const struct soc15_reg_golden *entry; 421 u32 tmp, reg; 422 int i; 423 424 for (i = 0; i < array_size; ++i) { 425 entry = ®s[i]; 426 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 427 428 if (entry->and_mask == 0xffffffff) { 429 tmp = entry->or_mask; 430 } else { 431 tmp = RREG32(reg); 432 tmp &= ~(entry->and_mask); 433 tmp |= (entry->or_mask & entry->and_mask); 434 } 435 436 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 437 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 438 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 439 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 440 WREG32_RLC(reg, tmp); 441 else 442 WREG32(reg, tmp); 443 444 } 445 446 } 447 448 static int soc15_asic_mode1_reset(struct amdgpu_device *adev) 449 { 450 u32 i; 451 int ret = 0; 452 453 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 454 455 dev_info(adev->dev, "GPU mode1 reset\n"); 456 457 /* disable BM */ 458 pci_clear_master(adev->pdev); 459 460 pci_save_state(adev->pdev); 461 462 ret = psp_gpu_reset(adev); 463 if (ret) 464 dev_err(adev->dev, "GPU mode1 reset failed\n"); 465 466 pci_restore_state(adev->pdev); 467 468 /* wait for asic to come out of reset */ 469 for (i = 0; i < adev->usec_timeout; i++) { 470 u32 memsize = adev->nbio.funcs->get_memsize(adev); 471 472 if (memsize != 0xffffffff) 473 break; 474 udelay(1); 475 } 476 477 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 478 479 return ret; 480 } 481 482 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 483 { 484 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 485 int ret = 0; 486 487 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 488 if (ras && ras->supported) 489 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 490 491 ret = amdgpu_dpm_baco_reset(adev); 492 if (ret) 493 return ret; 494 495 /* re-enable doorbell interrupt after BACO exit */ 496 if (ras && ras->supported) 497 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 498 499 return 0; 500 } 501 502 static enum amd_reset_method 503 soc15_asic_reset_method(struct amdgpu_device *adev) 504 { 505 bool baco_reset = false; 506 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 507 508 switch (adev->asic_type) { 509 case CHIP_RAVEN: 510 case CHIP_RENOIR: 511 return AMD_RESET_METHOD_MODE2; 512 case CHIP_VEGA10: 513 case CHIP_VEGA12: 514 case CHIP_ARCTURUS: 515 baco_reset = amdgpu_dpm_is_baco_supported(adev); 516 break; 517 case CHIP_VEGA20: 518 if (adev->psp.sos_fw_version >= 0x80067) 519 baco_reset = amdgpu_dpm_is_baco_supported(adev); 520 521 /* 522 * 1. PMFW version > 0x284300: all cases use baco 523 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 524 */ 525 if ((ras && ras->supported) && adev->pm.fw_version <= 0x283400) 526 baco_reset = false; 527 break; 528 default: 529 break; 530 } 531 532 if (baco_reset) 533 return AMD_RESET_METHOD_BACO; 534 else 535 return AMD_RESET_METHOD_MODE1; 536 } 537 538 static int soc15_asic_reset(struct amdgpu_device *adev) 539 { 540 /* original raven doesn't have full asic reset */ 541 if (adev->pdev->device == 0x15dd && adev->rev_id < 0x8) 542 return 0; 543 544 switch (soc15_asic_reset_method(adev)) { 545 case AMD_RESET_METHOD_BACO: 546 if (!adev->in_suspend) 547 amdgpu_inc_vram_lost(adev); 548 return soc15_asic_baco_reset(adev); 549 case AMD_RESET_METHOD_MODE2: 550 return amdgpu_dpm_mode2_reset(adev); 551 default: 552 if (!adev->in_suspend) 553 amdgpu_inc_vram_lost(adev); 554 return soc15_asic_mode1_reset(adev); 555 } 556 } 557 558 static bool soc15_supports_baco(struct amdgpu_device *adev) 559 { 560 switch (adev->asic_type) { 561 case CHIP_VEGA10: 562 case CHIP_VEGA12: 563 case CHIP_ARCTURUS: 564 return amdgpu_dpm_is_baco_supported(adev); 565 case CHIP_VEGA20: 566 if (adev->psp.sos_fw_version >= 0x80067) 567 return amdgpu_dpm_is_baco_supported(adev); 568 return false; 569 default: 570 return false; 571 } 572 } 573 574 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 575 u32 cntl_reg, u32 status_reg) 576 { 577 return 0; 578 }*/ 579 580 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 581 { 582 /*int r; 583 584 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 585 if (r) 586 return r; 587 588 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 589 */ 590 return 0; 591 } 592 593 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 594 { 595 /* todo */ 596 597 return 0; 598 } 599 600 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev) 601 { 602 if (pci_is_root_bus(adev->pdev->bus)) 603 return; 604 605 if (amdgpu_pcie_gen2 == 0) 606 return; 607 608 if (adev->flags & AMD_IS_APU) 609 return; 610 611 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 612 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 613 return; 614 615 /* todo */ 616 } 617 618 static void soc15_program_aspm(struct amdgpu_device *adev) 619 { 620 621 if (amdgpu_aspm == 0) 622 return; 623 624 /* todo */ 625 } 626 627 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev, 628 bool enable) 629 { 630 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 631 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 632 } 633 634 static const struct amdgpu_ip_block_version vega10_common_ip_block = 635 { 636 .type = AMD_IP_BLOCK_TYPE_COMMON, 637 .major = 2, 638 .minor = 0, 639 .rev = 0, 640 .funcs = &soc15_common_ip_funcs, 641 }; 642 643 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev) 644 { 645 return adev->nbio.funcs->get_rev_id(adev); 646 } 647 648 int soc15_set_ip_blocks(struct amdgpu_device *adev) 649 { 650 /* Set IP register base before any HW register access */ 651 switch (adev->asic_type) { 652 case CHIP_VEGA10: 653 case CHIP_VEGA12: 654 case CHIP_RAVEN: 655 case CHIP_RENOIR: 656 vega10_reg_base_init(adev); 657 break; 658 case CHIP_VEGA20: 659 vega20_reg_base_init(adev); 660 break; 661 case CHIP_ARCTURUS: 662 arct_reg_base_init(adev); 663 break; 664 default: 665 return -EINVAL; 666 } 667 668 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 669 adev->gmc.xgmi.supported = true; 670 671 if (adev->flags & AMD_IS_APU) { 672 adev->nbio.funcs = &nbio_v7_0_funcs; 673 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 674 } else if (adev->asic_type == CHIP_VEGA20 || 675 adev->asic_type == CHIP_ARCTURUS) { 676 adev->nbio.funcs = &nbio_v7_4_funcs; 677 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 678 } else { 679 adev->nbio.funcs = &nbio_v6_1_funcs; 680 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 681 } 682 683 if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS) 684 adev->df.funcs = &df_v3_6_funcs; 685 else 686 adev->df.funcs = &df_v1_7_funcs; 687 688 adev->rev_id = soc15_get_rev_id(adev); 689 adev->nbio.funcs->detect_hw_virt(adev); 690 691 if (amdgpu_sriov_vf(adev)) 692 adev->virt.ops = &xgpu_ai_virt_ops; 693 694 switch (adev->asic_type) { 695 case CHIP_VEGA10: 696 case CHIP_VEGA12: 697 case CHIP_VEGA20: 698 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 699 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 700 701 /* For Vega10 SR-IOV, PSP need to be initialized before IH */ 702 if (amdgpu_sriov_vf(adev)) { 703 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 704 if (adev->asic_type == CHIP_VEGA20) 705 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 706 else 707 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 708 } 709 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 710 } else { 711 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 712 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 713 if (adev->asic_type == CHIP_VEGA20) 714 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 715 else 716 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 717 } 718 } 719 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 720 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 721 if (is_support_sw_smu(adev)) { 722 if (!amdgpu_sriov_vf(adev)) 723 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 724 } else { 725 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 726 } 727 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 728 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 729 #if defined(CONFIG_DRM_AMD_DC) 730 else if (amdgpu_device_has_dc_support(adev)) 731 amdgpu_device_ip_block_add(adev, &dm_ip_block); 732 #endif 733 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) { 734 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 735 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 736 } 737 break; 738 case CHIP_RAVEN: 739 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 740 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 741 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 742 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 743 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 744 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 745 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 746 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 747 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 748 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 749 #if defined(CONFIG_DRM_AMD_DC) 750 else if (amdgpu_device_has_dc_support(adev)) 751 amdgpu_device_ip_block_add(adev, &dm_ip_block); 752 #endif 753 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 754 break; 755 case CHIP_ARCTURUS: 756 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 757 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 758 759 if (amdgpu_sriov_vf(adev)) { 760 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 761 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 762 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 763 } else { 764 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 765 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 766 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 767 } 768 769 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 770 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 771 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 772 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 773 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 774 775 if (amdgpu_sriov_vf(adev)) { 776 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 777 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 778 } else { 779 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 780 } 781 if (!amdgpu_sriov_vf(adev)) 782 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 783 break; 784 case CHIP_RENOIR: 785 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 786 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 787 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 788 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 789 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 790 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 791 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 792 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 793 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 794 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 795 #if defined(CONFIG_DRM_AMD_DC) 796 else if (amdgpu_device_has_dc_support(adev)) 797 amdgpu_device_ip_block_add(adev, &dm_ip_block); 798 #endif 799 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 800 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 801 break; 802 default: 803 return -EINVAL; 804 } 805 806 return 0; 807 } 808 809 static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 810 { 811 adev->nbio.funcs->hdp_flush(adev, ring); 812 } 813 814 static void soc15_invalidate_hdp(struct amdgpu_device *adev, 815 struct amdgpu_ring *ring) 816 { 817 if (!ring || !ring->funcs->emit_wreg) 818 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 819 else 820 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 821 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 822 } 823 824 static bool soc15_need_full_reset(struct amdgpu_device *adev) 825 { 826 /* change this when we implement soft reset */ 827 return true; 828 } 829 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 830 uint64_t *count1) 831 { 832 uint32_t perfctr = 0; 833 uint64_t cnt0_of, cnt1_of; 834 int tmp; 835 836 /* This reports 0 on APUs, so return to avoid writing/reading registers 837 * that may or may not be different from their GPU counterparts 838 */ 839 if (adev->flags & AMD_IS_APU) 840 return; 841 842 /* Set the 2 events that we wish to watch, defined above */ 843 /* Reg 40 is # received msgs */ 844 /* Reg 104 is # of posted requests sent */ 845 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 846 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 847 848 /* Write to enable desired perf counters */ 849 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 850 /* Zero out and enable the perf counters 851 * Write 0x5: 852 * Bit 0 = Start all counters(1) 853 * Bit 2 = Global counter reset enable(1) 854 */ 855 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 856 857 msleep(1000); 858 859 /* Load the shadow and disable the perf counters 860 * Write 0x2: 861 * Bit 0 = Stop counters(0) 862 * Bit 1 = Load the shadow counters(1) 863 */ 864 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 865 866 /* Read register values to get any >32bit overflow */ 867 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 868 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 869 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 870 871 /* Get the values and add the overflow */ 872 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 873 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 874 } 875 876 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 877 uint64_t *count1) 878 { 879 uint32_t perfctr = 0; 880 uint64_t cnt0_of, cnt1_of; 881 int tmp; 882 883 /* This reports 0 on APUs, so return to avoid writing/reading registers 884 * that may or may not be different from their GPU counterparts 885 */ 886 if (adev->flags & AMD_IS_APU) 887 return; 888 889 /* Set the 2 events that we wish to watch, defined above */ 890 /* Reg 40 is # received msgs */ 891 /* Reg 108 is # of posted requests sent on VG20 */ 892 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 893 EVENT0_SEL, 40); 894 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 895 EVENT1_SEL, 108); 896 897 /* Write to enable desired perf counters */ 898 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 899 /* Zero out and enable the perf counters 900 * Write 0x5: 901 * Bit 0 = Start all counters(1) 902 * Bit 2 = Global counter reset enable(1) 903 */ 904 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 905 906 msleep(1000); 907 908 /* Load the shadow and disable the perf counters 909 * Write 0x2: 910 * Bit 0 = Stop counters(0) 911 * Bit 1 = Load the shadow counters(1) 912 */ 913 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 914 915 /* Read register values to get any >32bit overflow */ 916 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 917 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 918 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 919 920 /* Get the values and add the overflow */ 921 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 922 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 923 } 924 925 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 926 { 927 u32 sol_reg; 928 929 /* Just return false for soc15 GPUs. Reset does not seem to 930 * be necessary. 931 */ 932 if (!amdgpu_passthrough(adev)) 933 return false; 934 935 if (adev->flags & AMD_IS_APU) 936 return false; 937 938 /* Check sOS sign of life register to confirm sys driver and sOS 939 * are already been loaded. 940 */ 941 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 942 if (sol_reg) 943 return true; 944 945 return false; 946 } 947 948 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 949 { 950 uint64_t nak_r, nak_g; 951 952 /* Get the number of NAKs received and generated */ 953 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 954 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 955 956 /* Add the total number of NAKs, i.e the number of replays */ 957 return (nak_r + nak_g); 958 } 959 960 static const struct amdgpu_asic_funcs soc15_asic_funcs = 961 { 962 .read_disabled_bios = &soc15_read_disabled_bios, 963 .read_bios_from_rom = &soc15_read_bios_from_rom, 964 .read_register = &soc15_read_register, 965 .reset = &soc15_asic_reset, 966 .reset_method = &soc15_asic_reset_method, 967 .set_vga_state = &soc15_vga_set_state, 968 .get_xclk = &soc15_get_xclk, 969 .set_uvd_clocks = &soc15_set_uvd_clocks, 970 .set_vce_clocks = &soc15_set_vce_clocks, 971 .get_config_memsize = &soc15_get_config_memsize, 972 .flush_hdp = &soc15_flush_hdp, 973 .invalidate_hdp = &soc15_invalidate_hdp, 974 .need_full_reset = &soc15_need_full_reset, 975 .init_doorbell_index = &vega10_doorbell_index_init, 976 .get_pcie_usage = &soc15_get_pcie_usage, 977 .need_reset_on_init = &soc15_need_reset_on_init, 978 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 979 .supports_baco = &soc15_supports_baco, 980 }; 981 982 static const struct amdgpu_asic_funcs vega20_asic_funcs = 983 { 984 .read_disabled_bios = &soc15_read_disabled_bios, 985 .read_bios_from_rom = &soc15_read_bios_from_rom, 986 .read_register = &soc15_read_register, 987 .reset = &soc15_asic_reset, 988 .reset_method = &soc15_asic_reset_method, 989 .set_vga_state = &soc15_vga_set_state, 990 .get_xclk = &soc15_get_xclk, 991 .set_uvd_clocks = &soc15_set_uvd_clocks, 992 .set_vce_clocks = &soc15_set_vce_clocks, 993 .get_config_memsize = &soc15_get_config_memsize, 994 .flush_hdp = &soc15_flush_hdp, 995 .invalidate_hdp = &soc15_invalidate_hdp, 996 .need_full_reset = &soc15_need_full_reset, 997 .init_doorbell_index = &vega20_doorbell_index_init, 998 .get_pcie_usage = &vega20_get_pcie_usage, 999 .need_reset_on_init = &soc15_need_reset_on_init, 1000 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 1001 .supports_baco = &soc15_supports_baco, 1002 }; 1003 1004 static int soc15_common_early_init(void *handle) 1005 { 1006 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 1007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1008 1009 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 1010 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 1011 adev->smc_rreg = NULL; 1012 adev->smc_wreg = NULL; 1013 adev->pcie_rreg = &soc15_pcie_rreg; 1014 adev->pcie_wreg = &soc15_pcie_wreg; 1015 adev->pcie_rreg64 = &soc15_pcie_rreg64; 1016 adev->pcie_wreg64 = &soc15_pcie_wreg64; 1017 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 1018 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 1019 adev->didt_rreg = &soc15_didt_rreg; 1020 adev->didt_wreg = &soc15_didt_wreg; 1021 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 1022 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 1023 adev->se_cac_rreg = &soc15_se_cac_rreg; 1024 adev->se_cac_wreg = &soc15_se_cac_wreg; 1025 1026 1027 adev->external_rev_id = 0xFF; 1028 switch (adev->asic_type) { 1029 case CHIP_VEGA10: 1030 adev->asic_funcs = &soc15_asic_funcs; 1031 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1032 AMD_CG_SUPPORT_GFX_MGLS | 1033 AMD_CG_SUPPORT_GFX_RLC_LS | 1034 AMD_CG_SUPPORT_GFX_CP_LS | 1035 AMD_CG_SUPPORT_GFX_3D_CGCG | 1036 AMD_CG_SUPPORT_GFX_3D_CGLS | 1037 AMD_CG_SUPPORT_GFX_CGCG | 1038 AMD_CG_SUPPORT_GFX_CGLS | 1039 AMD_CG_SUPPORT_BIF_MGCG | 1040 AMD_CG_SUPPORT_BIF_LS | 1041 AMD_CG_SUPPORT_HDP_LS | 1042 AMD_CG_SUPPORT_DRM_MGCG | 1043 AMD_CG_SUPPORT_DRM_LS | 1044 AMD_CG_SUPPORT_ROM_MGCG | 1045 AMD_CG_SUPPORT_DF_MGCG | 1046 AMD_CG_SUPPORT_SDMA_MGCG | 1047 AMD_CG_SUPPORT_SDMA_LS | 1048 AMD_CG_SUPPORT_MC_MGCG | 1049 AMD_CG_SUPPORT_MC_LS; 1050 adev->pg_flags = 0; 1051 adev->external_rev_id = 0x1; 1052 break; 1053 case CHIP_VEGA12: 1054 adev->asic_funcs = &soc15_asic_funcs; 1055 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1056 AMD_CG_SUPPORT_GFX_MGLS | 1057 AMD_CG_SUPPORT_GFX_CGCG | 1058 AMD_CG_SUPPORT_GFX_CGLS | 1059 AMD_CG_SUPPORT_GFX_3D_CGCG | 1060 AMD_CG_SUPPORT_GFX_3D_CGLS | 1061 AMD_CG_SUPPORT_GFX_CP_LS | 1062 AMD_CG_SUPPORT_MC_LS | 1063 AMD_CG_SUPPORT_MC_MGCG | 1064 AMD_CG_SUPPORT_SDMA_MGCG | 1065 AMD_CG_SUPPORT_SDMA_LS | 1066 AMD_CG_SUPPORT_BIF_MGCG | 1067 AMD_CG_SUPPORT_BIF_LS | 1068 AMD_CG_SUPPORT_HDP_MGCG | 1069 AMD_CG_SUPPORT_HDP_LS | 1070 AMD_CG_SUPPORT_ROM_MGCG | 1071 AMD_CG_SUPPORT_VCE_MGCG | 1072 AMD_CG_SUPPORT_UVD_MGCG; 1073 adev->pg_flags = 0; 1074 adev->external_rev_id = adev->rev_id + 0x14; 1075 break; 1076 case CHIP_VEGA20: 1077 adev->asic_funcs = &vega20_asic_funcs; 1078 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1079 AMD_CG_SUPPORT_GFX_MGLS | 1080 AMD_CG_SUPPORT_GFX_CGCG | 1081 AMD_CG_SUPPORT_GFX_CGLS | 1082 AMD_CG_SUPPORT_GFX_3D_CGCG | 1083 AMD_CG_SUPPORT_GFX_3D_CGLS | 1084 AMD_CG_SUPPORT_GFX_CP_LS | 1085 AMD_CG_SUPPORT_MC_LS | 1086 AMD_CG_SUPPORT_MC_MGCG | 1087 AMD_CG_SUPPORT_SDMA_MGCG | 1088 AMD_CG_SUPPORT_SDMA_LS | 1089 AMD_CG_SUPPORT_BIF_MGCG | 1090 AMD_CG_SUPPORT_BIF_LS | 1091 AMD_CG_SUPPORT_HDP_MGCG | 1092 AMD_CG_SUPPORT_HDP_LS | 1093 AMD_CG_SUPPORT_ROM_MGCG | 1094 AMD_CG_SUPPORT_VCE_MGCG | 1095 AMD_CG_SUPPORT_UVD_MGCG; 1096 adev->pg_flags = 0; 1097 adev->external_rev_id = adev->rev_id + 0x28; 1098 break; 1099 case CHIP_RAVEN: 1100 adev->asic_funcs = &soc15_asic_funcs; 1101 if (adev->rev_id >= 0x8) 1102 adev->external_rev_id = adev->rev_id + 0x79; 1103 else if (adev->pdev->device == 0x15d8) 1104 adev->external_rev_id = adev->rev_id + 0x41; 1105 else if (adev->rev_id == 1) 1106 adev->external_rev_id = adev->rev_id + 0x20; 1107 else 1108 adev->external_rev_id = adev->rev_id + 0x01; 1109 1110 if (adev->rev_id >= 0x8) { 1111 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1112 AMD_CG_SUPPORT_GFX_MGLS | 1113 AMD_CG_SUPPORT_GFX_CP_LS | 1114 AMD_CG_SUPPORT_GFX_3D_CGCG | 1115 AMD_CG_SUPPORT_GFX_3D_CGLS | 1116 AMD_CG_SUPPORT_GFX_CGCG | 1117 AMD_CG_SUPPORT_GFX_CGLS | 1118 AMD_CG_SUPPORT_BIF_LS | 1119 AMD_CG_SUPPORT_HDP_LS | 1120 AMD_CG_SUPPORT_ROM_MGCG | 1121 AMD_CG_SUPPORT_MC_MGCG | 1122 AMD_CG_SUPPORT_MC_LS | 1123 AMD_CG_SUPPORT_SDMA_MGCG | 1124 AMD_CG_SUPPORT_SDMA_LS | 1125 AMD_CG_SUPPORT_VCN_MGCG; 1126 1127 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1128 } else if (adev->pdev->device == 0x15d8) { 1129 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1130 AMD_CG_SUPPORT_GFX_MGLS | 1131 AMD_CG_SUPPORT_GFX_CP_LS | 1132 AMD_CG_SUPPORT_GFX_3D_CGCG | 1133 AMD_CG_SUPPORT_GFX_3D_CGLS | 1134 AMD_CG_SUPPORT_GFX_CGCG | 1135 AMD_CG_SUPPORT_GFX_CGLS | 1136 AMD_CG_SUPPORT_BIF_LS | 1137 AMD_CG_SUPPORT_HDP_LS | 1138 AMD_CG_SUPPORT_ROM_MGCG | 1139 AMD_CG_SUPPORT_MC_MGCG | 1140 AMD_CG_SUPPORT_MC_LS | 1141 AMD_CG_SUPPORT_SDMA_MGCG | 1142 AMD_CG_SUPPORT_SDMA_LS; 1143 1144 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1145 AMD_PG_SUPPORT_MMHUB | 1146 AMD_PG_SUPPORT_VCN | 1147 AMD_PG_SUPPORT_VCN_DPG; 1148 } else { 1149 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1150 AMD_CG_SUPPORT_GFX_MGLS | 1151 AMD_CG_SUPPORT_GFX_RLC_LS | 1152 AMD_CG_SUPPORT_GFX_CP_LS | 1153 AMD_CG_SUPPORT_GFX_3D_CGCG | 1154 AMD_CG_SUPPORT_GFX_3D_CGLS | 1155 AMD_CG_SUPPORT_GFX_CGCG | 1156 AMD_CG_SUPPORT_GFX_CGLS | 1157 AMD_CG_SUPPORT_BIF_MGCG | 1158 AMD_CG_SUPPORT_BIF_LS | 1159 AMD_CG_SUPPORT_HDP_MGCG | 1160 AMD_CG_SUPPORT_HDP_LS | 1161 AMD_CG_SUPPORT_DRM_MGCG | 1162 AMD_CG_SUPPORT_DRM_LS | 1163 AMD_CG_SUPPORT_ROM_MGCG | 1164 AMD_CG_SUPPORT_MC_MGCG | 1165 AMD_CG_SUPPORT_MC_LS | 1166 AMD_CG_SUPPORT_SDMA_MGCG | 1167 AMD_CG_SUPPORT_SDMA_LS | 1168 AMD_CG_SUPPORT_VCN_MGCG; 1169 1170 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1171 } 1172 break; 1173 case CHIP_ARCTURUS: 1174 adev->asic_funcs = &vega20_asic_funcs; 1175 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1176 AMD_CG_SUPPORT_GFX_MGLS | 1177 AMD_CG_SUPPORT_GFX_CGCG | 1178 AMD_CG_SUPPORT_GFX_CGLS | 1179 AMD_CG_SUPPORT_GFX_CP_LS | 1180 AMD_CG_SUPPORT_HDP_MGCG | 1181 AMD_CG_SUPPORT_HDP_LS | 1182 AMD_CG_SUPPORT_SDMA_MGCG | 1183 AMD_CG_SUPPORT_SDMA_LS | 1184 AMD_CG_SUPPORT_MC_MGCG | 1185 AMD_CG_SUPPORT_MC_LS | 1186 AMD_CG_SUPPORT_IH_CG | 1187 AMD_CG_SUPPORT_VCN_MGCG | 1188 AMD_CG_SUPPORT_JPEG_MGCG; 1189 adev->pg_flags = 0; 1190 adev->external_rev_id = adev->rev_id + 0x32; 1191 break; 1192 case CHIP_RENOIR: 1193 adev->asic_funcs = &soc15_asic_funcs; 1194 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1195 AMD_CG_SUPPORT_GFX_MGLS | 1196 AMD_CG_SUPPORT_GFX_3D_CGCG | 1197 AMD_CG_SUPPORT_GFX_3D_CGLS | 1198 AMD_CG_SUPPORT_GFX_CGCG | 1199 AMD_CG_SUPPORT_GFX_CGLS | 1200 AMD_CG_SUPPORT_GFX_CP_LS | 1201 AMD_CG_SUPPORT_MC_MGCG | 1202 AMD_CG_SUPPORT_MC_LS | 1203 AMD_CG_SUPPORT_SDMA_MGCG | 1204 AMD_CG_SUPPORT_SDMA_LS | 1205 AMD_CG_SUPPORT_BIF_LS | 1206 AMD_CG_SUPPORT_HDP_LS | 1207 AMD_CG_SUPPORT_ROM_MGCG | 1208 AMD_CG_SUPPORT_VCN_MGCG | 1209 AMD_CG_SUPPORT_JPEG_MGCG | 1210 AMD_CG_SUPPORT_IH_CG | 1211 AMD_CG_SUPPORT_ATHUB_LS | 1212 AMD_CG_SUPPORT_ATHUB_MGCG | 1213 AMD_CG_SUPPORT_DF_MGCG; 1214 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1215 AMD_PG_SUPPORT_VCN | 1216 AMD_PG_SUPPORT_JPEG | 1217 AMD_PG_SUPPORT_VCN_DPG; 1218 adev->external_rev_id = adev->rev_id + 0x91; 1219 break; 1220 default: 1221 /* FIXME: not supported yet */ 1222 return -EINVAL; 1223 } 1224 1225 if (amdgpu_sriov_vf(adev)) { 1226 amdgpu_virt_init_setting(adev); 1227 xgpu_ai_mailbox_set_irq_funcs(adev); 1228 } 1229 1230 return 0; 1231 } 1232 1233 static int soc15_common_late_init(void *handle) 1234 { 1235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1236 int r = 0; 1237 1238 if (amdgpu_sriov_vf(adev)) 1239 xgpu_ai_mailbox_get_irq(adev); 1240 1241 if (adev->nbio.funcs->ras_late_init) 1242 r = adev->nbio.funcs->ras_late_init(adev); 1243 1244 return r; 1245 } 1246 1247 static int soc15_common_sw_init(void *handle) 1248 { 1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1250 1251 if (amdgpu_sriov_vf(adev)) 1252 xgpu_ai_mailbox_add_irq_id(adev); 1253 1254 adev->df.funcs->sw_init(adev); 1255 1256 return 0; 1257 } 1258 1259 static int soc15_common_sw_fini(void *handle) 1260 { 1261 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1262 1263 amdgpu_nbio_ras_fini(adev); 1264 adev->df.funcs->sw_fini(adev); 1265 return 0; 1266 } 1267 1268 static void soc15_doorbell_range_init(struct amdgpu_device *adev) 1269 { 1270 int i; 1271 struct amdgpu_ring *ring; 1272 1273 /* sdma/ih doorbell range are programed by hypervisor */ 1274 if (!amdgpu_sriov_vf(adev)) { 1275 for (i = 0; i < adev->sdma.num_instances; i++) { 1276 ring = &adev->sdma.instance[i].ring; 1277 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1278 ring->use_doorbell, ring->doorbell_index, 1279 adev->doorbell_index.sdma_doorbell_range); 1280 } 1281 1282 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, 1283 adev->irq.ih.doorbell_index); 1284 } 1285 } 1286 1287 static int soc15_common_hw_init(void *handle) 1288 { 1289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1290 1291 /* enable pcie gen2/3 link */ 1292 soc15_pcie_gen3_enable(adev); 1293 /* enable aspm */ 1294 soc15_program_aspm(adev); 1295 /* setup nbio registers */ 1296 adev->nbio.funcs->init_registers(adev); 1297 /* remap HDP registers to a hole in mmio space, 1298 * for the purpose of expose those registers 1299 * to process space 1300 */ 1301 if (adev->nbio.funcs->remap_hdp_registers) 1302 adev->nbio.funcs->remap_hdp_registers(adev); 1303 1304 /* enable the doorbell aperture */ 1305 soc15_enable_doorbell_aperture(adev, true); 1306 /* HW doorbell routing policy: doorbell writing not 1307 * in SDMA/IH/MM/ACV range will be routed to CP. So 1308 * we need to init SDMA/IH/MM/ACV doorbell range prior 1309 * to CP ip block init and ring test. 1310 */ 1311 soc15_doorbell_range_init(adev); 1312 1313 return 0; 1314 } 1315 1316 static int soc15_common_hw_fini(void *handle) 1317 { 1318 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1319 1320 /* disable the doorbell aperture */ 1321 soc15_enable_doorbell_aperture(adev, false); 1322 if (amdgpu_sriov_vf(adev)) 1323 xgpu_ai_mailbox_put_irq(adev); 1324 1325 if (adev->nbio.ras_if && 1326 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1327 if (adev->nbio.funcs->init_ras_controller_interrupt) 1328 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1329 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) 1330 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1331 } 1332 1333 return 0; 1334 } 1335 1336 static int soc15_common_suspend(void *handle) 1337 { 1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1339 1340 return soc15_common_hw_fini(adev); 1341 } 1342 1343 static int soc15_common_resume(void *handle) 1344 { 1345 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1346 1347 return soc15_common_hw_init(adev); 1348 } 1349 1350 static bool soc15_common_is_idle(void *handle) 1351 { 1352 return true; 1353 } 1354 1355 static int soc15_common_wait_for_idle(void *handle) 1356 { 1357 return 0; 1358 } 1359 1360 static int soc15_common_soft_reset(void *handle) 1361 { 1362 return 0; 1363 } 1364 1365 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable) 1366 { 1367 uint32_t def, data; 1368 1369 if (adev->asic_type == CHIP_VEGA20 || 1370 adev->asic_type == CHIP_ARCTURUS) { 1371 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); 1372 1373 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1374 data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1375 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1376 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1377 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK; 1378 else 1379 data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK | 1380 HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK | 1381 HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK | 1382 HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK); 1383 1384 if (def != data) 1385 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); 1386 } else { 1387 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1388 1389 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 1390 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1391 else 1392 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK; 1393 1394 if (def != data) 1395 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); 1396 } 1397 } 1398 1399 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1400 { 1401 uint32_t def, data; 1402 1403 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1404 1405 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1406 data &= ~(0x01000000 | 1407 0x02000000 | 1408 0x04000000 | 1409 0x08000000 | 1410 0x10000000 | 1411 0x20000000 | 1412 0x40000000 | 1413 0x80000000); 1414 else 1415 data |= (0x01000000 | 1416 0x02000000 | 1417 0x04000000 | 1418 0x08000000 | 1419 0x10000000 | 1420 0x20000000 | 1421 0x40000000 | 1422 0x80000000); 1423 1424 if (def != data) 1425 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1426 } 1427 1428 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1429 { 1430 uint32_t def, data; 1431 1432 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1433 1434 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1435 data |= 1; 1436 else 1437 data &= ~1; 1438 1439 if (def != data) 1440 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1441 } 1442 1443 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev, 1444 bool enable) 1445 { 1446 uint32_t def, data; 1447 1448 def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1449 1450 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG)) 1451 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1452 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK); 1453 else 1454 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK | 1455 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK; 1456 1457 if (def != data) 1458 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data); 1459 } 1460 1461 static int soc15_common_set_clockgating_state(void *handle, 1462 enum amd_clockgating_state state) 1463 { 1464 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1465 1466 if (amdgpu_sriov_vf(adev)) 1467 return 0; 1468 1469 switch (adev->asic_type) { 1470 case CHIP_VEGA10: 1471 case CHIP_VEGA12: 1472 case CHIP_VEGA20: 1473 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1474 state == AMD_CG_STATE_GATE); 1475 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1476 state == AMD_CG_STATE_GATE); 1477 soc15_update_hdp_light_sleep(adev, 1478 state == AMD_CG_STATE_GATE); 1479 soc15_update_drm_clock_gating(adev, 1480 state == AMD_CG_STATE_GATE); 1481 soc15_update_drm_light_sleep(adev, 1482 state == AMD_CG_STATE_GATE); 1483 soc15_update_rom_medium_grain_clock_gating(adev, 1484 state == AMD_CG_STATE_GATE); 1485 adev->df.funcs->update_medium_grain_clock_gating(adev, 1486 state == AMD_CG_STATE_GATE); 1487 break; 1488 case CHIP_RAVEN: 1489 case CHIP_RENOIR: 1490 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1491 state == AMD_CG_STATE_GATE); 1492 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1493 state == AMD_CG_STATE_GATE); 1494 soc15_update_hdp_light_sleep(adev, 1495 state == AMD_CG_STATE_GATE); 1496 soc15_update_drm_clock_gating(adev, 1497 state == AMD_CG_STATE_GATE); 1498 soc15_update_drm_light_sleep(adev, 1499 state == AMD_CG_STATE_GATE); 1500 soc15_update_rom_medium_grain_clock_gating(adev, 1501 state == AMD_CG_STATE_GATE); 1502 break; 1503 case CHIP_ARCTURUS: 1504 soc15_update_hdp_light_sleep(adev, 1505 state == AMD_CG_STATE_GATE); 1506 break; 1507 default: 1508 break; 1509 } 1510 return 0; 1511 } 1512 1513 static void soc15_common_get_clockgating_state(void *handle, u32 *flags) 1514 { 1515 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1516 int data; 1517 1518 if (amdgpu_sriov_vf(adev)) 1519 *flags = 0; 1520 1521 adev->nbio.funcs->get_clockgating_state(adev, flags); 1522 1523 /* AMD_CG_SUPPORT_HDP_LS */ 1524 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); 1525 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK) 1526 *flags |= AMD_CG_SUPPORT_HDP_LS; 1527 1528 /* AMD_CG_SUPPORT_DRM_MGCG */ 1529 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1530 if (!(data & 0x01000000)) 1531 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1532 1533 /* AMD_CG_SUPPORT_DRM_LS */ 1534 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1535 if (data & 0x1) 1536 *flags |= AMD_CG_SUPPORT_DRM_LS; 1537 1538 /* AMD_CG_SUPPORT_ROM_MGCG */ 1539 data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0)); 1540 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 1541 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 1542 1543 adev->df.funcs->get_clockgating_state(adev, flags); 1544 } 1545 1546 static int soc15_common_set_powergating_state(void *handle, 1547 enum amd_powergating_state state) 1548 { 1549 /* todo */ 1550 return 0; 1551 } 1552 1553 const struct amd_ip_funcs soc15_common_ip_funcs = { 1554 .name = "soc15_common", 1555 .early_init = soc15_common_early_init, 1556 .late_init = soc15_common_late_init, 1557 .sw_init = soc15_common_sw_init, 1558 .sw_fini = soc15_common_sw_fini, 1559 .hw_init = soc15_common_hw_init, 1560 .hw_fini = soc15_common_hw_fini, 1561 .suspend = soc15_common_suspend, 1562 .resume = soc15_common_resume, 1563 .is_idle = soc15_common_is_idle, 1564 .wait_for_idle = soc15_common_wait_for_idle, 1565 .soft_reset = soc15_common_soft_reset, 1566 .set_clockgating_state = soc15_common_set_clockgating_state, 1567 .set_powergating_state = soc15_common_set_powergating_state, 1568 .get_clockgating_state= soc15_common_get_clockgating_state, 1569 }; 1570