109aac699SHawking Zhang /*
209aac699SHawking Zhang * Copyright 2020 Advanced Micro Devices, Inc.
309aac699SHawking Zhang *
409aac699SHawking Zhang * Permission is hereby granted, free of charge, to any person obtaining a
509aac699SHawking Zhang * copy of this software and associated documentation files (the "Software"),
609aac699SHawking Zhang * to deal in the Software without restriction, including without limitation
709aac699SHawking Zhang * the rights to use, copy, modify, merge, publish, distribute, sublicense,
809aac699SHawking Zhang * and/or sell copies of the Software, and to permit persons to whom the
909aac699SHawking Zhang * Software is furnished to do so, subject to the following conditions:
1009aac699SHawking Zhang *
1109aac699SHawking Zhang * The above copyright notice and this permission notice shall be included in
1209aac699SHawking Zhang * all copies or substantial portions of the Software.
1309aac699SHawking Zhang *
1409aac699SHawking Zhang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1509aac699SHawking Zhang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1609aac699SHawking Zhang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1709aac699SHawking Zhang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1809aac699SHawking Zhang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1909aac699SHawking Zhang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2009aac699SHawking Zhang * OTHER DEALINGS IN THE SOFTWARE.
2109aac699SHawking Zhang *
2209aac699SHawking Zhang */
2309aac699SHawking Zhang #include "amdgpu.h"
2409aac699SHawking Zhang #include "smuio_v9_0.h"
2509aac699SHawking Zhang #include "smuio/smuio_9_0_offset.h"
2609aac699SHawking Zhang #include "smuio/smuio_9_0_sh_mask.h"
2709aac699SHawking Zhang
smuio_v9_0_get_rom_index_offset(struct amdgpu_device * adev)2809aac699SHawking Zhang static u32 smuio_v9_0_get_rom_index_offset(struct amdgpu_device *adev)
2909aac699SHawking Zhang {
3009aac699SHawking Zhang return SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
3109aac699SHawking Zhang }
3209aac699SHawking Zhang
smuio_v9_0_get_rom_data_offset(struct amdgpu_device * adev)3309aac699SHawking Zhang static u32 smuio_v9_0_get_rom_data_offset(struct amdgpu_device *adev)
3409aac699SHawking Zhang {
3509aac699SHawking Zhang return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
3609aac699SHawking Zhang }
3709aac699SHawking Zhang
smuio_v9_0_update_rom_clock_gating(struct amdgpu_device * adev,bool enable)381c990e78SHawking Zhang static void smuio_v9_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
3909aac699SHawking Zhang {
4009aac699SHawking Zhang u32 def, data;
4109aac699SHawking Zhang
4209aac699SHawking Zhang /* enable/disable ROM CG is not supported on APU */
4309aac699SHawking Zhang if (adev->flags & AMD_IS_APU)
4409aac699SHawking Zhang return;
4509aac699SHawking Zhang
4609aac699SHawking Zhang def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
4709aac699SHawking Zhang
4809aac699SHawking Zhang if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
4909aac699SHawking Zhang data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
5009aac699SHawking Zhang CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
5109aac699SHawking Zhang else
5209aac699SHawking Zhang data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
5309aac699SHawking Zhang CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
5409aac699SHawking Zhang
5509aac699SHawking Zhang if (def != data)
5609aac699SHawking Zhang WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data);
5709aac699SHawking Zhang }
5809aac699SHawking Zhang
smuio_v9_0_get_clock_gating_state(struct amdgpu_device * adev,u64 * flags)59*25faeddcSEvan Quan static void smuio_v9_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)
6009aac699SHawking Zhang {
6109aac699SHawking Zhang u32 data;
6209aac699SHawking Zhang
6309aac699SHawking Zhang /* CGTT_ROM_CLK_CTRL0 is not availabe for APUs */
6409aac699SHawking Zhang if (adev->flags & AMD_IS_APU)
6509aac699SHawking Zhang return;
6609aac699SHawking Zhang
6709aac699SHawking Zhang data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
6809aac699SHawking Zhang if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
6909aac699SHawking Zhang *flags |= AMD_CG_SUPPORT_ROM_MGCG;
7009aac699SHawking Zhang }
7109aac699SHawking Zhang
7209aac699SHawking Zhang const struct amdgpu_smuio_funcs smuio_v9_0_funcs = {
7309aac699SHawking Zhang .get_rom_index_offset = smuio_v9_0_get_rom_index_offset,
7409aac699SHawking Zhang .get_rom_data_offset = smuio_v9_0_get_rom_data_offset,
7509aac699SHawking Zhang .update_rom_clock_gating = smuio_v9_0_update_rom_clock_gating,
7609aac699SHawking Zhang .get_clock_gating_state = smuio_v9_0_get_clock_gating_state,
7709aac699SHawking Zhang };
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