11deb9853SLikun Gao /*
21deb9853SLikun Gao * Copyright 2021 Advanced Micro Devices, Inc.
31deb9853SLikun Gao *
41deb9853SLikun Gao * Permission is hereby granted, free of charge, to any person obtaining a
51deb9853SLikun Gao * copy of this software and associated documentation files (the "Software"),
61deb9853SLikun Gao * to deal in the Software without restriction, including without limitation
71deb9853SLikun Gao * the rights to use, copy, modify, merge, publish, distribute, sublicense,
81deb9853SLikun Gao * and/or sell copies of the Software, and to permit persons to whom the
91deb9853SLikun Gao * Software is furnished to do so, subject to the following conditions:
101deb9853SLikun Gao *
111deb9853SLikun Gao * The above copyright notice and this permission notice shall be included in
121deb9853SLikun Gao * all copies or substantial portions of the Software.
131deb9853SLikun Gao *
141deb9853SLikun Gao * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
151deb9853SLikun Gao * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
161deb9853SLikun Gao * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
171deb9853SLikun Gao * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
181deb9853SLikun Gao * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
191deb9853SLikun Gao * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
201deb9853SLikun Gao * OTHER DEALINGS IN THE SOFTWARE.
211deb9853SLikun Gao *
221deb9853SLikun Gao */
231deb9853SLikun Gao #include "amdgpu.h"
241deb9853SLikun Gao #include "smuio_v11_0_6.h"
251deb9853SLikun Gao #include "smuio/smuio_11_0_6_offset.h"
261deb9853SLikun Gao #include "smuio/smuio_11_0_6_sh_mask.h"
271deb9853SLikun Gao
smuio_v11_0_6_get_rom_index_offset(struct amdgpu_device * adev)281deb9853SLikun Gao static u32 smuio_v11_0_6_get_rom_index_offset(struct amdgpu_device *adev)
291deb9853SLikun Gao {
301deb9853SLikun Gao return SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
311deb9853SLikun Gao }
321deb9853SLikun Gao
smuio_v11_0_6_get_rom_data_offset(struct amdgpu_device * adev)331deb9853SLikun Gao static u32 smuio_v11_0_6_get_rom_data_offset(struct amdgpu_device *adev)
341deb9853SLikun Gao {
351deb9853SLikun Gao return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
361deb9853SLikun Gao }
371deb9853SLikun Gao
smuio_v11_0_6_update_rom_clock_gating(struct amdgpu_device * adev,bool enable)381001f2a1SLikun Gao static void smuio_v11_0_6_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
391001f2a1SLikun Gao {
401001f2a1SLikun Gao u32 def, data;
411001f2a1SLikun Gao
421001f2a1SLikun Gao /* enable/disable ROM CG is not supported on APU */
431001f2a1SLikun Gao if (adev->flags & AMD_IS_APU)
441001f2a1SLikun Gao return;
451001f2a1SLikun Gao
461001f2a1SLikun Gao def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
471001f2a1SLikun Gao
481001f2a1SLikun Gao if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
491001f2a1SLikun Gao data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
501001f2a1SLikun Gao CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
511001f2a1SLikun Gao else
521001f2a1SLikun Gao data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
531001f2a1SLikun Gao CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
541001f2a1SLikun Gao
551001f2a1SLikun Gao if (def != data)
561001f2a1SLikun Gao WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data);
571001f2a1SLikun Gao }
581001f2a1SLikun Gao
smuio_v11_0_6_get_clock_gating_state(struct amdgpu_device * adev,u64 * flags)59*25faeddcSEvan Quan static void smuio_v11_0_6_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)
601001f2a1SLikun Gao {
611001f2a1SLikun Gao u32 data;
621001f2a1SLikun Gao
631001f2a1SLikun Gao /* CGTT_ROM_CLK_CTRL0 is not available for APU */
641001f2a1SLikun Gao if (adev->flags & AMD_IS_APU)
651001f2a1SLikun Gao return;
661001f2a1SLikun Gao
671001f2a1SLikun Gao data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
681001f2a1SLikun Gao if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
691001f2a1SLikun Gao *flags |= AMD_CG_SUPPORT_ROM_MGCG;
701001f2a1SLikun Gao }
711001f2a1SLikun Gao
721deb9853SLikun Gao const struct amdgpu_smuio_funcs smuio_v11_0_6_funcs = {
731deb9853SLikun Gao .get_rom_index_offset = smuio_v11_0_6_get_rom_index_offset,
741deb9853SLikun Gao .get_rom_data_offset = smuio_v11_0_6_get_rom_data_offset,
751001f2a1SLikun Gao .update_rom_clock_gating = smuio_v11_0_6_update_rom_clock_gating,
761001f2a1SLikun Gao .get_clock_gating_state = smuio_v11_0_6_get_clock_gating_state,
771deb9853SLikun Gao };
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