1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drmP.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "sid.h" 27 #include "si_ih.h" 28 29 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev); 30 31 static void si_ih_enable_interrupts(struct amdgpu_device *adev) 32 { 33 u32 ih_cntl = RREG32(IH_CNTL); 34 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 35 36 ih_cntl |= ENABLE_INTR; 37 ih_rb_cntl |= IH_RB_ENABLE; 38 WREG32(IH_CNTL, ih_cntl); 39 WREG32(IH_RB_CNTL, ih_rb_cntl); 40 adev->irq.ih.enabled = true; 41 } 42 43 static void si_ih_disable_interrupts(struct amdgpu_device *adev) 44 { 45 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 46 u32 ih_cntl = RREG32(IH_CNTL); 47 48 ih_rb_cntl &= ~IH_RB_ENABLE; 49 ih_cntl &= ~ENABLE_INTR; 50 WREG32(IH_RB_CNTL, ih_rb_cntl); 51 WREG32(IH_CNTL, ih_cntl); 52 WREG32(IH_RB_RPTR, 0); 53 WREG32(IH_RB_WPTR, 0); 54 adev->irq.ih.enabled = false; 55 adev->irq.ih.rptr = 0; 56 } 57 58 static int si_ih_irq_init(struct amdgpu_device *adev) 59 { 60 struct amdgpu_ih_ring *ih = &adev->irq.ih; 61 int rb_bufsz; 62 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 63 64 si_ih_disable_interrupts(adev); 65 WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8); 66 interrupt_cntl = RREG32(INTERRUPT_CNTL); 67 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 68 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 69 WREG32(INTERRUPT_CNTL, interrupt_cntl); 70 71 WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 72 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 73 74 ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE | 75 IH_WPTR_OVERFLOW_CLEAR | 76 (rb_bufsz << 1) | 77 IH_WPTR_WRITEBACK_ENABLE; 78 79 WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); 80 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); 81 WREG32(IH_RB_CNTL, ih_rb_cntl); 82 WREG32(IH_RB_RPTR, 0); 83 WREG32(IH_RB_WPTR, 0); 84 85 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); 86 if (adev->irq.msi_enabled) 87 ih_cntl |= RPTR_REARM; 88 WREG32(IH_CNTL, ih_cntl); 89 90 pci_set_master(adev->pdev); 91 si_ih_enable_interrupts(adev); 92 93 return 0; 94 } 95 96 static void si_ih_irq_disable(struct amdgpu_device *adev) 97 { 98 si_ih_disable_interrupts(adev); 99 mdelay(1); 100 } 101 102 static u32 si_ih_get_wptr(struct amdgpu_device *adev, 103 struct amdgpu_ih_ring *ih) 104 { 105 u32 wptr, tmp; 106 107 wptr = le32_to_cpu(*ih->wptr_cpu); 108 109 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { 110 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; 111 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 112 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); 113 ih->rptr = (wptr + 16) & ih->ptr_mask; 114 tmp = RREG32(IH_RB_CNTL); 115 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; 116 WREG32(IH_RB_CNTL, tmp); 117 } 118 return (wptr & ih->ptr_mask); 119 } 120 121 static void si_ih_decode_iv(struct amdgpu_device *adev, 122 struct amdgpu_ih_ring *ih, 123 struct amdgpu_iv_entry *entry) 124 { 125 u32 ring_index = ih->rptr >> 2; 126 uint32_t dw[4]; 127 128 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 129 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 130 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 131 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 132 133 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 134 entry->src_id = dw[0] & 0xff; 135 entry->src_data[0] = dw[1] & 0xfffffff; 136 entry->ring_id = dw[2] & 0xff; 137 entry->vmid = (dw[2] >> 8) & 0xff; 138 139 ih->rptr += 16; 140 } 141 142 static void si_ih_set_rptr(struct amdgpu_device *adev, 143 struct amdgpu_ih_ring *ih) 144 { 145 WREG32(IH_RB_RPTR, ih->rptr); 146 } 147 148 static int si_ih_early_init(void *handle) 149 { 150 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 151 152 si_ih_set_interrupt_funcs(adev); 153 154 return 0; 155 } 156 157 static int si_ih_sw_init(void *handle) 158 { 159 int r; 160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 161 162 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); 163 if (r) 164 return r; 165 166 return amdgpu_irq_init(adev); 167 } 168 169 static int si_ih_sw_fini(void *handle) 170 { 171 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 172 173 amdgpu_irq_fini(adev); 174 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 175 176 return 0; 177 } 178 179 static int si_ih_hw_init(void *handle) 180 { 181 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 182 183 return si_ih_irq_init(adev); 184 } 185 186 static int si_ih_hw_fini(void *handle) 187 { 188 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 189 190 si_ih_irq_disable(adev); 191 192 return 0; 193 } 194 195 static int si_ih_suspend(void *handle) 196 { 197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 198 199 return si_ih_hw_fini(adev); 200 } 201 202 static int si_ih_resume(void *handle) 203 { 204 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 205 206 return si_ih_hw_init(adev); 207 } 208 209 static bool si_ih_is_idle(void *handle) 210 { 211 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 212 u32 tmp = RREG32(SRBM_STATUS); 213 214 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 215 return false; 216 217 return true; 218 } 219 220 static int si_ih_wait_for_idle(void *handle) 221 { 222 unsigned i; 223 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 224 225 for (i = 0; i < adev->usec_timeout; i++) { 226 if (si_ih_is_idle(handle)) 227 return 0; 228 udelay(1); 229 } 230 return -ETIMEDOUT; 231 } 232 233 static int si_ih_soft_reset(void *handle) 234 { 235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 236 237 u32 srbm_soft_reset = 0; 238 u32 tmp = RREG32(SRBM_STATUS); 239 240 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 241 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; 242 243 if (srbm_soft_reset) { 244 tmp = RREG32(SRBM_SOFT_RESET); 245 tmp |= srbm_soft_reset; 246 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 247 WREG32(SRBM_SOFT_RESET, tmp); 248 tmp = RREG32(SRBM_SOFT_RESET); 249 250 udelay(50); 251 252 tmp &= ~srbm_soft_reset; 253 WREG32(SRBM_SOFT_RESET, tmp); 254 tmp = RREG32(SRBM_SOFT_RESET); 255 256 udelay(50); 257 } 258 259 return 0; 260 } 261 262 static int si_ih_set_clockgating_state(void *handle, 263 enum amd_clockgating_state state) 264 { 265 return 0; 266 } 267 268 static int si_ih_set_powergating_state(void *handle, 269 enum amd_powergating_state state) 270 { 271 return 0; 272 } 273 274 static const struct amd_ip_funcs si_ih_ip_funcs = { 275 .name = "si_ih", 276 .early_init = si_ih_early_init, 277 .late_init = NULL, 278 .sw_init = si_ih_sw_init, 279 .sw_fini = si_ih_sw_fini, 280 .hw_init = si_ih_hw_init, 281 .hw_fini = si_ih_hw_fini, 282 .suspend = si_ih_suspend, 283 .resume = si_ih_resume, 284 .is_idle = si_ih_is_idle, 285 .wait_for_idle = si_ih_wait_for_idle, 286 .soft_reset = si_ih_soft_reset, 287 .set_clockgating_state = si_ih_set_clockgating_state, 288 .set_powergating_state = si_ih_set_powergating_state, 289 }; 290 291 static const struct amdgpu_ih_funcs si_ih_funcs = { 292 .get_wptr = si_ih_get_wptr, 293 .decode_iv = si_ih_decode_iv, 294 .set_rptr = si_ih_set_rptr 295 }; 296 297 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev) 298 { 299 adev->irq.ih_funcs = &si_ih_funcs; 300 } 301 302 const struct amdgpu_ip_block_version si_ih_ip_block = 303 { 304 .type = AMD_IP_BLOCK_TYPE_IH, 305 .major = 1, 306 .minor = 0, 307 .rev = 0, 308 .funcs = &si_ih_ip_funcs, 309 }; 310