1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "sid.h" 29 #include "si_ih.h" 30 31 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev); 32 33 static void si_ih_enable_interrupts(struct amdgpu_device *adev) 34 { 35 u32 ih_cntl = RREG32(IH_CNTL); 36 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 37 38 ih_cntl |= ENABLE_INTR; 39 ih_rb_cntl |= IH_RB_ENABLE; 40 WREG32(IH_CNTL, ih_cntl); 41 WREG32(IH_RB_CNTL, ih_rb_cntl); 42 adev->irq.ih.enabled = true; 43 } 44 45 static void si_ih_disable_interrupts(struct amdgpu_device *adev) 46 { 47 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 48 u32 ih_cntl = RREG32(IH_CNTL); 49 50 ih_rb_cntl &= ~IH_RB_ENABLE; 51 ih_cntl &= ~ENABLE_INTR; 52 WREG32(IH_RB_CNTL, ih_rb_cntl); 53 WREG32(IH_CNTL, ih_cntl); 54 WREG32(IH_RB_RPTR, 0); 55 WREG32(IH_RB_WPTR, 0); 56 adev->irq.ih.enabled = false; 57 adev->irq.ih.rptr = 0; 58 } 59 60 static int si_ih_irq_init(struct amdgpu_device *adev) 61 { 62 struct amdgpu_ih_ring *ih = &adev->irq.ih; 63 int rb_bufsz; 64 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 65 66 si_ih_disable_interrupts(adev); 67 WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8); 68 interrupt_cntl = RREG32(INTERRUPT_CNTL); 69 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 70 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 71 WREG32(INTERRUPT_CNTL, interrupt_cntl); 72 73 WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 74 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 75 76 ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE | 77 IH_WPTR_OVERFLOW_CLEAR | 78 (rb_bufsz << 1) | 79 IH_WPTR_WRITEBACK_ENABLE; 80 81 WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); 82 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); 83 WREG32(IH_RB_CNTL, ih_rb_cntl); 84 WREG32(IH_RB_RPTR, 0); 85 WREG32(IH_RB_WPTR, 0); 86 87 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); 88 if (adev->irq.msi_enabled) 89 ih_cntl |= RPTR_REARM; 90 WREG32(IH_CNTL, ih_cntl); 91 92 pci_set_master(adev->pdev); 93 si_ih_enable_interrupts(adev); 94 95 return 0; 96 } 97 98 static void si_ih_irq_disable(struct amdgpu_device *adev) 99 { 100 si_ih_disable_interrupts(adev); 101 mdelay(1); 102 } 103 104 static u32 si_ih_get_wptr(struct amdgpu_device *adev, 105 struct amdgpu_ih_ring *ih) 106 { 107 u32 wptr, tmp; 108 109 wptr = le32_to_cpu(*ih->wptr_cpu); 110 111 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { 112 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; 113 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 114 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); 115 ih->rptr = (wptr + 16) & ih->ptr_mask; 116 tmp = RREG32(IH_RB_CNTL); 117 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; 118 WREG32(IH_RB_CNTL, tmp); 119 } 120 return (wptr & ih->ptr_mask); 121 } 122 123 static void si_ih_decode_iv(struct amdgpu_device *adev, 124 struct amdgpu_ih_ring *ih, 125 struct amdgpu_iv_entry *entry) 126 { 127 u32 ring_index = ih->rptr >> 2; 128 uint32_t dw[4]; 129 130 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 131 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 132 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 133 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 134 135 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 136 entry->src_id = dw[0] & 0xff; 137 entry->src_data[0] = dw[1] & 0xfffffff; 138 entry->ring_id = dw[2] & 0xff; 139 entry->vmid = (dw[2] >> 8) & 0xff; 140 141 ih->rptr += 16; 142 } 143 144 static void si_ih_set_rptr(struct amdgpu_device *adev, 145 struct amdgpu_ih_ring *ih) 146 { 147 WREG32(IH_RB_RPTR, ih->rptr); 148 } 149 150 static int si_ih_early_init(void *handle) 151 { 152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 153 154 si_ih_set_interrupt_funcs(adev); 155 156 return 0; 157 } 158 159 static int si_ih_sw_init(void *handle) 160 { 161 int r; 162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 163 164 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); 165 if (r) 166 return r; 167 168 return amdgpu_irq_init(adev); 169 } 170 171 static int si_ih_sw_fini(void *handle) 172 { 173 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 174 175 amdgpu_irq_fini(adev); 176 amdgpu_ih_ring_fini(adev, &adev->irq.ih); 177 178 return 0; 179 } 180 181 static int si_ih_hw_init(void *handle) 182 { 183 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 184 185 return si_ih_irq_init(adev); 186 } 187 188 static int si_ih_hw_fini(void *handle) 189 { 190 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 191 192 si_ih_irq_disable(adev); 193 194 return 0; 195 } 196 197 static int si_ih_suspend(void *handle) 198 { 199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 200 201 return si_ih_hw_fini(adev); 202 } 203 204 static int si_ih_resume(void *handle) 205 { 206 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 207 208 return si_ih_hw_init(adev); 209 } 210 211 static bool si_ih_is_idle(void *handle) 212 { 213 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 214 u32 tmp = RREG32(SRBM_STATUS); 215 216 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 217 return false; 218 219 return true; 220 } 221 222 static int si_ih_wait_for_idle(void *handle) 223 { 224 unsigned i; 225 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 226 227 for (i = 0; i < adev->usec_timeout; i++) { 228 if (si_ih_is_idle(handle)) 229 return 0; 230 udelay(1); 231 } 232 return -ETIMEDOUT; 233 } 234 235 static int si_ih_soft_reset(void *handle) 236 { 237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 238 239 u32 srbm_soft_reset = 0; 240 u32 tmp = RREG32(SRBM_STATUS); 241 242 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 243 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; 244 245 if (srbm_soft_reset) { 246 tmp = RREG32(SRBM_SOFT_RESET); 247 tmp |= srbm_soft_reset; 248 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 249 WREG32(SRBM_SOFT_RESET, tmp); 250 tmp = RREG32(SRBM_SOFT_RESET); 251 252 udelay(50); 253 254 tmp &= ~srbm_soft_reset; 255 WREG32(SRBM_SOFT_RESET, tmp); 256 tmp = RREG32(SRBM_SOFT_RESET); 257 258 udelay(50); 259 } 260 261 return 0; 262 } 263 264 static int si_ih_set_clockgating_state(void *handle, 265 enum amd_clockgating_state state) 266 { 267 return 0; 268 } 269 270 static int si_ih_set_powergating_state(void *handle, 271 enum amd_powergating_state state) 272 { 273 return 0; 274 } 275 276 static const struct amd_ip_funcs si_ih_ip_funcs = { 277 .name = "si_ih", 278 .early_init = si_ih_early_init, 279 .late_init = NULL, 280 .sw_init = si_ih_sw_init, 281 .sw_fini = si_ih_sw_fini, 282 .hw_init = si_ih_hw_init, 283 .hw_fini = si_ih_hw_fini, 284 .suspend = si_ih_suspend, 285 .resume = si_ih_resume, 286 .is_idle = si_ih_is_idle, 287 .wait_for_idle = si_ih_wait_for_idle, 288 .soft_reset = si_ih_soft_reset, 289 .set_clockgating_state = si_ih_set_clockgating_state, 290 .set_powergating_state = si_ih_set_powergating_state, 291 }; 292 293 static const struct amdgpu_ih_funcs si_ih_funcs = { 294 .get_wptr = si_ih_get_wptr, 295 .decode_iv = si_ih_decode_iv, 296 .set_rptr = si_ih_set_rptr 297 }; 298 299 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev) 300 { 301 adev->irq.ih_funcs = &si_ih_funcs; 302 } 303 304 const struct amdgpu_ip_block_version si_ih_ip_block = 305 { 306 .type = AMD_IP_BLOCK_TYPE_IH, 307 .major = 1, 308 .minor = 0, 309 .rev = 0, 310 .funcs = &si_ih_ip_funcs, 311 }; 312