1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef SI_ENUMS_H 24 #define SI_ENUMS_H 25 26 #define VBLANK_INT_MASK (1 << 0) 27 #define DC_HPDx_INT_EN (1 << 16) 28 #define VBLANK_ACK (1 << 4) 29 #define VLINE_ACK (1 << 4) 30 31 #define CURSOR_WIDTH 64 32 #define CURSOR_HEIGHT 64 33 34 #define VGA_VSTATUS_CNTL 0xFFFCFFFF 35 #define PRIORITY_MARK_MASK 0x7fff 36 #define PRIORITY_OFF (1 << 16) 37 #define PRIORITY_ALWAYS_ON (1 << 20) 38 #define INTERLEAVE_EN (1 << 0) 39 40 #define LATENCY_WATERMARK_MASK(x) ((x) << 16) 41 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 42 #define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8) 43 44 #define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) 45 #define GRPH_ENDIAN_NONE 0 46 #define GRPH_ENDIAN_8IN16 1 47 #define GRPH_ENDIAN_8IN32 2 48 #define GRPH_ENDIAN_8IN64 3 49 #define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) 50 #define GRPH_RED_SEL_R 0 51 #define GRPH_RED_SEL_G 1 52 #define GRPH_RED_SEL_B 2 53 #define GRPH_RED_SEL_A 3 54 #define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) 55 #define GRPH_GREEN_SEL_G 0 56 #define GRPH_GREEN_SEL_B 1 57 #define GRPH_GREEN_SEL_A 2 58 #define GRPH_GREEN_SEL_R 3 59 #define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) 60 #define GRPH_BLUE_SEL_B 0 61 #define GRPH_BLUE_SEL_A 1 62 #define GRPH_BLUE_SEL_R 2 63 #define GRPH_BLUE_SEL_G 3 64 #define GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) 65 #define GRPH_ALPHA_SEL_A 0 66 #define GRPH_ALPHA_SEL_R 1 67 #define GRPH_ALPHA_SEL_G 2 68 #define GRPH_ALPHA_SEL_B 3 69 70 #define GRPH_DEPTH(x) (((x) & 0x3) << 0) 71 #define GRPH_DEPTH_8BPP 0 72 #define GRPH_DEPTH_16BPP 1 73 #define GRPH_DEPTH_32BPP 2 74 75 #define GRPH_FORMAT(x) (((x) & 0x7) << 8) 76 #define GRPH_FORMAT_INDEXED 0 77 #define GRPH_FORMAT_ARGB1555 0 78 #define GRPH_FORMAT_ARGB565 1 79 #define GRPH_FORMAT_ARGB4444 2 80 #define GRPH_FORMAT_AI88 3 81 #define GRPH_FORMAT_MONO16 4 82 #define GRPH_FORMAT_BGRA5551 5 83 #define GRPH_FORMAT_ARGB8888 0 84 #define GRPH_FORMAT_ARGB2101010 1 85 #define GRPH_FORMAT_32BPP_DIG 2 86 #define GRPH_FORMAT_8B_ARGB2101010 3 87 #define GRPH_FORMAT_BGRA1010102 4 88 #define GRPH_FORMAT_8B_BGRA1010102 5 89 #define GRPH_FORMAT_RGB111110 6 90 #define GRPH_FORMAT_BGR101111 7 91 92 #define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2) 93 #define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 94 #define GRPH_ARRAY_LINEAR_GENERAL 0 95 #define GRPH_ARRAY_LINEAR_ALIGNED 1 96 #define GRPH_ARRAY_1D_TILED_THIN1 2 97 #define GRPH_ARRAY_2D_TILED_THIN1 4 98 #define GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13) 99 #define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6) 100 #define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11) 101 #define GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18) 102 #define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20) 103 #define GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24) 104 105 #define CURSOR_EN (1 << 0) 106 #define CURSOR_MODE(x) (((x) & 0x3) << 8) 107 #define CURSOR_MONO 0 108 #define CURSOR_24_1 1 109 #define CURSOR_24_8_PRE_MULT 2 110 #define CURSOR_24_8_UNPRE_MULT 3 111 #define CURSOR_2X_MAGNIFY (1 << 16) 112 #define CURSOR_FORCE_MC_ON (1 << 20) 113 #define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) 114 #define CURSOR_URGENT_ALWAYS 0 115 #define CURSOR_URGENT_1_8 1 116 #define CURSOR_URGENT_1_4 2 117 #define CURSOR_URGENT_3_8 3 118 #define CURSOR_URGENT_1_2 4 119 #define CURSOR_UPDATE_PENDING (1 << 0) 120 #define CURSOR_UPDATE_TAKEN (1 << 1) 121 #define CURSOR_UPDATE_LOCK (1 << 16) 122 #define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) 123 124 #define AMDGPU_NUM_OF_VMIDS 8 125 #define SI_CRTC0_REGISTER_OFFSET 0 126 #define SI_CRTC1_REGISTER_OFFSET 0x300 127 #define SI_CRTC2_REGISTER_OFFSET 0x2600 128 #define SI_CRTC3_REGISTER_OFFSET 0x2900 129 #define SI_CRTC4_REGISTER_OFFSET 0x2c00 130 #define SI_CRTC5_REGISTER_OFFSET 0x2f00 131 132 #define DMA0_REGISTER_OFFSET 0x000 133 #define DMA1_REGISTER_OFFSET 0x200 134 #define ES_AND_GS_AUTO 3 135 #define RADEON_PACKET_TYPE3 3 136 #define CE_PARTITION_BASE 3 137 #define BUF_SWAP_32BIT (2 << 16) 138 139 #define GFX_POWER_STATUS (1 << 1) 140 #define GFX_CLOCK_STATUS (1 << 2) 141 #define GFX_LS_STATUS (1 << 3) 142 #define RLC_BUSY_STATUS (1 << 0) 143 144 #define RLC_PUD(x) ((x) << 0) 145 #define RLC_PUD_MASK (0xff << 0) 146 #define RLC_PDD(x) ((x) << 8) 147 #define RLC_PDD_MASK (0xff << 8) 148 #define RLC_TTPD(x) ((x) << 16) 149 #define RLC_TTPD_MASK (0xff << 16) 150 #define RLC_MSD(x) ((x) << 24) 151 #define RLC_MSD_MASK (0xff << 24) 152 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 153 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 154 #define EVENT_TYPE(x) ((x) << 0) 155 #define EVENT_INDEX(x) ((x) << 8) 156 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 157 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 158 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 159 160 #define GFX6_NUM_GFX_RINGS 1 161 #define GFX6_NUM_COMPUTE_RINGS 2 162 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 163 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D 164 165 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 166 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x02010002 167 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 168 169 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 170 (((op) & 0xFF) << 8) | \ 171 ((n) & 0x3FFF) << 16) 172 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 173 #define PACKET3_NOP 0x10 174 #define PACKET3_SET_BASE 0x11 175 #define PACKET3_BASE_INDEX(x) ((x) << 0) 176 #define PACKET3_CLEAR_STATE 0x12 177 #define PACKET3_INDEX_BUFFER_SIZE 0x13 178 #define PACKET3_DISPATCH_DIRECT 0x15 179 #define PACKET3_DISPATCH_INDIRECT 0x16 180 #define PACKET3_ALLOC_GDS 0x1B 181 #define PACKET3_WRITE_GDS_RAM 0x1C 182 #define PACKET3_ATOMIC_GDS 0x1D 183 #define PACKET3_ATOMIC 0x1E 184 #define PACKET3_OCCLUSION_QUERY 0x1F 185 #define PACKET3_SET_PREDICATION 0x20 186 #define PACKET3_REG_RMW 0x21 187 #define PACKET3_COND_EXEC 0x22 188 #define PACKET3_PRED_EXEC 0x23 189 #define PACKET3_DRAW_INDIRECT 0x24 190 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 191 #define PACKET3_INDEX_BASE 0x26 192 #define PACKET3_DRAW_INDEX_2 0x27 193 #define PACKET3_CONTEXT_CONTROL 0x28 194 #define PACKET3_INDEX_TYPE 0x2A 195 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 196 #define PACKET3_DRAW_INDEX_AUTO 0x2D 197 #define PACKET3_DRAW_INDEX_IMMD 0x2E 198 #define PACKET3_NUM_INSTANCES 0x2F 199 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 200 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 201 #define PACKET3_INDIRECT_BUFFER 0x3F 202 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 203 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 204 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 205 #define PACKET3_WRITE_DATA 0x37 206 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 207 #define PACKET3_MEM_SEMAPHORE 0x39 208 #define PACKET3_MPEG_INDEX 0x3A 209 #define PACKET3_COPY_DW 0x3B 210 #define PACKET3_WAIT_REG_MEM 0x3C 211 #define PACKET3_MEM_WRITE 0x3D 212 #define PACKET3_COPY_DATA 0x40 213 #define PACKET3_CP_DMA 0x41 214 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 215 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 216 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 217 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 218 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 219 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 220 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 221 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 222 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 223 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 224 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 225 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 226 #define PACKET3_PFP_SYNC_ME 0x42 227 #define PACKET3_SURFACE_SYNC 0x43 228 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 229 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 230 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 231 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 232 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 233 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 234 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 235 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 236 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 237 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 238 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 239 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 240 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 241 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 242 # define PACKET3_TC_ACTION_ENA (1 << 23) 243 # define PACKET3_CB_ACTION_ENA (1 << 25) 244 # define PACKET3_DB_ACTION_ENA (1 << 26) 245 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 246 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 247 #define PACKET3_ME_INITIALIZE 0x44 248 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 249 #define PACKET3_COND_WRITE 0x45 250 #define PACKET3_EVENT_WRITE 0x46 251 #define PACKET3_EVENT_WRITE_EOP 0x47 252 #define PACKET3_EVENT_WRITE_EOS 0x48 253 #define PACKET3_PREAMBLE_CNTL 0x4A 254 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 255 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 256 #define PACKET3_ONE_REG_WRITE 0x57 257 #define PACKET3_LOAD_CONFIG_REG 0x5F 258 #define PACKET3_LOAD_CONTEXT_REG 0x60 259 #define PACKET3_LOAD_SH_REG 0x61 260 #define PACKET3_SET_CONFIG_REG 0x68 261 #define PACKET3_SET_CONFIG_REG_START 0x00002000 262 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 263 #define PACKET3_SET_CONTEXT_REG 0x69 264 #define PACKET3_SET_CONTEXT_REG_START 0x000a000 265 #define PACKET3_SET_CONTEXT_REG_END 0x000a400 266 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 267 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 268 #define PACKET3_SET_SH_REG 0x76 269 #define PACKET3_SET_SH_REG_START 0x00002c00 270 #define PACKET3_SET_SH_REG_END 0x00003000 271 #define PACKET3_SET_SH_REG_OFFSET 0x77 272 #define PACKET3_ME_WRITE 0x7A 273 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 274 #define PACKET3_SCRATCH_RAM_READ 0x7E 275 #define PACKET3_CE_WRITE 0x7F 276 #define PACKET3_LOAD_CONST_RAM 0x80 277 #define PACKET3_WRITE_CONST_RAM 0x81 278 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 279 #define PACKET3_DUMP_CONST_RAM 0x83 280 #define PACKET3_INCREMENT_CE_COUNTER 0x84 281 #define PACKET3_INCREMENT_DE_COUNTER 0x85 282 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 283 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 284 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 285 #define PACKET3_SET_CE_DE_COUNTERS 0x89 286 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 287 #define PACKET3_SWITCH_BUFFER 0x8B 288 #define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 289 #define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 290 #define PACKET3_SEM_SEL_WAIT (0x7 << 29) 291 292 #endif 293