1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <drm/drmP.h> 25 #include "amdgpu.h" 26 #include "amdgpu_trace.h" 27 #include "si.h" 28 #include "sid.h" 29 30 const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 31 { 32 DMA0_REGISTER_OFFSET, 33 DMA1_REGISTER_OFFSET 34 }; 35 36 static void si_dma_set_ring_funcs(struct amdgpu_device *adev); 37 static void si_dma_set_buffer_funcs(struct amdgpu_device *adev); 38 static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev); 39 static void si_dma_set_irq_funcs(struct amdgpu_device *adev); 40 41 static uint64_t si_dma_ring_get_rptr(struct amdgpu_ring *ring) 42 { 43 return ring->adev->wb.wb[ring->rptr_offs>>2]; 44 } 45 46 static uint64_t si_dma_ring_get_wptr(struct amdgpu_ring *ring) 47 { 48 struct amdgpu_device *adev = ring->adev; 49 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 50 51 return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; 52 } 53 54 static void si_dma_ring_set_wptr(struct amdgpu_ring *ring) 55 { 56 struct amdgpu_device *adev = ring->adev; 57 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 58 59 WREG32(DMA_RB_WPTR + sdma_offsets[me], 60 (lower_32_bits(ring->wptr) << 2) & 0x3fffc); 61 } 62 63 static void si_dma_ring_emit_ib(struct amdgpu_ring *ring, 64 struct amdgpu_ib *ib, 65 unsigned vmid, bool ctx_switch) 66 { 67 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. 68 * Pad as necessary with NOPs. 69 */ 70 while ((lower_32_bits(ring->wptr) & 7) != 5) 71 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 72 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0)); 73 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 74 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 75 76 } 77 78 static void si_dma_ring_emit_hdp_flush(struct amdgpu_ring *ring) 79 { 80 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 81 amdgpu_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL)); 82 amdgpu_ring_write(ring, 1); 83 } 84 85 static void si_dma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 86 { 87 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 88 amdgpu_ring_write(ring, (0xf << 16) | (HDP_DEBUG0)); 89 amdgpu_ring_write(ring, 1); 90 } 91 92 /** 93 * si_dma_ring_emit_fence - emit a fence on the DMA ring 94 * 95 * @ring: amdgpu ring pointer 96 * @fence: amdgpu fence object 97 * 98 * Add a DMA fence packet to the ring to write 99 * the fence seq number and DMA trap packet to generate 100 * an interrupt if needed (VI). 101 */ 102 static void si_dma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 103 unsigned flags) 104 { 105 106 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 107 /* write the fence */ 108 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); 109 amdgpu_ring_write(ring, addr & 0xfffffffc); 110 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); 111 amdgpu_ring_write(ring, seq); 112 /* optionally write high bits as well */ 113 if (write64bit) { 114 addr += 4; 115 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0)); 116 amdgpu_ring_write(ring, addr & 0xfffffffc); 117 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); 118 amdgpu_ring_write(ring, upper_32_bits(seq)); 119 } 120 /* generate an interrupt */ 121 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0, 0)); 122 } 123 124 static void si_dma_stop(struct amdgpu_device *adev) 125 { 126 struct amdgpu_ring *ring; 127 u32 rb_cntl; 128 unsigned i; 129 130 for (i = 0; i < adev->sdma.num_instances; i++) { 131 ring = &adev->sdma.instance[i].ring; 132 /* dma0 */ 133 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); 134 rb_cntl &= ~DMA_RB_ENABLE; 135 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); 136 137 if (adev->mman.buffer_funcs_ring == ring) 138 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size); 139 ring->ready = false; 140 } 141 } 142 143 static int si_dma_start(struct amdgpu_device *adev) 144 { 145 struct amdgpu_ring *ring; 146 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; 147 int i, r; 148 uint64_t rptr_addr; 149 150 for (i = 0; i < adev->sdma.num_instances; i++) { 151 ring = &adev->sdma.instance[i].ring; 152 153 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); 154 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 155 156 /* Set ring buffer size in dwords */ 157 rb_bufsz = order_base_2(ring->ring_size / 4); 158 rb_cntl = rb_bufsz << 1; 159 #ifdef __BIG_ENDIAN 160 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; 161 #endif 162 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); 163 164 /* Initialize the ring buffer's read and write pointers */ 165 WREG32(DMA_RB_RPTR + sdma_offsets[i], 0); 166 WREG32(DMA_RB_WPTR + sdma_offsets[i], 0); 167 168 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 169 170 WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); 171 WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); 172 173 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; 174 175 WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 176 177 /* enable DMA IBs */ 178 ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE; 179 #ifdef __BIG_ENDIAN 180 ib_cntl |= DMA_IB_SWAP_ENABLE; 181 #endif 182 WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl); 183 184 dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); 185 dma_cntl &= ~CTXEMPTY_INT_ENABLE; 186 WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); 187 188 ring->wptr = 0; 189 WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); 190 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); 191 192 ring->ready = true; 193 194 r = amdgpu_ring_test_ring(ring); 195 if (r) { 196 ring->ready = false; 197 return r; 198 } 199 200 if (adev->mman.buffer_funcs_ring == ring) 201 amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size); 202 } 203 204 return 0; 205 } 206 207 /** 208 * si_dma_ring_test_ring - simple async dma engine test 209 * 210 * @ring: amdgpu_ring structure holding ring information 211 * 212 * Test the DMA engine by writing using it to write an 213 * value to memory. (VI). 214 * Returns 0 for success, error for failure. 215 */ 216 static int si_dma_ring_test_ring(struct amdgpu_ring *ring) 217 { 218 struct amdgpu_device *adev = ring->adev; 219 unsigned i; 220 unsigned index; 221 int r; 222 u32 tmp; 223 u64 gpu_addr; 224 225 r = amdgpu_device_wb_get(adev, &index); 226 if (r) { 227 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 228 return r; 229 } 230 231 gpu_addr = adev->wb.gpu_addr + (index * 4); 232 tmp = 0xCAFEDEAD; 233 adev->wb.wb[index] = cpu_to_le32(tmp); 234 235 r = amdgpu_ring_alloc(ring, 4); 236 if (r) { 237 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 238 amdgpu_device_wb_free(adev, index); 239 return r; 240 } 241 242 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1)); 243 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 244 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); 245 amdgpu_ring_write(ring, 0xDEADBEEF); 246 amdgpu_ring_commit(ring); 247 248 for (i = 0; i < adev->usec_timeout; i++) { 249 tmp = le32_to_cpu(adev->wb.wb[index]); 250 if (tmp == 0xDEADBEEF) 251 break; 252 DRM_UDELAY(1); 253 } 254 255 if (i < adev->usec_timeout) { 256 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 257 } else { 258 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 259 ring->idx, tmp); 260 r = -EINVAL; 261 } 262 amdgpu_device_wb_free(adev, index); 263 264 return r; 265 } 266 267 /** 268 * si_dma_ring_test_ib - test an IB on the DMA engine 269 * 270 * @ring: amdgpu_ring structure holding ring information 271 * 272 * Test a simple IB in the DMA ring (VI). 273 * Returns 0 on success, error on failure. 274 */ 275 static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout) 276 { 277 struct amdgpu_device *adev = ring->adev; 278 struct amdgpu_ib ib; 279 struct dma_fence *f = NULL; 280 unsigned index; 281 u32 tmp = 0; 282 u64 gpu_addr; 283 long r; 284 285 r = amdgpu_device_wb_get(adev, &index); 286 if (r) { 287 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 288 return r; 289 } 290 291 gpu_addr = adev->wb.gpu_addr + (index * 4); 292 tmp = 0xCAFEDEAD; 293 adev->wb.wb[index] = cpu_to_le32(tmp); 294 memset(&ib, 0, sizeof(ib)); 295 r = amdgpu_ib_get(adev, NULL, 256, &ib); 296 if (r) { 297 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 298 goto err0; 299 } 300 301 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, 1); 302 ib.ptr[1] = lower_32_bits(gpu_addr); 303 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; 304 ib.ptr[3] = 0xDEADBEEF; 305 ib.length_dw = 4; 306 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 307 if (r) 308 goto err1; 309 310 r = dma_fence_wait_timeout(f, false, timeout); 311 if (r == 0) { 312 DRM_ERROR("amdgpu: IB test timed out\n"); 313 r = -ETIMEDOUT; 314 goto err1; 315 } else if (r < 0) { 316 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 317 goto err1; 318 } 319 tmp = le32_to_cpu(adev->wb.wb[index]); 320 if (tmp == 0xDEADBEEF) { 321 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 322 r = 0; 323 } else { 324 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 325 r = -EINVAL; 326 } 327 328 err1: 329 amdgpu_ib_free(adev, &ib, NULL); 330 dma_fence_put(f); 331 err0: 332 amdgpu_device_wb_free(adev, index); 333 return r; 334 } 335 336 /** 337 * cik_dma_vm_copy_pte - update PTEs by copying them from the GART 338 * 339 * @ib: indirect buffer to fill with commands 340 * @pe: addr of the page entry 341 * @src: src addr to copy from 342 * @count: number of page entries to update 343 * 344 * Update PTEs by copying them from the GART using DMA (SI). 345 */ 346 static void si_dma_vm_copy_pte(struct amdgpu_ib *ib, 347 uint64_t pe, uint64_t src, 348 unsigned count) 349 { 350 unsigned bytes = count * 8; 351 352 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, 353 1, 0, 0, bytes); 354 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 355 ib->ptr[ib->length_dw++] = lower_32_bits(src); 356 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; 357 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; 358 } 359 360 /** 361 * si_dma_vm_write_pte - update PTEs by writing them manually 362 * 363 * @ib: indirect buffer to fill with commands 364 * @pe: addr of the page entry 365 * @value: dst addr to write into pe 366 * @count: number of page entries to update 367 * @incr: increase next addr by incr bytes 368 * 369 * Update PTEs by writing them manually using DMA (SI). 370 */ 371 static void si_dma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 372 uint64_t value, unsigned count, 373 uint32_t incr) 374 { 375 unsigned ndw = count * 2; 376 377 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw); 378 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 379 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 380 for (; ndw > 0; ndw -= 2) { 381 ib->ptr[ib->length_dw++] = lower_32_bits(value); 382 ib->ptr[ib->length_dw++] = upper_32_bits(value); 383 value += incr; 384 } 385 } 386 387 /** 388 * si_dma_vm_set_pte_pde - update the page tables using sDMA 389 * 390 * @ib: indirect buffer to fill with commands 391 * @pe: addr of the page entry 392 * @addr: dst addr to write into pe 393 * @count: number of page entries to update 394 * @incr: increase next addr by incr bytes 395 * @flags: access flags 396 * 397 * Update the page tables using sDMA (CIK). 398 */ 399 static void si_dma_vm_set_pte_pde(struct amdgpu_ib *ib, 400 uint64_t pe, 401 uint64_t addr, unsigned count, 402 uint32_t incr, uint64_t flags) 403 { 404 uint64_t value; 405 unsigned ndw; 406 407 while (count) { 408 ndw = count * 2; 409 if (ndw > 0xFFFFE) 410 ndw = 0xFFFFE; 411 412 if (flags & AMDGPU_PTE_VALID) 413 value = addr; 414 else 415 value = 0; 416 417 /* for physically contiguous pages (vram) */ 418 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); 419 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 420 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; 421 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 422 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 423 ib->ptr[ib->length_dw++] = value; /* value */ 424 ib->ptr[ib->length_dw++] = upper_32_bits(value); 425 ib->ptr[ib->length_dw++] = incr; /* increment size */ 426 ib->ptr[ib->length_dw++] = 0; 427 pe += ndw * 4; 428 addr += (ndw / 2) * incr; 429 count -= ndw / 2; 430 } 431 } 432 433 /** 434 * si_dma_pad_ib - pad the IB to the required number of dw 435 * 436 * @ib: indirect buffer to fill with padding 437 * 438 */ 439 static void si_dma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 440 { 441 while (ib->length_dw & 0x7) 442 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0); 443 } 444 445 /** 446 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline 447 * 448 * @ring: amdgpu_ring pointer 449 * 450 * Make sure all previous operations are completed (CIK). 451 */ 452 static void si_dma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 453 { 454 uint32_t seq = ring->fence_drv.sync_seq; 455 uint64_t addr = ring->fence_drv.gpu_addr; 456 457 /* wait for idle */ 458 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0) | 459 (1 << 27)); /* Poll memory */ 460 amdgpu_ring_write(ring, lower_32_bits(addr)); 461 amdgpu_ring_write(ring, (0xff << 16) | upper_32_bits(addr)); /* retry, addr_hi */ 462 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 463 amdgpu_ring_write(ring, seq); /* value */ 464 amdgpu_ring_write(ring, (3 << 28) | 0x20); /* func(equal) | poll interval */ 465 } 466 467 /** 468 * si_dma_ring_emit_vm_flush - cik vm flush using sDMA 469 * 470 * @ring: amdgpu_ring pointer 471 * @vm: amdgpu_vm pointer 472 * 473 * Update the page table base and flush the VM TLB 474 * using sDMA (VI). 475 */ 476 static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring, 477 unsigned vmid, unsigned pasid, 478 uint64_t pd_addr) 479 { 480 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pasid, pd_addr); 481 482 /* wait for invalidate to complete */ 483 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0)); 484 amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST); 485 amdgpu_ring_write(ring, 0xff << 16); /* retry */ 486 amdgpu_ring_write(ring, 1 << vmid); /* mask */ 487 amdgpu_ring_write(ring, 0); /* value */ 488 amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */ 489 } 490 491 static void si_dma_ring_emit_wreg(struct amdgpu_ring *ring, 492 uint32_t reg, uint32_t val) 493 { 494 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 495 amdgpu_ring_write(ring, (0xf << 16) | reg); 496 amdgpu_ring_write(ring, val); 497 } 498 499 static int si_dma_early_init(void *handle) 500 { 501 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 502 503 adev->sdma.num_instances = 2; 504 505 si_dma_set_ring_funcs(adev); 506 si_dma_set_buffer_funcs(adev); 507 si_dma_set_vm_pte_funcs(adev); 508 si_dma_set_irq_funcs(adev); 509 510 return 0; 511 } 512 513 static int si_dma_sw_init(void *handle) 514 { 515 struct amdgpu_ring *ring; 516 int r, i; 517 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 518 519 /* DMA0 trap event */ 520 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq); 521 if (r) 522 return r; 523 524 /* DMA1 trap event */ 525 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 244, &adev->sdma.trap_irq_1); 526 if (r) 527 return r; 528 529 for (i = 0; i < adev->sdma.num_instances; i++) { 530 ring = &adev->sdma.instance[i].ring; 531 ring->ring_obj = NULL; 532 ring->use_doorbell = false; 533 sprintf(ring->name, "sdma%d", i); 534 r = amdgpu_ring_init(adev, ring, 1024, 535 &adev->sdma.trap_irq, 536 (i == 0) ? 537 AMDGPU_SDMA_IRQ_TRAP0 : 538 AMDGPU_SDMA_IRQ_TRAP1); 539 if (r) 540 return r; 541 } 542 543 return r; 544 } 545 546 static int si_dma_sw_fini(void *handle) 547 { 548 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 549 int i; 550 551 for (i = 0; i < adev->sdma.num_instances; i++) 552 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 553 554 return 0; 555 } 556 557 static int si_dma_hw_init(void *handle) 558 { 559 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 560 561 return si_dma_start(adev); 562 } 563 564 static int si_dma_hw_fini(void *handle) 565 { 566 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 567 568 si_dma_stop(adev); 569 570 return 0; 571 } 572 573 static int si_dma_suspend(void *handle) 574 { 575 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 576 577 return si_dma_hw_fini(adev); 578 } 579 580 static int si_dma_resume(void *handle) 581 { 582 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 583 584 return si_dma_hw_init(adev); 585 } 586 587 static bool si_dma_is_idle(void *handle) 588 { 589 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 590 u32 tmp = RREG32(SRBM_STATUS2); 591 592 if (tmp & (DMA_BUSY_MASK | DMA1_BUSY_MASK)) 593 return false; 594 595 return true; 596 } 597 598 static int si_dma_wait_for_idle(void *handle) 599 { 600 unsigned i; 601 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 602 603 for (i = 0; i < adev->usec_timeout; i++) { 604 if (si_dma_is_idle(handle)) 605 return 0; 606 udelay(1); 607 } 608 return -ETIMEDOUT; 609 } 610 611 static int si_dma_soft_reset(void *handle) 612 { 613 DRM_INFO("si_dma_soft_reset --- not implemented !!!!!!!\n"); 614 return 0; 615 } 616 617 static int si_dma_set_trap_irq_state(struct amdgpu_device *adev, 618 struct amdgpu_irq_src *src, 619 unsigned type, 620 enum amdgpu_interrupt_state state) 621 { 622 u32 sdma_cntl; 623 624 switch (type) { 625 case AMDGPU_SDMA_IRQ_TRAP0: 626 switch (state) { 627 case AMDGPU_IRQ_STATE_DISABLE: 628 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); 629 sdma_cntl &= ~TRAP_ENABLE; 630 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); 631 break; 632 case AMDGPU_IRQ_STATE_ENABLE: 633 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); 634 sdma_cntl |= TRAP_ENABLE; 635 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); 636 break; 637 default: 638 break; 639 } 640 break; 641 case AMDGPU_SDMA_IRQ_TRAP1: 642 switch (state) { 643 case AMDGPU_IRQ_STATE_DISABLE: 644 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); 645 sdma_cntl &= ~TRAP_ENABLE; 646 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); 647 break; 648 case AMDGPU_IRQ_STATE_ENABLE: 649 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); 650 sdma_cntl |= TRAP_ENABLE; 651 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); 652 break; 653 default: 654 break; 655 } 656 break; 657 default: 658 break; 659 } 660 return 0; 661 } 662 663 static int si_dma_process_trap_irq(struct amdgpu_device *adev, 664 struct amdgpu_irq_src *source, 665 struct amdgpu_iv_entry *entry) 666 { 667 amdgpu_fence_process(&adev->sdma.instance[0].ring); 668 669 return 0; 670 } 671 672 static int si_dma_process_trap_irq_1(struct amdgpu_device *adev, 673 struct amdgpu_irq_src *source, 674 struct amdgpu_iv_entry *entry) 675 { 676 amdgpu_fence_process(&adev->sdma.instance[1].ring); 677 678 return 0; 679 } 680 681 static int si_dma_process_illegal_inst_irq(struct amdgpu_device *adev, 682 struct amdgpu_irq_src *source, 683 struct amdgpu_iv_entry *entry) 684 { 685 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 686 schedule_work(&adev->reset_work); 687 return 0; 688 } 689 690 static int si_dma_set_clockgating_state(void *handle, 691 enum amd_clockgating_state state) 692 { 693 u32 orig, data, offset; 694 int i; 695 bool enable; 696 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 697 698 enable = (state == AMD_CG_STATE_GATE) ? true : false; 699 700 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 701 for (i = 0; i < adev->sdma.num_instances; i++) { 702 if (i == 0) 703 offset = DMA0_REGISTER_OFFSET; 704 else 705 offset = DMA1_REGISTER_OFFSET; 706 orig = data = RREG32(DMA_POWER_CNTL + offset); 707 data &= ~MEM_POWER_OVERRIDE; 708 if (data != orig) 709 WREG32(DMA_POWER_CNTL + offset, data); 710 WREG32(DMA_CLK_CTRL + offset, 0x00000100); 711 } 712 } else { 713 for (i = 0; i < adev->sdma.num_instances; i++) { 714 if (i == 0) 715 offset = DMA0_REGISTER_OFFSET; 716 else 717 offset = DMA1_REGISTER_OFFSET; 718 orig = data = RREG32(DMA_POWER_CNTL + offset); 719 data |= MEM_POWER_OVERRIDE; 720 if (data != orig) 721 WREG32(DMA_POWER_CNTL + offset, data); 722 723 orig = data = RREG32(DMA_CLK_CTRL + offset); 724 data = 0xff000000; 725 if (data != orig) 726 WREG32(DMA_CLK_CTRL + offset, data); 727 } 728 } 729 730 return 0; 731 } 732 733 static int si_dma_set_powergating_state(void *handle, 734 enum amd_powergating_state state) 735 { 736 u32 tmp; 737 738 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 739 740 WREG32(DMA_PGFSM_WRITE, 0x00002000); 741 WREG32(DMA_PGFSM_CONFIG, 0x100010ff); 742 743 for (tmp = 0; tmp < 5; tmp++) 744 WREG32(DMA_PGFSM_WRITE, 0); 745 746 return 0; 747 } 748 749 static const struct amd_ip_funcs si_dma_ip_funcs = { 750 .name = "si_dma", 751 .early_init = si_dma_early_init, 752 .late_init = NULL, 753 .sw_init = si_dma_sw_init, 754 .sw_fini = si_dma_sw_fini, 755 .hw_init = si_dma_hw_init, 756 .hw_fini = si_dma_hw_fini, 757 .suspend = si_dma_suspend, 758 .resume = si_dma_resume, 759 .is_idle = si_dma_is_idle, 760 .wait_for_idle = si_dma_wait_for_idle, 761 .soft_reset = si_dma_soft_reset, 762 .set_clockgating_state = si_dma_set_clockgating_state, 763 .set_powergating_state = si_dma_set_powergating_state, 764 }; 765 766 static const struct amdgpu_ring_funcs si_dma_ring_funcs = { 767 .type = AMDGPU_RING_TYPE_SDMA, 768 .align_mask = 0xf, 769 .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), 770 .support_64bit_ptrs = false, 771 .get_rptr = si_dma_ring_get_rptr, 772 .get_wptr = si_dma_ring_get_wptr, 773 .set_wptr = si_dma_ring_set_wptr, 774 .emit_frame_size = 775 3 + /* si_dma_ring_emit_hdp_flush */ 776 3 + /* si_dma_ring_emit_hdp_invalidate */ 777 6 + /* si_dma_ring_emit_pipeline_sync */ 778 SI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* si_dma_ring_emit_vm_flush */ 779 9 + 9 + 9, /* si_dma_ring_emit_fence x3 for user fence, vm fence */ 780 .emit_ib_size = 7 + 3, /* si_dma_ring_emit_ib */ 781 .emit_ib = si_dma_ring_emit_ib, 782 .emit_fence = si_dma_ring_emit_fence, 783 .emit_pipeline_sync = si_dma_ring_emit_pipeline_sync, 784 .emit_vm_flush = si_dma_ring_emit_vm_flush, 785 .emit_hdp_flush = si_dma_ring_emit_hdp_flush, 786 .emit_hdp_invalidate = si_dma_ring_emit_hdp_invalidate, 787 .test_ring = si_dma_ring_test_ring, 788 .test_ib = si_dma_ring_test_ib, 789 .insert_nop = amdgpu_ring_insert_nop, 790 .pad_ib = si_dma_ring_pad_ib, 791 .emit_wreg = si_dma_ring_emit_wreg, 792 }; 793 794 static void si_dma_set_ring_funcs(struct amdgpu_device *adev) 795 { 796 int i; 797 798 for (i = 0; i < adev->sdma.num_instances; i++) 799 adev->sdma.instance[i].ring.funcs = &si_dma_ring_funcs; 800 } 801 802 static const struct amdgpu_irq_src_funcs si_dma_trap_irq_funcs = { 803 .set = si_dma_set_trap_irq_state, 804 .process = si_dma_process_trap_irq, 805 }; 806 807 static const struct amdgpu_irq_src_funcs si_dma_trap_irq_funcs_1 = { 808 .set = si_dma_set_trap_irq_state, 809 .process = si_dma_process_trap_irq_1, 810 }; 811 812 static const struct amdgpu_irq_src_funcs si_dma_illegal_inst_irq_funcs = { 813 .process = si_dma_process_illegal_inst_irq, 814 }; 815 816 static void si_dma_set_irq_funcs(struct amdgpu_device *adev) 817 { 818 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 819 adev->sdma.trap_irq.funcs = &si_dma_trap_irq_funcs; 820 adev->sdma.trap_irq_1.funcs = &si_dma_trap_irq_funcs_1; 821 adev->sdma.illegal_inst_irq.funcs = &si_dma_illegal_inst_irq_funcs; 822 } 823 824 /** 825 * si_dma_emit_copy_buffer - copy buffer using the sDMA engine 826 * 827 * @ring: amdgpu_ring structure holding ring information 828 * @src_offset: src GPU address 829 * @dst_offset: dst GPU address 830 * @byte_count: number of bytes to xfer 831 * 832 * Copy GPU buffers using the DMA engine (VI). 833 * Used by the amdgpu ttm implementation to move pages if 834 * registered as the asic copy callback. 835 */ 836 static void si_dma_emit_copy_buffer(struct amdgpu_ib *ib, 837 uint64_t src_offset, 838 uint64_t dst_offset, 839 uint32_t byte_count) 840 { 841 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, 842 1, 0, 0, byte_count); 843 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 844 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 845 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) & 0xff; 846 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset) & 0xff; 847 } 848 849 /** 850 * si_dma_emit_fill_buffer - fill buffer using the sDMA engine 851 * 852 * @ring: amdgpu_ring structure holding ring information 853 * @src_data: value to write to buffer 854 * @dst_offset: dst GPU address 855 * @byte_count: number of bytes to xfer 856 * 857 * Fill GPU buffers using the DMA engine (VI). 858 */ 859 static void si_dma_emit_fill_buffer(struct amdgpu_ib *ib, 860 uint32_t src_data, 861 uint64_t dst_offset, 862 uint32_t byte_count) 863 { 864 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_CONSTANT_FILL, 865 0, 0, 0, byte_count / 4); 866 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 867 ib->ptr[ib->length_dw++] = src_data; 868 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset) << 16; 869 } 870 871 872 static const struct amdgpu_buffer_funcs si_dma_buffer_funcs = { 873 .copy_max_bytes = 0xffff8, 874 .copy_num_dw = 5, 875 .emit_copy_buffer = si_dma_emit_copy_buffer, 876 877 .fill_max_bytes = 0xffff8, 878 .fill_num_dw = 4, 879 .emit_fill_buffer = si_dma_emit_fill_buffer, 880 }; 881 882 static void si_dma_set_buffer_funcs(struct amdgpu_device *adev) 883 { 884 if (adev->mman.buffer_funcs == NULL) { 885 adev->mman.buffer_funcs = &si_dma_buffer_funcs; 886 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 887 } 888 } 889 890 static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = { 891 .copy_pte_num_dw = 5, 892 .copy_pte = si_dma_vm_copy_pte, 893 894 .write_pte = si_dma_vm_write_pte, 895 896 .set_max_nums_pte_pde = 0xffff8 >> 3, 897 .set_pte_pde_num_dw = 9, 898 .set_pte_pde = si_dma_vm_set_pte_pde, 899 }; 900 901 static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev) 902 { 903 unsigned i; 904 905 if (adev->vm_manager.vm_pte_funcs == NULL) { 906 adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; 907 for (i = 0; i < adev->sdma.num_instances; i++) 908 adev->vm_manager.vm_pte_rings[i] = 909 &adev->sdma.instance[i].ring; 910 911 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 912 } 913 } 914 915 const struct amdgpu_ip_block_version si_dma_ip_block = 916 { 917 .type = AMD_IP_BLOCK_TYPE_SDMA, 918 .major = 1, 919 .minor = 0, 920 .rev = 0, 921 .funcs = &si_dma_ip_funcs, 922 }; 923