1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_11_0_0_offset.h" 34 #include "gc/gc_11_0_0_sh_mask.h" 35 #include "gc/gc_11_0_0_default.h" 36 #include "hdp/hdp_6_0_0_offset.h" 37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "sdma_v6_0_0_pkt_open.h" 42 #include "nbio_v4_3.h" 43 #include "sdma_common.h" 44 #include "sdma_v6_0.h" 45 #include "v11_structs.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); 50 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); 51 52 #define SDMA1_REG_OFFSET 0x600 53 #define SDMA0_HYP_DEC_REG_START 0x5880 54 #define SDMA0_HYP_DEC_REG_END 0x589a 55 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 56 57 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); 58 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); 59 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); 60 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); 61 static int sdma_v6_0_start(struct amdgpu_device *adev); 62 63 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 64 { 65 u32 base; 66 67 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 68 internal_offset <= SDMA0_HYP_DEC_REG_END) { 69 base = adev->reg_offset[GC_HWIP][0][1]; 70 if (instance != 0) 71 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 72 } else { 73 base = adev->reg_offset[GC_HWIP][0][0]; 74 if (instance == 1) 75 internal_offset += SDMA1_REG_OFFSET; 76 } 77 78 return base + internal_offset; 79 } 80 81 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring) 82 { 83 unsigned ret; 84 85 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 86 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 87 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 88 amdgpu_ring_write(ring, 1); 89 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 90 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 91 92 return ret; 93 } 94 95 static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 96 unsigned offset) 97 { 98 unsigned cur; 99 100 BUG_ON(offset > ring->buf_mask); 101 BUG_ON(ring->ring[offset] != 0x55aa55aa); 102 103 cur = (ring->wptr - 1) & ring->buf_mask; 104 if (cur > offset) 105 ring->ring[offset] = cur - offset; 106 else 107 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 108 } 109 110 /** 111 * sdma_v6_0_ring_get_rptr - get the current read pointer 112 * 113 * @ring: amdgpu ring pointer 114 * 115 * Get the current rptr from the hardware. 116 */ 117 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 118 { 119 u64 *rptr; 120 121 /* XXX check if swapping is necessary on BE */ 122 rptr = (u64 *)ring->rptr_cpu_addr; 123 124 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 125 return ((*rptr) >> 2); 126 } 127 128 /** 129 * sdma_v6_0_ring_get_wptr - get the current write pointer 130 * 131 * @ring: amdgpu ring pointer 132 * 133 * Get the current wptr from the hardware. 134 */ 135 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 136 { 137 u64 wptr = 0; 138 139 if (ring->use_doorbell) { 140 /* XXX check if swapping is necessary on BE */ 141 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 142 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 143 } 144 145 return wptr >> 2; 146 } 147 148 /** 149 * sdma_v6_0_ring_set_wptr - commit the write pointer 150 * 151 * @ring: amdgpu ring pointer 152 * 153 * Write the wptr back to the hardware. 154 */ 155 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 156 { 157 struct amdgpu_device *adev = ring->adev; 158 uint32_t *wptr_saved; 159 uint32_t *is_queue_unmap; 160 uint64_t aggregated_db_index; 161 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size; 162 163 DRM_DEBUG("Setting write pointer\n"); 164 165 if (ring->is_mes_queue) { 166 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 167 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 168 sizeof(uint32_t)); 169 aggregated_db_index = 170 amdgpu_mes_get_aggregated_doorbell_index(adev, 171 ring->hw_prio); 172 173 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 174 ring->wptr << 2); 175 *wptr_saved = ring->wptr << 2; 176 if (*is_queue_unmap) { 177 WDOORBELL64(aggregated_db_index, ring->wptr << 2); 178 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 179 ring->doorbell_index, ring->wptr << 2); 180 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 181 } else { 182 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 183 ring->doorbell_index, ring->wptr << 2); 184 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 185 186 if (*is_queue_unmap) 187 WDOORBELL64(aggregated_db_index, 188 ring->wptr << 2); 189 } 190 } else { 191 if (ring->use_doorbell) { 192 DRM_DEBUG("Using doorbell -- " 193 "wptr_offs == 0x%08x " 194 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 195 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 196 ring->wptr_offs, 197 lower_32_bits(ring->wptr << 2), 198 upper_32_bits(ring->wptr << 2)); 199 /* XXX check if swapping is necessary on BE */ 200 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 201 ring->wptr << 2); 202 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 203 ring->doorbell_index, ring->wptr << 2); 204 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 205 } else { 206 DRM_DEBUG("Not using doorbell -- " 207 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 208 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 209 ring->me, 210 lower_32_bits(ring->wptr << 2), 211 ring->me, 212 upper_32_bits(ring->wptr << 2)); 213 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 214 ring->me, regSDMA0_QUEUE0_RB_WPTR), 215 lower_32_bits(ring->wptr << 2)); 216 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 217 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI), 218 upper_32_bits(ring->wptr << 2)); 219 } 220 } 221 } 222 223 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 224 { 225 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 226 int i; 227 228 for (i = 0; i < count; i++) 229 if (sdma && sdma->burst_nop && (i == 0)) 230 amdgpu_ring_write(ring, ring->funcs->nop | 231 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 232 else 233 amdgpu_ring_write(ring, ring->funcs->nop); 234 } 235 236 /** 237 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine 238 * 239 * @ring: amdgpu ring pointer 240 * @ib: IB object to schedule 241 * @flags: unused 242 * @job: job to retrieve vmid from 243 * 244 * Schedule an IB in the DMA ring. 245 */ 246 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 247 struct amdgpu_job *job, 248 struct amdgpu_ib *ib, 249 uint32_t flags) 250 { 251 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 252 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 253 254 /* An IB packet must end on a 8 DW boundary--the next dword 255 * must be on a 8-dword boundary. Our IB packet below is 6 256 * dwords long, thus add x number of NOPs, such that, in 257 * modular arithmetic, 258 * wptr + 6 + x = 8k, k >= 0, which in C is, 259 * (wptr + 6 + x) % 8 = 0. 260 * The expression below, is a solution of x. 261 */ 262 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 263 264 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 265 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 266 /* base must be 32 byte aligned */ 267 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 268 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 269 amdgpu_ring_write(ring, ib->length_dw); 270 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 271 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 272 } 273 274 /** 275 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 276 * 277 * @ring: amdgpu ring pointer 278 * 279 * flush the IB by graphics cache rinse. 280 */ 281 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 282 { 283 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 284 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 285 SDMA_GCR_GLI_INV(1); 286 287 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 288 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 289 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 290 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 291 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 292 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 293 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 294 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 295 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 296 } 297 298 299 /** 300 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 301 * 302 * @ring: amdgpu ring pointer 303 * 304 * Emit an hdp flush packet on the requested DMA ring. 305 */ 306 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 307 { 308 struct amdgpu_device *adev = ring->adev; 309 u32 ref_and_mask = 0; 310 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 311 312 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 313 314 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 315 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 316 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 317 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 318 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 319 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 320 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 321 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 322 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 323 } 324 325 /** 326 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring 327 * 328 * @ring: amdgpu ring pointer 329 * @addr: address 330 * @seq: fence seq number 331 * @flags: fence flags 332 * 333 * Add a DMA fence packet to the ring to write 334 * the fence seq number and DMA trap packet to generate 335 * an interrupt if needed. 336 */ 337 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 338 unsigned flags) 339 { 340 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 341 /* write the fence */ 342 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 343 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 344 /* zero in first two bits */ 345 BUG_ON(addr & 0x3); 346 amdgpu_ring_write(ring, lower_32_bits(addr)); 347 amdgpu_ring_write(ring, upper_32_bits(addr)); 348 amdgpu_ring_write(ring, lower_32_bits(seq)); 349 350 /* optionally write high bits as well */ 351 if (write64bit) { 352 addr += 4; 353 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 354 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 355 /* zero in first two bits */ 356 BUG_ON(addr & 0x3); 357 amdgpu_ring_write(ring, lower_32_bits(addr)); 358 amdgpu_ring_write(ring, upper_32_bits(addr)); 359 amdgpu_ring_write(ring, upper_32_bits(seq)); 360 } 361 362 if (flags & AMDGPU_FENCE_FLAG_INT) { 363 uint32_t ctx = ring->is_mes_queue ? 364 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 365 /* generate an interrupt */ 366 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 367 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 368 } 369 } 370 371 /** 372 * sdma_v6_0_gfx_stop - stop the gfx async dma engines 373 * 374 * @adev: amdgpu_device pointer 375 * 376 * Stop the gfx async dma ring buffers. 377 */ 378 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev) 379 { 380 u32 rb_cntl, ib_cntl; 381 int i; 382 383 amdgpu_sdma_unset_buffer_funcs_helper(adev); 384 385 for (i = 0; i < adev->sdma.num_instances; i++) { 386 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 387 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 388 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 389 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 390 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 391 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 392 } 393 } 394 395 /** 396 * sdma_v6_0_rlc_stop - stop the compute async dma engines 397 * 398 * @adev: amdgpu_device pointer 399 * 400 * Stop the compute async dma queues. 401 */ 402 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev) 403 { 404 /* XXX todo */ 405 } 406 407 /** 408 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts 409 * 410 * @adev: amdgpu_device pointer 411 * @enable: enable/disable context switching due to queue empty conditions 412 * 413 * Enable or disable the async dma engines queue empty context switch. 414 */ 415 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable) 416 { 417 u32 f32_cntl; 418 int i; 419 420 if (!amdgpu_sriov_vf(adev)) { 421 for (i = 0; i < adev->sdma.num_instances; i++) { 422 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL)); 423 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 424 CTXEMPTY_INT_ENABLE, enable ? 1 : 0); 425 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl); 426 } 427 } 428 } 429 430 /** 431 * sdma_v6_0_enable - stop the async dma engines 432 * 433 * @adev: amdgpu_device pointer 434 * @enable: enable/disable the DMA MEs. 435 * 436 * Halt or unhalt the async dma engines. 437 */ 438 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) 439 { 440 u32 f32_cntl; 441 int i; 442 443 if (!enable) { 444 sdma_v6_0_gfx_stop(adev); 445 sdma_v6_0_rlc_stop(adev); 446 } 447 448 if (amdgpu_sriov_vf(adev)) 449 return; 450 451 for (i = 0; i < adev->sdma.num_instances; i++) { 452 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 453 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 454 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); 455 } 456 } 457 458 /** 459 * sdma_v6_0_gfx_resume - setup and start the async dma engines 460 * 461 * @adev: amdgpu_device pointer 462 * 463 * Set up the gfx DMA ring buffers and enable them. 464 * Returns 0 for success, error for failure. 465 */ 466 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 467 { 468 struct amdgpu_ring *ring; 469 u32 rb_cntl, ib_cntl; 470 u32 rb_bufsz; 471 u32 doorbell; 472 u32 doorbell_offset; 473 u32 temp; 474 u64 wptr_gpu_addr; 475 int i, r; 476 477 for (i = 0; i < adev->sdma.num_instances; i++) { 478 ring = &adev->sdma.instance[i].ring; 479 480 if (!amdgpu_sriov_vf(adev)) 481 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 482 483 /* Set ring buffer size in dwords */ 484 rb_bufsz = order_base_2(ring->ring_size / 4); 485 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 486 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 487 #ifdef __BIG_ENDIAN 488 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 489 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 490 RPTR_WRITEBACK_SWAP_ENABLE, 1); 491 #endif 492 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 493 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 494 495 /* Initialize the ring buffer's read and write pointers */ 496 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 497 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 498 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 499 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 500 501 /* setup the wptr shadow polling */ 502 wptr_gpu_addr = ring->wptr_gpu_addr; 503 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 504 lower_32_bits(wptr_gpu_addr)); 505 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 506 upper_32_bits(wptr_gpu_addr)); 507 508 /* set the wb address whether it's enabled or not */ 509 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 510 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 511 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 512 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 513 514 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 515 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 516 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); 517 518 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 519 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 520 521 ring->wptr = 0; 522 523 /* before programing wptr to a less value, need set minor_ptr_update first */ 524 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 525 526 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 527 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 528 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 529 } 530 531 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 532 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 533 534 if (ring->use_doorbell) { 535 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 536 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 537 OFFSET, ring->doorbell_index); 538 } else { 539 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 540 } 541 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 542 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 543 544 if (i == 0) 545 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 546 ring->doorbell_index, 547 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 548 549 if (amdgpu_sriov_vf(adev)) 550 sdma_v6_0_ring_set_wptr(ring); 551 552 /* set minor_ptr_update to 0 after wptr programed */ 553 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 554 555 /* Set up RESP_MODE to non-copy addresses */ 556 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 557 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 558 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 559 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 560 561 /* program default cache read and write policy */ 562 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 563 /* clean read policy and write policy bits */ 564 temp &= 0xFF0FFF; 565 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 566 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 567 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 568 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 569 570 if (!amdgpu_sriov_vf(adev)) { 571 /* unhalt engine */ 572 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 573 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 574 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); 575 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); 576 } 577 578 /* enable DMA RB */ 579 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 580 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 581 582 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 583 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 584 #ifdef __BIG_ENDIAN 585 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 586 #endif 587 /* enable DMA IBs */ 588 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 589 590 if (amdgpu_sriov_vf(adev)) 591 sdma_v6_0_enable(adev, true); 592 593 r = amdgpu_ring_test_helper(ring); 594 if (r) 595 return r; 596 597 if (adev->mman.buffer_funcs_ring == ring) 598 amdgpu_ttm_set_buffer_funcs_status(adev, true); 599 } 600 601 return 0; 602 } 603 604 /** 605 * sdma_v6_0_rlc_resume - setup and start the async dma engines 606 * 607 * @adev: amdgpu_device pointer 608 * 609 * Set up the compute DMA queues and enable them. 610 * Returns 0 for success, error for failure. 611 */ 612 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev) 613 { 614 return 0; 615 } 616 617 /** 618 * sdma_v6_0_load_microcode - load the sDMA ME ucode 619 * 620 * @adev: amdgpu_device pointer 621 * 622 * Loads the sDMA0/1 ucode. 623 * Returns 0 for success, -EINVAL if the ucode is not available. 624 */ 625 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev) 626 { 627 const struct sdma_firmware_header_v2_0 *hdr; 628 const __le32 *fw_data; 629 u32 fw_size; 630 int i, j; 631 bool use_broadcast; 632 633 /* halt the MEs */ 634 sdma_v6_0_enable(adev, false); 635 636 if (!adev->sdma.instance[0].fw) 637 return -EINVAL; 638 639 /* use broadcast mode to load SDMA microcode by default */ 640 use_broadcast = true; 641 642 if (use_broadcast) { 643 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n"); 644 /* load Control Thread microcode */ 645 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 646 amdgpu_ucode_print_sdma_hdr(&hdr->header); 647 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 648 649 fw_data = (const __le32 *) 650 (adev->sdma.instance[0].fw->data + 651 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 652 653 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0); 654 655 for (j = 0; j < fw_size; j++) { 656 if (amdgpu_emu_mode == 1 && j % 500 == 0) 657 msleep(1); 658 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 659 } 660 661 /* load Context Switch microcode */ 662 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 663 664 fw_data = (const __le32 *) 665 (adev->sdma.instance[0].fw->data + 666 le32_to_cpu(hdr->ctl_ucode_offset)); 667 668 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000); 669 670 for (j = 0; j < fw_size; j++) { 671 if (amdgpu_emu_mode == 1 && j % 500 == 0) 672 msleep(1); 673 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 674 } 675 } else { 676 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n"); 677 for (i = 0; i < adev->sdma.num_instances; i++) { 678 /* load Control Thread microcode */ 679 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 680 amdgpu_ucode_print_sdma_hdr(&hdr->header); 681 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 682 683 fw_data = (const __le32 *) 684 (adev->sdma.instance[0].fw->data + 685 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 686 687 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0); 688 689 for (j = 0; j < fw_size; j++) { 690 if (amdgpu_emu_mode == 1 && j % 500 == 0) 691 msleep(1); 692 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 693 } 694 695 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 696 697 /* load Context Switch microcode */ 698 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 699 700 fw_data = (const __le32 *) 701 (adev->sdma.instance[0].fw->data + 702 le32_to_cpu(hdr->ctl_ucode_offset)); 703 704 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000); 705 706 for (j = 0; j < fw_size; j++) { 707 if (amdgpu_emu_mode == 1 && j % 500 == 0) 708 msleep(1); 709 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 710 } 711 712 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 713 } 714 } 715 716 return 0; 717 } 718 719 static int sdma_v6_0_soft_reset(void *handle) 720 { 721 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 722 u32 tmp; 723 int i; 724 725 sdma_v6_0_gfx_stop(adev); 726 727 for (i = 0; i < adev->sdma.num_instances; i++) { 728 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 729 tmp |= SDMA0_FREEZE__FREEZE_MASK; 730 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 731 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 732 tmp |= SDMA0_F32_CNTL__HALT_MASK; 733 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK; 734 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); 735 736 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 737 738 udelay(100); 739 740 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 741 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 742 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 743 744 udelay(100); 745 746 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 747 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 748 749 udelay(100); 750 } 751 752 return sdma_v6_0_start(adev); 753 } 754 755 static bool sdma_v6_0_check_soft_reset(void *handle) 756 { 757 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 758 struct amdgpu_ring *ring; 759 int i, r; 760 long tmo = msecs_to_jiffies(1000); 761 762 for (i = 0; i < adev->sdma.num_instances; i++) { 763 ring = &adev->sdma.instance[i].ring; 764 r = amdgpu_ring_test_ib(ring, tmo); 765 if (r) 766 return true; 767 } 768 769 return false; 770 } 771 772 /** 773 * sdma_v6_0_start - setup and start the async dma engines 774 * 775 * @adev: amdgpu_device pointer 776 * 777 * Set up the DMA engines and enable them. 778 * Returns 0 for success, error for failure. 779 */ 780 static int sdma_v6_0_start(struct amdgpu_device *adev) 781 { 782 int r = 0; 783 784 if (amdgpu_sriov_vf(adev)) { 785 sdma_v6_0_enable(adev, false); 786 787 /* set RB registers */ 788 r = sdma_v6_0_gfx_resume(adev); 789 return r; 790 } 791 792 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 793 r = sdma_v6_0_load_microcode(adev); 794 if (r) 795 return r; 796 797 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */ 798 if (amdgpu_emu_mode == 1) 799 msleep(1000); 800 } 801 802 /* unhalt the MEs */ 803 sdma_v6_0_enable(adev, true); 804 /* enable sdma ring preemption */ 805 sdma_v6_0_ctxempty_int_enable(adev, true); 806 807 /* start the gfx rings and rlc compute queues */ 808 r = sdma_v6_0_gfx_resume(adev); 809 if (r) 810 return r; 811 r = sdma_v6_0_rlc_resume(adev); 812 813 return r; 814 } 815 816 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd, 817 struct amdgpu_mqd_prop *prop) 818 { 819 struct v11_sdma_mqd *m = mqd; 820 uint64_t wb_gpu_addr; 821 822 m->sdmax_rlcx_rb_cntl = 823 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 824 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 825 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 826 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; 827 828 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 829 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 830 831 wb_gpu_addr = prop->wptr_gpu_addr; 832 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 833 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 834 835 wb_gpu_addr = prop->rptr_gpu_addr; 836 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 837 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 838 839 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0, 840 regSDMA0_QUEUE0_IB_CNTL)); 841 842 m->sdmax_rlcx_doorbell_offset = 843 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 844 845 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 846 847 m->sdmax_rlcx_skip_cntl = 0; 848 m->sdmax_rlcx_context_status = 0; 849 m->sdmax_rlcx_doorbell_log = 0; 850 851 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 852 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 853 854 return 0; 855 } 856 857 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev) 858 { 859 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd); 860 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init; 861 } 862 863 /** 864 * sdma_v6_0_ring_test_ring - simple async dma engine test 865 * 866 * @ring: amdgpu_ring structure holding ring information 867 * 868 * Test the DMA engine by writing using it to write an 869 * value to memory. 870 * Returns 0 for success, error for failure. 871 */ 872 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) 873 { 874 struct amdgpu_device *adev = ring->adev; 875 unsigned i; 876 unsigned index; 877 int r; 878 u32 tmp; 879 u64 gpu_addr; 880 volatile uint32_t *cpu_ptr = NULL; 881 882 tmp = 0xCAFEDEAD; 883 884 if (ring->is_mes_queue) { 885 uint32_t offset = 0; 886 offset = amdgpu_mes_ctx_get_offs(ring, 887 AMDGPU_MES_CTX_PADDING_OFFS); 888 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 889 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 890 *cpu_ptr = tmp; 891 } else { 892 r = amdgpu_device_wb_get(adev, &index); 893 if (r) { 894 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 895 return r; 896 } 897 898 gpu_addr = adev->wb.gpu_addr + (index * 4); 899 adev->wb.wb[index] = cpu_to_le32(tmp); 900 } 901 902 r = amdgpu_ring_alloc(ring, 5); 903 if (r) { 904 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 905 amdgpu_device_wb_free(adev, index); 906 return r; 907 } 908 909 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 910 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 911 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 912 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 913 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 914 amdgpu_ring_write(ring, 0xDEADBEEF); 915 amdgpu_ring_commit(ring); 916 917 for (i = 0; i < adev->usec_timeout; i++) { 918 if (ring->is_mes_queue) 919 tmp = le32_to_cpu(*cpu_ptr); 920 else 921 tmp = le32_to_cpu(adev->wb.wb[index]); 922 if (tmp == 0xDEADBEEF) 923 break; 924 if (amdgpu_emu_mode == 1) 925 msleep(1); 926 else 927 udelay(1); 928 } 929 930 if (i >= adev->usec_timeout) 931 r = -ETIMEDOUT; 932 933 if (!ring->is_mes_queue) 934 amdgpu_device_wb_free(adev, index); 935 936 return r; 937 } 938 939 /** 940 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine 941 * 942 * @ring: amdgpu_ring structure holding ring information 943 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 944 * 945 * Test a simple IB in the DMA ring. 946 * Returns 0 on success, error on failure. 947 */ 948 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 949 { 950 struct amdgpu_device *adev = ring->adev; 951 struct amdgpu_ib ib; 952 struct dma_fence *f = NULL; 953 unsigned index; 954 long r; 955 u32 tmp = 0; 956 u64 gpu_addr; 957 volatile uint32_t *cpu_ptr = NULL; 958 959 tmp = 0xCAFEDEAD; 960 memset(&ib, 0, sizeof(ib)); 961 962 if (ring->is_mes_queue) { 963 uint32_t offset = 0; 964 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 965 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 966 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 967 968 offset = amdgpu_mes_ctx_get_offs(ring, 969 AMDGPU_MES_CTX_PADDING_OFFS); 970 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 971 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 972 *cpu_ptr = tmp; 973 } else { 974 r = amdgpu_device_wb_get(adev, &index); 975 if (r) { 976 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 977 return r; 978 } 979 980 gpu_addr = adev->wb.gpu_addr + (index * 4); 981 adev->wb.wb[index] = cpu_to_le32(tmp); 982 983 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 984 if (r) { 985 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 986 goto err0; 987 } 988 } 989 990 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 991 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 992 ib.ptr[1] = lower_32_bits(gpu_addr); 993 ib.ptr[2] = upper_32_bits(gpu_addr); 994 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 995 ib.ptr[4] = 0xDEADBEEF; 996 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 997 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 998 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 999 ib.length_dw = 8; 1000 1001 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1002 if (r) 1003 goto err1; 1004 1005 r = dma_fence_wait_timeout(f, false, timeout); 1006 if (r == 0) { 1007 DRM_ERROR("amdgpu: IB test timed out\n"); 1008 r = -ETIMEDOUT; 1009 goto err1; 1010 } else if (r < 0) { 1011 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1012 goto err1; 1013 } 1014 1015 if (ring->is_mes_queue) 1016 tmp = le32_to_cpu(*cpu_ptr); 1017 else 1018 tmp = le32_to_cpu(adev->wb.wb[index]); 1019 1020 if (tmp == 0xDEADBEEF) 1021 r = 0; 1022 else 1023 r = -EINVAL; 1024 1025 err1: 1026 amdgpu_ib_free(adev, &ib, NULL); 1027 dma_fence_put(f); 1028 err0: 1029 if (!ring->is_mes_queue) 1030 amdgpu_device_wb_free(adev, index); 1031 return r; 1032 } 1033 1034 1035 /** 1036 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART 1037 * 1038 * @ib: indirect buffer to fill with commands 1039 * @pe: addr of the page entry 1040 * @src: src addr to copy from 1041 * @count: number of page entries to update 1042 * 1043 * Update PTEs by copying them from the GART using sDMA. 1044 */ 1045 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib, 1046 uint64_t pe, uint64_t src, 1047 unsigned count) 1048 { 1049 unsigned bytes = count * 8; 1050 1051 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1052 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1053 ib->ptr[ib->length_dw++] = bytes - 1; 1054 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1055 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1056 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1057 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1058 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1059 1060 } 1061 1062 /** 1063 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually 1064 * 1065 * @ib: indirect buffer to fill with commands 1066 * @pe: addr of the page entry 1067 * @value: dst addr to write into pe 1068 * @count: number of page entries to update 1069 * @incr: increase next addr by incr bytes 1070 * 1071 * Update PTEs by writing them manually using sDMA. 1072 */ 1073 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1074 uint64_t value, unsigned count, 1075 uint32_t incr) 1076 { 1077 unsigned ndw = count * 2; 1078 1079 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1080 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1081 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1082 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1083 ib->ptr[ib->length_dw++] = ndw - 1; 1084 for (; ndw > 0; ndw -= 2) { 1085 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1086 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1087 value += incr; 1088 } 1089 } 1090 1091 /** 1092 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA 1093 * 1094 * @ib: indirect buffer to fill with commands 1095 * @pe: addr of the page entry 1096 * @addr: dst addr to write into pe 1097 * @count: number of page entries to update 1098 * @incr: increase next addr by incr bytes 1099 * @flags: access flags 1100 * 1101 * Update the page tables using sDMA. 1102 */ 1103 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1104 uint64_t pe, 1105 uint64_t addr, unsigned count, 1106 uint32_t incr, uint64_t flags) 1107 { 1108 /* for physically contiguous pages (vram) */ 1109 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1110 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1111 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1112 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1113 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1114 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1115 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1116 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1117 ib->ptr[ib->length_dw++] = 0; 1118 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1119 } 1120 1121 /** 1122 * sdma_v6_0_ring_pad_ib - pad the IB 1123 * @ib: indirect buffer to fill with padding 1124 * @ring: amdgpu ring pointer 1125 * 1126 * Pad the IB with NOPs to a boundary multiple of 8. 1127 */ 1128 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1129 { 1130 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1131 u32 pad_count; 1132 int i; 1133 1134 pad_count = (-ib->length_dw) & 0x7; 1135 for (i = 0; i < pad_count; i++) 1136 if (sdma && sdma->burst_nop && (i == 0)) 1137 ib->ptr[ib->length_dw++] = 1138 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1139 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1140 else 1141 ib->ptr[ib->length_dw++] = 1142 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1143 } 1144 1145 /** 1146 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline 1147 * 1148 * @ring: amdgpu_ring pointer 1149 * 1150 * Make sure all previous operations are completed (CIK). 1151 */ 1152 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1153 { 1154 uint32_t seq = ring->fence_drv.sync_seq; 1155 uint64_t addr = ring->fence_drv.gpu_addr; 1156 1157 /* wait for idle */ 1158 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1159 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1160 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1161 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1162 amdgpu_ring_write(ring, addr & 0xfffffffc); 1163 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1164 amdgpu_ring_write(ring, seq); /* reference */ 1165 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1166 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1167 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1168 } 1169 1170 /** 1171 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA 1172 * 1173 * @ring: amdgpu_ring pointer 1174 * @vmid: vmid number to use 1175 * @pd_addr: address 1176 * 1177 * Update the page table base and flush the VM TLB 1178 * using sDMA. 1179 */ 1180 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1181 unsigned vmid, uint64_t pd_addr) 1182 { 1183 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1184 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 1185 1186 /* Update the PD address for this VMID. */ 1187 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1188 (hub->ctx_addr_distance * vmid), 1189 lower_32_bits(pd_addr)); 1190 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1191 (hub->ctx_addr_distance * vmid), 1192 upper_32_bits(pd_addr)); 1193 1194 /* Trigger invalidation. */ 1195 amdgpu_ring_write(ring, 1196 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1197 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) | 1198 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) | 1199 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f)); 1200 amdgpu_ring_write(ring, req); 1201 amdgpu_ring_write(ring, 0xFFFFFFFF); 1202 amdgpu_ring_write(ring, 1203 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) | 1204 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F)); 1205 } 1206 1207 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1208 uint32_t reg, uint32_t val) 1209 { 1210 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1211 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1212 amdgpu_ring_write(ring, reg); 1213 amdgpu_ring_write(ring, val); 1214 } 1215 1216 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1217 uint32_t val, uint32_t mask) 1218 { 1219 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1220 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1221 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1222 amdgpu_ring_write(ring, reg << 2); 1223 amdgpu_ring_write(ring, 0); 1224 amdgpu_ring_write(ring, val); /* reference */ 1225 amdgpu_ring_write(ring, mask); /* mask */ 1226 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1227 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1228 } 1229 1230 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1231 uint32_t reg0, uint32_t reg1, 1232 uint32_t ref, uint32_t mask) 1233 { 1234 amdgpu_ring_emit_wreg(ring, reg0, ref); 1235 /* wait for a cycle to reset vm_inv_eng*_ack */ 1236 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1237 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1238 } 1239 1240 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = { 1241 .ras_block = { 1242 .ras_late_init = amdgpu_ras_block_late_init, 1243 }, 1244 }; 1245 1246 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev) 1247 { 1248 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1249 case IP_VERSION(6, 0, 3): 1250 adev->sdma.ras = &sdma_v6_0_3_ras; 1251 break; 1252 default: 1253 break; 1254 } 1255 1256 } 1257 1258 static int sdma_v6_0_early_init(void *handle) 1259 { 1260 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1261 1262 sdma_v6_0_set_ring_funcs(adev); 1263 sdma_v6_0_set_buffer_funcs(adev); 1264 sdma_v6_0_set_vm_pte_funcs(adev); 1265 sdma_v6_0_set_irq_funcs(adev); 1266 sdma_v6_0_set_mqd_funcs(adev); 1267 sdma_v6_0_set_ras_funcs(adev); 1268 1269 return 0; 1270 } 1271 1272 static int sdma_v6_0_sw_init(void *handle) 1273 { 1274 struct amdgpu_ring *ring; 1275 int r, i; 1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1277 1278 /* SDMA trap event */ 1279 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1280 GFX_11_0_0__SRCID__SDMA_TRAP, 1281 &adev->sdma.trap_irq); 1282 if (r) 1283 return r; 1284 1285 r = amdgpu_sdma_init_microcode(adev, 0, true); 1286 if (r) { 1287 DRM_ERROR("Failed to load sdma firmware!\n"); 1288 return r; 1289 } 1290 1291 for (i = 0; i < adev->sdma.num_instances; i++) { 1292 ring = &adev->sdma.instance[i].ring; 1293 ring->ring_obj = NULL; 1294 ring->use_doorbell = true; 1295 ring->me = i; 1296 1297 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1298 ring->use_doorbell?"true":"false"); 1299 1300 ring->doorbell_index = 1301 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1302 1303 ring->vm_hub = AMDGPU_GFXHUB(0); 1304 sprintf(ring->name, "sdma%d", i); 1305 r = amdgpu_ring_init(adev, ring, 1024, 1306 &adev->sdma.trap_irq, 1307 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1308 AMDGPU_RING_PRIO_DEFAULT, NULL); 1309 if (r) 1310 return r; 1311 } 1312 1313 if (amdgpu_sdma_ras_sw_init(adev)) { 1314 dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); 1315 return -EINVAL; 1316 } 1317 1318 return r; 1319 } 1320 1321 static int sdma_v6_0_sw_fini(void *handle) 1322 { 1323 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1324 int i; 1325 1326 for (i = 0; i < adev->sdma.num_instances; i++) 1327 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1328 1329 amdgpu_sdma_destroy_inst_ctx(adev, true); 1330 1331 return 0; 1332 } 1333 1334 static int sdma_v6_0_hw_init(void *handle) 1335 { 1336 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1337 1338 return sdma_v6_0_start(adev); 1339 } 1340 1341 static int sdma_v6_0_hw_fini(void *handle) 1342 { 1343 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1344 1345 if (amdgpu_sriov_vf(adev)) { 1346 /* disable the scheduler for SDMA */ 1347 amdgpu_sdma_unset_buffer_funcs_helper(adev); 1348 return 0; 1349 } 1350 1351 sdma_v6_0_ctxempty_int_enable(adev, false); 1352 sdma_v6_0_enable(adev, false); 1353 1354 return 0; 1355 } 1356 1357 static int sdma_v6_0_suspend(void *handle) 1358 { 1359 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1360 1361 return sdma_v6_0_hw_fini(adev); 1362 } 1363 1364 static int sdma_v6_0_resume(void *handle) 1365 { 1366 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1367 1368 return sdma_v6_0_hw_init(adev); 1369 } 1370 1371 static bool sdma_v6_0_is_idle(void *handle) 1372 { 1373 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1374 u32 i; 1375 1376 for (i = 0; i < adev->sdma.num_instances; i++) { 1377 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1378 1379 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1380 return false; 1381 } 1382 1383 return true; 1384 } 1385 1386 static int sdma_v6_0_wait_for_idle(void *handle) 1387 { 1388 unsigned i; 1389 u32 sdma0, sdma1; 1390 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1391 1392 for (i = 0; i < adev->usec_timeout; i++) { 1393 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1394 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1395 1396 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1397 return 0; 1398 udelay(1); 1399 } 1400 return -ETIMEDOUT; 1401 } 1402 1403 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) 1404 { 1405 int i, r = 0; 1406 struct amdgpu_device *adev = ring->adev; 1407 u32 index = 0; 1408 u64 sdma_gfx_preempt; 1409 1410 amdgpu_sdma_get_index_from_ring(ring, &index); 1411 sdma_gfx_preempt = 1412 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1413 1414 /* assert preemption condition */ 1415 amdgpu_ring_set_preempt_cond_exec(ring, false); 1416 1417 /* emit the trailing fence */ 1418 ring->trail_seq += 1; 1419 amdgpu_ring_alloc(ring, 10); 1420 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1421 ring->trail_seq, 0); 1422 amdgpu_ring_commit(ring); 1423 1424 /* assert IB preemption */ 1425 WREG32(sdma_gfx_preempt, 1); 1426 1427 /* poll the trailing fence */ 1428 for (i = 0; i < adev->usec_timeout; i++) { 1429 if (ring->trail_seq == 1430 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1431 break; 1432 udelay(1); 1433 } 1434 1435 if (i >= adev->usec_timeout) { 1436 r = -EINVAL; 1437 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1438 } 1439 1440 /* deassert IB preemption */ 1441 WREG32(sdma_gfx_preempt, 0); 1442 1443 /* deassert the preemption condition */ 1444 amdgpu_ring_set_preempt_cond_exec(ring, true); 1445 return r; 1446 } 1447 1448 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, 1449 struct amdgpu_irq_src *source, 1450 unsigned type, 1451 enum amdgpu_interrupt_state state) 1452 { 1453 u32 sdma_cntl; 1454 1455 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1456 1457 if (!amdgpu_sriov_vf(adev)) { 1458 sdma_cntl = RREG32(reg_offset); 1459 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1460 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1461 WREG32(reg_offset, sdma_cntl); 1462 } 1463 1464 return 0; 1465 } 1466 1467 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev, 1468 struct amdgpu_irq_src *source, 1469 struct amdgpu_iv_entry *entry) 1470 { 1471 int instances, queue; 1472 uint32_t mes_queue_id = entry->src_data[0]; 1473 1474 DRM_DEBUG("IH: SDMA trap\n"); 1475 1476 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1477 struct amdgpu_mes_queue *queue; 1478 1479 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1480 1481 spin_lock(&adev->mes.queue_id_lock); 1482 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1483 if (queue) { 1484 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1485 amdgpu_fence_process(queue->ring); 1486 } 1487 spin_unlock(&adev->mes.queue_id_lock); 1488 return 0; 1489 } 1490 1491 queue = entry->ring_id & 0xf; 1492 instances = (entry->ring_id & 0xf0) >> 4; 1493 if (instances > 1) { 1494 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1495 return -EINVAL; 1496 } 1497 1498 switch (entry->client_id) { 1499 case SOC21_IH_CLIENTID_GFX: 1500 switch (queue) { 1501 case 0: 1502 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1503 break; 1504 default: 1505 break; 1506 } 1507 break; 1508 } 1509 return 0; 1510 } 1511 1512 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1513 struct amdgpu_irq_src *source, 1514 struct amdgpu_iv_entry *entry) 1515 { 1516 return 0; 1517 } 1518 1519 static int sdma_v6_0_set_clockgating_state(void *handle, 1520 enum amd_clockgating_state state) 1521 { 1522 return 0; 1523 } 1524 1525 static int sdma_v6_0_set_powergating_state(void *handle, 1526 enum amd_powergating_state state) 1527 { 1528 return 0; 1529 } 1530 1531 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags) 1532 { 1533 } 1534 1535 const struct amd_ip_funcs sdma_v6_0_ip_funcs = { 1536 .name = "sdma_v6_0", 1537 .early_init = sdma_v6_0_early_init, 1538 .late_init = NULL, 1539 .sw_init = sdma_v6_0_sw_init, 1540 .sw_fini = sdma_v6_0_sw_fini, 1541 .hw_init = sdma_v6_0_hw_init, 1542 .hw_fini = sdma_v6_0_hw_fini, 1543 .suspend = sdma_v6_0_suspend, 1544 .resume = sdma_v6_0_resume, 1545 .is_idle = sdma_v6_0_is_idle, 1546 .wait_for_idle = sdma_v6_0_wait_for_idle, 1547 .soft_reset = sdma_v6_0_soft_reset, 1548 .check_soft_reset = sdma_v6_0_check_soft_reset, 1549 .set_clockgating_state = sdma_v6_0_set_clockgating_state, 1550 .set_powergating_state = sdma_v6_0_set_powergating_state, 1551 .get_clockgating_state = sdma_v6_0_get_clockgating_state, 1552 }; 1553 1554 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { 1555 .type = AMDGPU_RING_TYPE_SDMA, 1556 .align_mask = 0xf, 1557 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1558 .support_64bit_ptrs = true, 1559 .secure_submission_supported = true, 1560 .get_rptr = sdma_v6_0_ring_get_rptr, 1561 .get_wptr = sdma_v6_0_ring_get_wptr, 1562 .set_wptr = sdma_v6_0_ring_set_wptr, 1563 .emit_frame_size = 1564 5 + /* sdma_v6_0_ring_init_cond_exec */ 1565 6 + /* sdma_v6_0_ring_emit_hdp_flush */ 1566 6 + /* sdma_v6_0_ring_emit_pipeline_sync */ 1567 /* sdma_v6_0_ring_emit_vm_flush */ 1568 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1569 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1570 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */ 1571 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */ 1572 .emit_ib = sdma_v6_0_ring_emit_ib, 1573 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync, 1574 .emit_fence = sdma_v6_0_ring_emit_fence, 1575 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync, 1576 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush, 1577 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush, 1578 .test_ring = sdma_v6_0_ring_test_ring, 1579 .test_ib = sdma_v6_0_ring_test_ib, 1580 .insert_nop = sdma_v6_0_ring_insert_nop, 1581 .pad_ib = sdma_v6_0_ring_pad_ib, 1582 .emit_wreg = sdma_v6_0_ring_emit_wreg, 1583 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait, 1584 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait, 1585 .init_cond_exec = sdma_v6_0_ring_init_cond_exec, 1586 .patch_cond_exec = sdma_v6_0_ring_patch_cond_exec, 1587 .preempt_ib = sdma_v6_0_ring_preempt_ib, 1588 }; 1589 1590 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1591 { 1592 int i; 1593 1594 for (i = 0; i < adev->sdma.num_instances; i++) { 1595 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs; 1596 adev->sdma.instance[i].ring.me = i; 1597 } 1598 } 1599 1600 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = { 1601 .set = sdma_v6_0_set_trap_irq_state, 1602 .process = sdma_v6_0_process_trap_irq, 1603 }; 1604 1605 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = { 1606 .process = sdma_v6_0_process_illegal_inst_irq, 1607 }; 1608 1609 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1610 { 1611 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1612 adev->sdma.num_instances; 1613 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs; 1614 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs; 1615 } 1616 1617 /** 1618 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine 1619 * 1620 * @ib: indirect buffer to fill with commands 1621 * @src_offset: src GPU address 1622 * @dst_offset: dst GPU address 1623 * @byte_count: number of bytes to xfer 1624 * @tmz: if a secure copy should be used 1625 * 1626 * Copy GPU buffers using the DMA engine. 1627 * Used by the amdgpu ttm implementation to move pages if 1628 * registered as the asic copy callback. 1629 */ 1630 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib, 1631 uint64_t src_offset, 1632 uint64_t dst_offset, 1633 uint32_t byte_count, 1634 bool tmz) 1635 { 1636 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1637 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1638 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1639 ib->ptr[ib->length_dw++] = byte_count - 1; 1640 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1641 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1642 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1643 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1644 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1645 } 1646 1647 /** 1648 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine 1649 * 1650 * @ib: indirect buffer to fill 1651 * @src_data: value to write to buffer 1652 * @dst_offset: dst GPU address 1653 * @byte_count: number of bytes to xfer 1654 * 1655 * Fill GPU buffers using the DMA engine. 1656 */ 1657 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, 1658 uint32_t src_data, 1659 uint64_t dst_offset, 1660 uint32_t byte_count) 1661 { 1662 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL); 1663 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1664 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1665 ib->ptr[ib->length_dw++] = src_data; 1666 ib->ptr[ib->length_dw++] = byte_count - 1; 1667 } 1668 1669 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { 1670 .copy_max_bytes = 0x400000, 1671 .copy_num_dw = 7, 1672 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, 1673 1674 .fill_max_bytes = 0x400000, 1675 .fill_num_dw = 5, 1676 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, 1677 }; 1678 1679 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) 1680 { 1681 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs; 1682 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1683 } 1684 1685 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1686 .copy_pte_num_dw = 7, 1687 .copy_pte = sdma_v6_0_vm_copy_pte, 1688 .write_pte = sdma_v6_0_vm_write_pte, 1689 .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1690 }; 1691 1692 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1693 { 1694 unsigned i; 1695 1696 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs; 1697 for (i = 0; i < adev->sdma.num_instances; i++) { 1698 adev->vm_manager.vm_pte_scheds[i] = 1699 &adev->sdma.instance[i].ring.sched; 1700 } 1701 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1702 } 1703 1704 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { 1705 .type = AMD_IP_BLOCK_TYPE_SDMA, 1706 .major = 6, 1707 .minor = 0, 1708 .rev = 0, 1709 .funcs = &sdma_v6_0_ip_funcs, 1710 }; 1711