1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_11_0_0_offset.h" 34 #include "gc/gc_11_0_0_sh_mask.h" 35 #include "gc/gc_11_0_0_default.h" 36 #include "hdp/hdp_6_0_0_offset.h" 37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "sdma_v6_0_0_pkt_open.h" 42 #include "nbio_v4_3.h" 43 #include "sdma_common.h" 44 #include "sdma_v6_0.h" 45 #include "v11_structs.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); 50 51 #define SDMA1_REG_OFFSET 0x600 52 #define SDMA0_HYP_DEC_REG_START 0x5880 53 #define SDMA0_HYP_DEC_REG_END 0x589a 54 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 55 56 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); 57 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); 58 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); 59 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); 60 static int sdma_v6_0_start(struct amdgpu_device *adev); 61 62 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 63 { 64 u32 base; 65 66 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 67 internal_offset <= SDMA0_HYP_DEC_REG_END) { 68 base = adev->reg_offset[GC_HWIP][0][1]; 69 if (instance != 0) 70 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 71 } else { 72 base = adev->reg_offset[GC_HWIP][0][0]; 73 if (instance == 1) 74 internal_offset += SDMA1_REG_OFFSET; 75 } 76 77 return base + internal_offset; 78 } 79 80 static int sdma_v6_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 81 { 82 int err = 0; 83 const struct sdma_firmware_header_v2_0 *hdr; 84 85 err = amdgpu_ucode_validate(sdma_inst->fw); 86 if (err) 87 return err; 88 89 hdr = (const struct sdma_firmware_header_v2_0 *)sdma_inst->fw->data; 90 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 91 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 92 93 if (sdma_inst->feature_version >= 20) 94 sdma_inst->burst_nop = true; 95 96 return 0; 97 } 98 99 static void sdma_v6_0_destroy_inst_ctx(struct amdgpu_device *adev) 100 { 101 release_firmware(adev->sdma.instance[0].fw); 102 103 memset((void*)adev->sdma.instance, 0, 104 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 105 } 106 107 /** 108 * sdma_v6_0_init_microcode - load ucode images from disk 109 * 110 * @adev: amdgpu_device pointer 111 * 112 * Use the firmware interface to load the ucode images into 113 * the driver (not loaded into hw). 114 * Returns 0 on success, error on failure. 115 */ 116 117 // emulation only, won't work on real chip 118 // sdma 6.0.0 real chip need to use PSP to load firmware 119 static int sdma_v6_0_init_microcode(struct amdgpu_device *adev) 120 { 121 char fw_name[30]; 122 char ucode_prefix[30]; 123 int err = 0, i; 124 struct amdgpu_firmware_info *info = NULL; 125 const struct sdma_firmware_header_v2_0 *sdma_hdr; 126 127 DRM_DEBUG("\n"); 128 129 amdgpu_ucode_ip_version_decode(adev, SDMA0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 130 131 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); 132 133 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 134 if (err) 135 goto out; 136 137 err = sdma_v6_0_init_inst_ctx(&adev->sdma.instance[0]); 138 if (err) 139 goto out; 140 141 for (i = 1; i < adev->sdma.num_instances; i++) { 142 memcpy((void*)&adev->sdma.instance[i], 143 (void*)&adev->sdma.instance[0], 144 sizeof(struct amdgpu_sdma_instance)); 145 } 146 147 DRM_DEBUG("psp_load == '%s'\n", 148 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 149 150 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 151 sdma_hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 152 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH0]; 153 info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH0; 154 info->fw = adev->sdma.instance[0].fw; 155 adev->firmware.fw_size += 156 ALIGN(le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes), PAGE_SIZE); 157 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA_UCODE_TH1]; 158 info->ucode_id = AMDGPU_UCODE_ID_SDMA_UCODE_TH1; 159 info->fw = adev->sdma.instance[0].fw; 160 adev->firmware.fw_size += 161 ALIGN(le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes), PAGE_SIZE); 162 } 163 164 out: 165 if (err) { 166 DRM_ERROR("sdma_v6_0: Failed to load firmware \"%s\"\n", fw_name); 167 sdma_v6_0_destroy_inst_ctx(adev); 168 } 169 return err; 170 } 171 172 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring) 173 { 174 unsigned ret; 175 176 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 177 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 178 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 179 amdgpu_ring_write(ring, 1); 180 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 181 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 182 183 return ret; 184 } 185 186 static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 187 unsigned offset) 188 { 189 unsigned cur; 190 191 BUG_ON(offset > ring->buf_mask); 192 BUG_ON(ring->ring[offset] != 0x55aa55aa); 193 194 cur = (ring->wptr - 1) & ring->buf_mask; 195 if (cur > offset) 196 ring->ring[offset] = cur - offset; 197 else 198 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 199 } 200 201 /** 202 * sdma_v6_0_ring_get_rptr - get the current read pointer 203 * 204 * @ring: amdgpu ring pointer 205 * 206 * Get the current rptr from the hardware. 207 */ 208 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 209 { 210 u64 *rptr; 211 212 /* XXX check if swapping is necessary on BE */ 213 rptr = (u64 *)ring->rptr_cpu_addr; 214 215 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 216 return ((*rptr) >> 2); 217 } 218 219 /** 220 * sdma_v6_0_ring_get_wptr - get the current write pointer 221 * 222 * @ring: amdgpu ring pointer 223 * 224 * Get the current wptr from the hardware. 225 */ 226 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 227 { 228 u64 wptr = 0; 229 230 if (ring->use_doorbell) { 231 /* XXX check if swapping is necessary on BE */ 232 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 233 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 234 } 235 236 return wptr >> 2; 237 } 238 239 /** 240 * sdma_v6_0_ring_set_wptr - commit the write pointer 241 * 242 * @ring: amdgpu ring pointer 243 * 244 * Write the wptr back to the hardware. 245 */ 246 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 247 { 248 struct amdgpu_device *adev = ring->adev; 249 uint32_t *wptr_saved; 250 uint32_t *is_queue_unmap; 251 uint64_t aggregated_db_index; 252 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size; 253 254 DRM_DEBUG("Setting write pointer\n"); 255 256 if (ring->is_mes_queue) { 257 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 258 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 259 sizeof(uint32_t)); 260 aggregated_db_index = 261 amdgpu_mes_get_aggregated_doorbell_index(adev, 262 ring->hw_prio); 263 264 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 265 ring->wptr << 2); 266 *wptr_saved = ring->wptr << 2; 267 if (*is_queue_unmap) { 268 WDOORBELL64(aggregated_db_index, ring->wptr << 2); 269 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 270 ring->doorbell_index, ring->wptr << 2); 271 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 272 } else { 273 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 274 ring->doorbell_index, ring->wptr << 2); 275 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 276 277 if (*is_queue_unmap) 278 WDOORBELL64(aggregated_db_index, 279 ring->wptr << 2); 280 } 281 } else { 282 if (ring->use_doorbell) { 283 DRM_DEBUG("Using doorbell -- " 284 "wptr_offs == 0x%08x " 285 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 286 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 287 ring->wptr_offs, 288 lower_32_bits(ring->wptr << 2), 289 upper_32_bits(ring->wptr << 2)); 290 /* XXX check if swapping is necessary on BE */ 291 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 292 ring->wptr << 2); 293 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 294 ring->doorbell_index, ring->wptr << 2); 295 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 296 } else { 297 DRM_DEBUG("Not using doorbell -- " 298 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 299 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 300 ring->me, 301 lower_32_bits(ring->wptr << 2), 302 ring->me, 303 upper_32_bits(ring->wptr << 2)); 304 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 305 ring->me, regSDMA0_QUEUE0_RB_WPTR), 306 lower_32_bits(ring->wptr << 2)); 307 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 308 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI), 309 upper_32_bits(ring->wptr << 2)); 310 } 311 } 312 } 313 314 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 315 { 316 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 317 int i; 318 319 for (i = 0; i < count; i++) 320 if (sdma && sdma->burst_nop && (i == 0)) 321 amdgpu_ring_write(ring, ring->funcs->nop | 322 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 323 else 324 amdgpu_ring_write(ring, ring->funcs->nop); 325 } 326 327 /** 328 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine 329 * 330 * @ring: amdgpu ring pointer 331 * @ib: IB object to schedule 332 * 333 * Schedule an IB in the DMA ring. 334 */ 335 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 336 struct amdgpu_job *job, 337 struct amdgpu_ib *ib, 338 uint32_t flags) 339 { 340 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 341 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 342 343 /* An IB packet must end on a 8 DW boundary--the next dword 344 * must be on a 8-dword boundary. Our IB packet below is 6 345 * dwords long, thus add x number of NOPs, such that, in 346 * modular arithmetic, 347 * wptr + 6 + x = 8k, k >= 0, which in C is, 348 * (wptr + 6 + x) % 8 = 0. 349 * The expression below, is a solution of x. 350 */ 351 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 352 353 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 354 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 355 /* base must be 32 byte aligned */ 356 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 357 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 358 amdgpu_ring_write(ring, ib->length_dw); 359 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 360 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 361 } 362 363 /** 364 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 365 * 366 * @ring: amdgpu ring pointer 367 * @job: job to retrieve vmid from 368 * @ib: IB object to schedule 369 * 370 * flush the IB by graphics cache rinse. 371 */ 372 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 373 { 374 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 375 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 376 SDMA_GCR_GLI_INV(1); 377 378 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 379 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 380 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 381 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 382 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 383 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 384 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 385 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 386 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 387 } 388 389 390 /** 391 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 392 * 393 * @ring: amdgpu ring pointer 394 * 395 * Emit an hdp flush packet on the requested DMA ring. 396 */ 397 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 398 { 399 struct amdgpu_device *adev = ring->adev; 400 u32 ref_and_mask = 0; 401 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 402 403 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 404 405 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 406 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 407 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 408 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 409 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 410 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 411 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 412 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 413 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 414 } 415 416 /** 417 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring 418 * 419 * @ring: amdgpu ring pointer 420 * @fence: amdgpu fence object 421 * 422 * Add a DMA fence packet to the ring to write 423 * the fence seq number and DMA trap packet to generate 424 * an interrupt if needed. 425 */ 426 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 427 unsigned flags) 428 { 429 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 430 /* write the fence */ 431 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 432 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 433 /* zero in first two bits */ 434 BUG_ON(addr & 0x3); 435 amdgpu_ring_write(ring, lower_32_bits(addr)); 436 amdgpu_ring_write(ring, upper_32_bits(addr)); 437 amdgpu_ring_write(ring, lower_32_bits(seq)); 438 439 /* optionally write high bits as well */ 440 if (write64bit) { 441 addr += 4; 442 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 443 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 444 /* zero in first two bits */ 445 BUG_ON(addr & 0x3); 446 amdgpu_ring_write(ring, lower_32_bits(addr)); 447 amdgpu_ring_write(ring, upper_32_bits(addr)); 448 amdgpu_ring_write(ring, upper_32_bits(seq)); 449 } 450 451 if (flags & AMDGPU_FENCE_FLAG_INT) { 452 uint32_t ctx = ring->is_mes_queue ? 453 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 454 /* generate an interrupt */ 455 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 456 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 457 } 458 } 459 460 /** 461 * sdma_v6_0_gfx_stop - stop the gfx async dma engines 462 * 463 * @adev: amdgpu_device pointer 464 * 465 * Stop the gfx async dma ring buffers. 466 */ 467 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev) 468 { 469 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 470 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 471 u32 rb_cntl, ib_cntl; 472 int i; 473 474 if ((adev->mman.buffer_funcs_ring == sdma0) || 475 (adev->mman.buffer_funcs_ring == sdma1)) 476 amdgpu_ttm_set_buffer_funcs_status(adev, false); 477 478 for (i = 0; i < adev->sdma.num_instances; i++) { 479 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 480 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 481 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 482 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 483 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 484 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 485 } 486 487 sdma0->sched.ready = false; 488 sdma1->sched.ready = false; 489 } 490 491 /** 492 * sdma_v6_0_rlc_stop - stop the compute async dma engines 493 * 494 * @adev: amdgpu_device pointer 495 * 496 * Stop the compute async dma queues. 497 */ 498 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev) 499 { 500 /* XXX todo */ 501 } 502 503 /** 504 * sdma_v6_0_ctx_switch_enable - stop the async dma engines context switch 505 * 506 * @adev: amdgpu_device pointer 507 * @enable: enable/disable the DMA MEs context switch. 508 * 509 * Halt or unhalt the async dma engines context switch. 510 */ 511 static void sdma_v6_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 512 { 513 } 514 515 /** 516 * sdma_v6_0_enable - stop the async dma engines 517 * 518 * @adev: amdgpu_device pointer 519 * @enable: enable/disable the DMA MEs. 520 * 521 * Halt or unhalt the async dma engines. 522 */ 523 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) 524 { 525 u32 f32_cntl; 526 int i; 527 528 if (!enable) { 529 sdma_v6_0_gfx_stop(adev); 530 sdma_v6_0_rlc_stop(adev); 531 } 532 533 for (i = 0; i < adev->sdma.num_instances; i++) { 534 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 535 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 536 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); 537 } 538 } 539 540 /** 541 * sdma_v6_0_gfx_resume - setup and start the async dma engines 542 * 543 * @adev: amdgpu_device pointer 544 * 545 * Set up the gfx DMA ring buffers and enable them. 546 * Returns 0 for success, error for failure. 547 */ 548 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 549 { 550 struct amdgpu_ring *ring; 551 u32 rb_cntl, ib_cntl; 552 u32 rb_bufsz; 553 u32 doorbell; 554 u32 doorbell_offset; 555 u32 temp; 556 u64 wptr_gpu_addr; 557 int i, r; 558 559 for (i = 0; i < adev->sdma.num_instances; i++) { 560 ring = &adev->sdma.instance[i].ring; 561 562 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 563 564 /* Set ring buffer size in dwords */ 565 rb_bufsz = order_base_2(ring->ring_size / 4); 566 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 567 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 568 #ifdef __BIG_ENDIAN 569 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 570 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 571 RPTR_WRITEBACK_SWAP_ENABLE, 1); 572 #endif 573 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 574 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 575 576 /* Initialize the ring buffer's read and write pointers */ 577 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 578 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 579 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 580 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 581 582 /* setup the wptr shadow polling */ 583 wptr_gpu_addr = ring->wptr_gpu_addr; 584 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 585 lower_32_bits(wptr_gpu_addr)); 586 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 587 upper_32_bits(wptr_gpu_addr)); 588 589 /* set the wb address whether it's enabled or not */ 590 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 591 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 592 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 593 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 594 595 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 596 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 597 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); 598 599 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 600 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 601 602 ring->wptr = 0; 603 604 /* before programing wptr to a less value, need set minor_ptr_update first */ 605 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 606 607 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 608 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 609 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 610 } 611 612 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 613 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 614 615 if (ring->use_doorbell) { 616 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 617 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 618 OFFSET, ring->doorbell_index); 619 } else { 620 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 621 } 622 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 623 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 624 625 if (i == 0) 626 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 627 ring->doorbell_index, 628 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 629 630 if (amdgpu_sriov_vf(adev)) 631 sdma_v6_0_ring_set_wptr(ring); 632 633 /* set minor_ptr_update to 0 after wptr programed */ 634 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 635 636 /* Set up RESP_MODE to non-copy addresses */ 637 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 638 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 639 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 640 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 641 642 /* program default cache read and write policy */ 643 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 644 /* clean read policy and write policy bits */ 645 temp &= 0xFF0FFF; 646 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 647 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 648 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 649 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 650 651 if (!amdgpu_sriov_vf(adev)) { 652 /* unhalt engine */ 653 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 654 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 655 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); 656 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); 657 } 658 659 /* enable DMA RB */ 660 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 661 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 662 663 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 664 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 665 #ifdef __BIG_ENDIAN 666 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 667 #endif 668 /* enable DMA IBs */ 669 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 670 671 ring->sched.ready = true; 672 673 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 674 sdma_v6_0_ctx_switch_enable(adev, true); 675 sdma_v6_0_enable(adev, true); 676 } 677 678 r = amdgpu_ring_test_helper(ring); 679 if (r) { 680 ring->sched.ready = false; 681 return r; 682 } 683 684 if (adev->mman.buffer_funcs_ring == ring) 685 amdgpu_ttm_set_buffer_funcs_status(adev, true); 686 } 687 688 return 0; 689 } 690 691 /** 692 * sdma_v6_0_rlc_resume - setup and start the async dma engines 693 * 694 * @adev: amdgpu_device pointer 695 * 696 * Set up the compute DMA queues and enable them. 697 * Returns 0 for success, error for failure. 698 */ 699 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev) 700 { 701 return 0; 702 } 703 704 /** 705 * sdma_v6_0_load_microcode - load the sDMA ME ucode 706 * 707 * @adev: amdgpu_device pointer 708 * 709 * Loads the sDMA0/1 ucode. 710 * Returns 0 for success, -EINVAL if the ucode is not available. 711 */ 712 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev) 713 { 714 const struct sdma_firmware_header_v2_0 *hdr; 715 const __le32 *fw_data; 716 u32 fw_size; 717 int i, j; 718 bool use_broadcast; 719 720 /* halt the MEs */ 721 sdma_v6_0_enable(adev, false); 722 723 if (!adev->sdma.instance[0].fw) 724 return -EINVAL; 725 726 /* use broadcast mode to load SDMA microcode by default */ 727 use_broadcast = true; 728 729 if (use_broadcast) { 730 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n"); 731 /* load Control Thread microcode */ 732 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 733 amdgpu_ucode_print_sdma_hdr(&hdr->header); 734 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 735 736 fw_data = (const __le32 *) 737 (adev->sdma.instance[0].fw->data + 738 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 739 740 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0); 741 742 for (j = 0; j < fw_size; j++) { 743 if (amdgpu_emu_mode == 1 && j % 500 == 0) 744 msleep(1); 745 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 746 } 747 748 /* load Context Switch microcode */ 749 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 750 751 fw_data = (const __le32 *) 752 (adev->sdma.instance[0].fw->data + 753 le32_to_cpu(hdr->ctl_ucode_offset)); 754 755 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000); 756 757 for (j = 0; j < fw_size; j++) { 758 if (amdgpu_emu_mode == 1 && j % 500 == 0) 759 msleep(1); 760 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 761 } 762 } else { 763 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n"); 764 for (i = 0; i < adev->sdma.num_instances; i++) { 765 /* load Control Thread microcode */ 766 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 767 amdgpu_ucode_print_sdma_hdr(&hdr->header); 768 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 769 770 fw_data = (const __le32 *) 771 (adev->sdma.instance[0].fw->data + 772 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 773 774 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0); 775 776 for (j = 0; j < fw_size; j++) { 777 if (amdgpu_emu_mode == 1 && j % 500 == 0) 778 msleep(1); 779 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 780 } 781 782 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 783 784 /* load Context Switch microcode */ 785 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 786 787 fw_data = (const __le32 *) 788 (adev->sdma.instance[0].fw->data + 789 le32_to_cpu(hdr->ctl_ucode_offset)); 790 791 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000); 792 793 for (j = 0; j < fw_size; j++) { 794 if (amdgpu_emu_mode == 1 && j % 500 == 0) 795 msleep(1); 796 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 797 } 798 799 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 800 } 801 } 802 803 return 0; 804 } 805 806 static int sdma_v6_0_soft_reset(void *handle) 807 { 808 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 809 u32 tmp; 810 int i; 811 812 sdma_v6_0_gfx_stop(adev); 813 814 for (i = 0; i < adev->sdma.num_instances; i++) { 815 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 816 tmp |= SDMA0_FREEZE__FREEZE_MASK; 817 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 818 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 819 tmp |= SDMA0_F32_CNTL__HALT_MASK; 820 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK; 821 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); 822 823 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 824 825 udelay(100); 826 827 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 828 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 829 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 830 831 udelay(100); 832 833 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 834 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 835 836 udelay(100); 837 } 838 839 return sdma_v6_0_start(adev); 840 } 841 842 static bool sdma_v6_0_check_soft_reset(void *handle) 843 { 844 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 845 struct amdgpu_ring *ring; 846 int i, r; 847 long tmo = msecs_to_jiffies(1000); 848 849 for (i = 0; i < adev->sdma.num_instances; i++) { 850 ring = &adev->sdma.instance[i].ring; 851 r = amdgpu_ring_test_ib(ring, tmo); 852 if (r) 853 return true; 854 } 855 856 return false; 857 } 858 859 /** 860 * sdma_v6_0_start - setup and start the async dma engines 861 * 862 * @adev: amdgpu_device pointer 863 * 864 * Set up the DMA engines and enable them. 865 * Returns 0 for success, error for failure. 866 */ 867 static int sdma_v6_0_start(struct amdgpu_device *adev) 868 { 869 int r = 0; 870 871 if (amdgpu_sriov_vf(adev)) { 872 sdma_v6_0_ctx_switch_enable(adev, false); 873 sdma_v6_0_enable(adev, false); 874 875 /* set RB registers */ 876 r = sdma_v6_0_gfx_resume(adev); 877 return r; 878 } 879 880 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 881 r = sdma_v6_0_load_microcode(adev); 882 if (r) 883 return r; 884 885 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */ 886 if (amdgpu_emu_mode == 1) 887 msleep(1000); 888 } 889 890 /* unhalt the MEs */ 891 sdma_v6_0_enable(adev, true); 892 /* enable sdma ring preemption */ 893 sdma_v6_0_ctx_switch_enable(adev, true); 894 895 /* start the gfx rings and rlc compute queues */ 896 r = sdma_v6_0_gfx_resume(adev); 897 if (r) 898 return r; 899 r = sdma_v6_0_rlc_resume(adev); 900 901 return r; 902 } 903 904 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd, 905 struct amdgpu_mqd_prop *prop) 906 { 907 struct v11_sdma_mqd *m = mqd; 908 uint64_t wb_gpu_addr; 909 910 m->sdmax_rlcx_rb_cntl = 911 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 912 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 913 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; 914 915 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 916 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 917 918 wb_gpu_addr = prop->wptr_gpu_addr; 919 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 920 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 921 922 wb_gpu_addr = prop->rptr_gpu_addr; 923 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 924 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 925 926 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0, 927 regSDMA0_QUEUE0_IB_CNTL)); 928 929 m->sdmax_rlcx_doorbell_offset = 930 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 931 932 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 933 934 m->sdmax_rlcx_skip_cntl = 0; 935 m->sdmax_rlcx_context_status = 0; 936 m->sdmax_rlcx_doorbell_log = 0; 937 938 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 939 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 940 941 return 0; 942 } 943 944 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev) 945 { 946 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd); 947 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init; 948 } 949 950 /** 951 * sdma_v6_0_ring_test_ring - simple async dma engine test 952 * 953 * @ring: amdgpu_ring structure holding ring information 954 * 955 * Test the DMA engine by writing using it to write an 956 * value to memory. 957 * Returns 0 for success, error for failure. 958 */ 959 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) 960 { 961 struct amdgpu_device *adev = ring->adev; 962 unsigned i; 963 unsigned index; 964 int r; 965 u32 tmp; 966 u64 gpu_addr; 967 volatile uint32_t *cpu_ptr = NULL; 968 969 tmp = 0xCAFEDEAD; 970 971 if (ring->is_mes_queue) { 972 uint32_t offset = 0; 973 offset = amdgpu_mes_ctx_get_offs(ring, 974 AMDGPU_MES_CTX_PADDING_OFFS); 975 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 976 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 977 *cpu_ptr = tmp; 978 } else { 979 r = amdgpu_device_wb_get(adev, &index); 980 if (r) { 981 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 982 return r; 983 } 984 985 gpu_addr = adev->wb.gpu_addr + (index * 4); 986 adev->wb.wb[index] = cpu_to_le32(tmp); 987 } 988 989 r = amdgpu_ring_alloc(ring, 5); 990 if (r) { 991 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 992 amdgpu_device_wb_free(adev, index); 993 return r; 994 } 995 996 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 997 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 998 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 999 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1000 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1001 amdgpu_ring_write(ring, 0xDEADBEEF); 1002 amdgpu_ring_commit(ring); 1003 1004 for (i = 0; i < adev->usec_timeout; i++) { 1005 if (ring->is_mes_queue) 1006 tmp = le32_to_cpu(*cpu_ptr); 1007 else 1008 tmp = le32_to_cpu(adev->wb.wb[index]); 1009 if (tmp == 0xDEADBEEF) 1010 break; 1011 if (amdgpu_emu_mode == 1) 1012 msleep(1); 1013 else 1014 udelay(1); 1015 } 1016 1017 if (i >= adev->usec_timeout) 1018 r = -ETIMEDOUT; 1019 1020 if (!ring->is_mes_queue) 1021 amdgpu_device_wb_free(adev, index); 1022 1023 return r; 1024 } 1025 1026 /** 1027 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine 1028 * 1029 * @ring: amdgpu_ring structure holding ring information 1030 * 1031 * Test a simple IB in the DMA ring. 1032 * Returns 0 on success, error on failure. 1033 */ 1034 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1035 { 1036 struct amdgpu_device *adev = ring->adev; 1037 struct amdgpu_ib ib; 1038 struct dma_fence *f = NULL; 1039 unsigned index; 1040 long r; 1041 u32 tmp = 0; 1042 u64 gpu_addr; 1043 volatile uint32_t *cpu_ptr = NULL; 1044 1045 tmp = 0xCAFEDEAD; 1046 memset(&ib, 0, sizeof(ib)); 1047 1048 if (ring->is_mes_queue) { 1049 uint32_t offset = 0; 1050 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 1051 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 1052 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 1053 1054 offset = amdgpu_mes_ctx_get_offs(ring, 1055 AMDGPU_MES_CTX_PADDING_OFFS); 1056 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 1057 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 1058 *cpu_ptr = tmp; 1059 } else { 1060 r = amdgpu_device_wb_get(adev, &index); 1061 if (r) { 1062 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1063 return r; 1064 } 1065 1066 gpu_addr = adev->wb.gpu_addr + (index * 4); 1067 adev->wb.wb[index] = cpu_to_le32(tmp); 1068 1069 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 1070 if (r) { 1071 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1072 goto err0; 1073 } 1074 } 1075 1076 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1077 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1078 ib.ptr[1] = lower_32_bits(gpu_addr); 1079 ib.ptr[2] = upper_32_bits(gpu_addr); 1080 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1081 ib.ptr[4] = 0xDEADBEEF; 1082 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1083 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1084 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1085 ib.length_dw = 8; 1086 1087 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1088 if (r) 1089 goto err1; 1090 1091 r = dma_fence_wait_timeout(f, false, timeout); 1092 if (r == 0) { 1093 DRM_ERROR("amdgpu: IB test timed out\n"); 1094 r = -ETIMEDOUT; 1095 goto err1; 1096 } else if (r < 0) { 1097 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1098 goto err1; 1099 } 1100 1101 if (ring->is_mes_queue) 1102 tmp = le32_to_cpu(*cpu_ptr); 1103 else 1104 tmp = le32_to_cpu(adev->wb.wb[index]); 1105 1106 if (tmp == 0xDEADBEEF) 1107 r = 0; 1108 else 1109 r = -EINVAL; 1110 1111 err1: 1112 amdgpu_ib_free(adev, &ib, NULL); 1113 dma_fence_put(f); 1114 err0: 1115 if (!ring->is_mes_queue) 1116 amdgpu_device_wb_free(adev, index); 1117 return r; 1118 } 1119 1120 1121 /** 1122 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART 1123 * 1124 * @ib: indirect buffer to fill with commands 1125 * @pe: addr of the page entry 1126 * @src: src addr to copy from 1127 * @count: number of page entries to update 1128 * 1129 * Update PTEs by copying them from the GART using sDMA. 1130 */ 1131 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib, 1132 uint64_t pe, uint64_t src, 1133 unsigned count) 1134 { 1135 unsigned bytes = count * 8; 1136 1137 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1138 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1139 ib->ptr[ib->length_dw++] = bytes - 1; 1140 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1141 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1142 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1143 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1144 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1145 1146 } 1147 1148 /** 1149 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually 1150 * 1151 * @ib: indirect buffer to fill with commands 1152 * @pe: addr of the page entry 1153 * @addr: dst addr to write into pe 1154 * @count: number of page entries to update 1155 * @incr: increase next addr by incr bytes 1156 * @flags: access flags 1157 * 1158 * Update PTEs by writing them manually using sDMA. 1159 */ 1160 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1161 uint64_t value, unsigned count, 1162 uint32_t incr) 1163 { 1164 unsigned ndw = count * 2; 1165 1166 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1167 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1168 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1169 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1170 ib->ptr[ib->length_dw++] = ndw - 1; 1171 for (; ndw > 0; ndw -= 2) { 1172 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1173 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1174 value += incr; 1175 } 1176 } 1177 1178 /** 1179 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA 1180 * 1181 * @ib: indirect buffer to fill with commands 1182 * @pe: addr of the page entry 1183 * @addr: dst addr to write into pe 1184 * @count: number of page entries to update 1185 * @incr: increase next addr by incr bytes 1186 * @flags: access flags 1187 * 1188 * Update the page tables using sDMA. 1189 */ 1190 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1191 uint64_t pe, 1192 uint64_t addr, unsigned count, 1193 uint32_t incr, uint64_t flags) 1194 { 1195 /* for physically contiguous pages (vram) */ 1196 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1197 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1198 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1199 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1200 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1201 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1202 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1203 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1204 ib->ptr[ib->length_dw++] = 0; 1205 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1206 } 1207 1208 /** 1209 * sdma_v6_0_ring_pad_ib - pad the IB 1210 * @ib: indirect buffer to fill with padding 1211 * 1212 * Pad the IB with NOPs to a boundary multiple of 8. 1213 */ 1214 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1215 { 1216 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1217 u32 pad_count; 1218 int i; 1219 1220 pad_count = (-ib->length_dw) & 0x7; 1221 for (i = 0; i < pad_count; i++) 1222 if (sdma && sdma->burst_nop && (i == 0)) 1223 ib->ptr[ib->length_dw++] = 1224 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1225 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1226 else 1227 ib->ptr[ib->length_dw++] = 1228 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1229 } 1230 1231 /** 1232 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline 1233 * 1234 * @ring: amdgpu_ring pointer 1235 * 1236 * Make sure all previous operations are completed (CIK). 1237 */ 1238 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1239 { 1240 uint32_t seq = ring->fence_drv.sync_seq; 1241 uint64_t addr = ring->fence_drv.gpu_addr; 1242 1243 /* wait for idle */ 1244 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1245 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1246 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1247 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1248 amdgpu_ring_write(ring, addr & 0xfffffffc); 1249 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1250 amdgpu_ring_write(ring, seq); /* reference */ 1251 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1252 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1253 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1254 } 1255 1256 /** 1257 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA 1258 * 1259 * @ring: amdgpu_ring pointer 1260 * @vm: amdgpu_vm pointer 1261 * 1262 * Update the page table base and flush the VM TLB 1263 * using sDMA. 1264 */ 1265 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1266 unsigned vmid, uint64_t pd_addr) 1267 { 1268 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1269 } 1270 1271 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1272 uint32_t reg, uint32_t val) 1273 { 1274 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1275 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1276 amdgpu_ring_write(ring, reg); 1277 amdgpu_ring_write(ring, val); 1278 } 1279 1280 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1281 uint32_t val, uint32_t mask) 1282 { 1283 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1284 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1285 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1286 amdgpu_ring_write(ring, reg << 2); 1287 amdgpu_ring_write(ring, 0); 1288 amdgpu_ring_write(ring, val); /* reference */ 1289 amdgpu_ring_write(ring, mask); /* mask */ 1290 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1291 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1292 } 1293 1294 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1295 uint32_t reg0, uint32_t reg1, 1296 uint32_t ref, uint32_t mask) 1297 { 1298 amdgpu_ring_emit_wreg(ring, reg0, ref); 1299 /* wait for a cycle to reset vm_inv_eng*_ack */ 1300 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1301 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1302 } 1303 1304 static int sdma_v6_0_early_init(void *handle) 1305 { 1306 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1307 1308 sdma_v6_0_set_ring_funcs(adev); 1309 sdma_v6_0_set_buffer_funcs(adev); 1310 sdma_v6_0_set_vm_pte_funcs(adev); 1311 sdma_v6_0_set_irq_funcs(adev); 1312 sdma_v6_0_set_mqd_funcs(adev); 1313 1314 return 0; 1315 } 1316 1317 static int sdma_v6_0_sw_init(void *handle) 1318 { 1319 struct amdgpu_ring *ring; 1320 int r, i; 1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1322 1323 /* SDMA trap event */ 1324 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1325 GFX_11_0_0__SRCID__SDMA_TRAP, 1326 &adev->sdma.trap_irq); 1327 if (r) 1328 return r; 1329 1330 r = sdma_v6_0_init_microcode(adev); 1331 if (r) { 1332 DRM_ERROR("Failed to load sdma firmware!\n"); 1333 return r; 1334 } 1335 1336 for (i = 0; i < adev->sdma.num_instances; i++) { 1337 ring = &adev->sdma.instance[i].ring; 1338 ring->ring_obj = NULL; 1339 ring->use_doorbell = true; 1340 ring->me = i; 1341 1342 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1343 ring->use_doorbell?"true":"false"); 1344 1345 ring->doorbell_index = 1346 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1347 1348 sprintf(ring->name, "sdma%d", i); 1349 r = amdgpu_ring_init(adev, ring, 1024, 1350 &adev->sdma.trap_irq, 1351 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1352 AMDGPU_RING_PRIO_DEFAULT, NULL); 1353 if (r) 1354 return r; 1355 } 1356 1357 return r; 1358 } 1359 1360 static int sdma_v6_0_sw_fini(void *handle) 1361 { 1362 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1363 int i; 1364 1365 for (i = 0; i < adev->sdma.num_instances; i++) 1366 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1367 1368 sdma_v6_0_destroy_inst_ctx(adev); 1369 1370 return 0; 1371 } 1372 1373 static int sdma_v6_0_hw_init(void *handle) 1374 { 1375 int r; 1376 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1377 1378 r = sdma_v6_0_start(adev); 1379 1380 return r; 1381 } 1382 1383 static int sdma_v6_0_hw_fini(void *handle) 1384 { 1385 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1386 1387 if (amdgpu_sriov_vf(adev)) 1388 return 0; 1389 1390 sdma_v6_0_ctx_switch_enable(adev, false); 1391 sdma_v6_0_enable(adev, false); 1392 1393 return 0; 1394 } 1395 1396 static int sdma_v6_0_suspend(void *handle) 1397 { 1398 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1399 1400 return sdma_v6_0_hw_fini(adev); 1401 } 1402 1403 static int sdma_v6_0_resume(void *handle) 1404 { 1405 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1406 1407 return sdma_v6_0_hw_init(adev); 1408 } 1409 1410 static bool sdma_v6_0_is_idle(void *handle) 1411 { 1412 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1413 u32 i; 1414 1415 for (i = 0; i < adev->sdma.num_instances; i++) { 1416 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1417 1418 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1419 return false; 1420 } 1421 1422 return true; 1423 } 1424 1425 static int sdma_v6_0_wait_for_idle(void *handle) 1426 { 1427 unsigned i; 1428 u32 sdma0, sdma1; 1429 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1430 1431 for (i = 0; i < adev->usec_timeout; i++) { 1432 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1433 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1434 1435 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1436 return 0; 1437 udelay(1); 1438 } 1439 return -ETIMEDOUT; 1440 } 1441 1442 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) 1443 { 1444 int i, r = 0; 1445 struct amdgpu_device *adev = ring->adev; 1446 u32 index = 0; 1447 u64 sdma_gfx_preempt; 1448 1449 amdgpu_sdma_get_index_from_ring(ring, &index); 1450 sdma_gfx_preempt = 1451 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1452 1453 /* assert preemption condition */ 1454 amdgpu_ring_set_preempt_cond_exec(ring, false); 1455 1456 /* emit the trailing fence */ 1457 ring->trail_seq += 1; 1458 amdgpu_ring_alloc(ring, 10); 1459 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1460 ring->trail_seq, 0); 1461 amdgpu_ring_commit(ring); 1462 1463 /* assert IB preemption */ 1464 WREG32(sdma_gfx_preempt, 1); 1465 1466 /* poll the trailing fence */ 1467 for (i = 0; i < adev->usec_timeout; i++) { 1468 if (ring->trail_seq == 1469 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1470 break; 1471 udelay(1); 1472 } 1473 1474 if (i >= adev->usec_timeout) { 1475 r = -EINVAL; 1476 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1477 } 1478 1479 /* deassert IB preemption */ 1480 WREG32(sdma_gfx_preempt, 0); 1481 1482 /* deassert the preemption condition */ 1483 amdgpu_ring_set_preempt_cond_exec(ring, true); 1484 return r; 1485 } 1486 1487 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, 1488 struct amdgpu_irq_src *source, 1489 unsigned type, 1490 enum amdgpu_interrupt_state state) 1491 { 1492 u32 sdma_cntl; 1493 1494 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1495 1496 sdma_cntl = RREG32(reg_offset); 1497 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1498 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1499 WREG32(reg_offset, sdma_cntl); 1500 1501 return 0; 1502 } 1503 1504 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev, 1505 struct amdgpu_irq_src *source, 1506 struct amdgpu_iv_entry *entry) 1507 { 1508 int instances, queue; 1509 uint32_t mes_queue_id = entry->src_data[0]; 1510 1511 DRM_DEBUG("IH: SDMA trap\n"); 1512 1513 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1514 struct amdgpu_mes_queue *queue; 1515 1516 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1517 1518 spin_lock(&adev->mes.queue_id_lock); 1519 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1520 if (queue) { 1521 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1522 amdgpu_fence_process(queue->ring); 1523 } 1524 spin_unlock(&adev->mes.queue_id_lock); 1525 return 0; 1526 } 1527 1528 queue = entry->ring_id & 0xf; 1529 instances = (entry->ring_id & 0xf0) >> 4; 1530 if (instances > 1) { 1531 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1532 return -EINVAL; 1533 } 1534 1535 switch (entry->client_id) { 1536 case SOC21_IH_CLIENTID_GFX: 1537 switch (queue) { 1538 case 0: 1539 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1540 break; 1541 default: 1542 break; 1543 } 1544 break; 1545 } 1546 return 0; 1547 } 1548 1549 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1550 struct amdgpu_irq_src *source, 1551 struct amdgpu_iv_entry *entry) 1552 { 1553 return 0; 1554 } 1555 1556 static int sdma_v6_0_set_clockgating_state(void *handle, 1557 enum amd_clockgating_state state) 1558 { 1559 return 0; 1560 } 1561 1562 static int sdma_v6_0_set_powergating_state(void *handle, 1563 enum amd_powergating_state state) 1564 { 1565 return 0; 1566 } 1567 1568 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags) 1569 { 1570 } 1571 1572 const struct amd_ip_funcs sdma_v6_0_ip_funcs = { 1573 .name = "sdma_v6_0", 1574 .early_init = sdma_v6_0_early_init, 1575 .late_init = NULL, 1576 .sw_init = sdma_v6_0_sw_init, 1577 .sw_fini = sdma_v6_0_sw_fini, 1578 .hw_init = sdma_v6_0_hw_init, 1579 .hw_fini = sdma_v6_0_hw_fini, 1580 .suspend = sdma_v6_0_suspend, 1581 .resume = sdma_v6_0_resume, 1582 .is_idle = sdma_v6_0_is_idle, 1583 .wait_for_idle = sdma_v6_0_wait_for_idle, 1584 .soft_reset = sdma_v6_0_soft_reset, 1585 .check_soft_reset = sdma_v6_0_check_soft_reset, 1586 .set_clockgating_state = sdma_v6_0_set_clockgating_state, 1587 .set_powergating_state = sdma_v6_0_set_powergating_state, 1588 .get_clockgating_state = sdma_v6_0_get_clockgating_state, 1589 }; 1590 1591 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { 1592 .type = AMDGPU_RING_TYPE_SDMA, 1593 .align_mask = 0xf, 1594 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1595 .support_64bit_ptrs = true, 1596 .vmhub = AMDGPU_GFXHUB_0, 1597 .get_rptr = sdma_v6_0_ring_get_rptr, 1598 .get_wptr = sdma_v6_0_ring_get_wptr, 1599 .set_wptr = sdma_v6_0_ring_set_wptr, 1600 .emit_frame_size = 1601 5 + /* sdma_v6_0_ring_init_cond_exec */ 1602 6 + /* sdma_v6_0_ring_emit_hdp_flush */ 1603 6 + /* sdma_v6_0_ring_emit_pipeline_sync */ 1604 /* sdma_v6_0_ring_emit_vm_flush */ 1605 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1606 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1607 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */ 1608 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */ 1609 .emit_ib = sdma_v6_0_ring_emit_ib, 1610 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync, 1611 .emit_fence = sdma_v6_0_ring_emit_fence, 1612 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync, 1613 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush, 1614 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush, 1615 .test_ring = sdma_v6_0_ring_test_ring, 1616 .test_ib = sdma_v6_0_ring_test_ib, 1617 .insert_nop = sdma_v6_0_ring_insert_nop, 1618 .pad_ib = sdma_v6_0_ring_pad_ib, 1619 .emit_wreg = sdma_v6_0_ring_emit_wreg, 1620 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait, 1621 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait, 1622 .init_cond_exec = sdma_v6_0_ring_init_cond_exec, 1623 .patch_cond_exec = sdma_v6_0_ring_patch_cond_exec, 1624 .preempt_ib = sdma_v6_0_ring_preempt_ib, 1625 }; 1626 1627 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1628 { 1629 int i; 1630 1631 for (i = 0; i < adev->sdma.num_instances; i++) { 1632 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs; 1633 adev->sdma.instance[i].ring.me = i; 1634 } 1635 } 1636 1637 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = { 1638 .set = sdma_v6_0_set_trap_irq_state, 1639 .process = sdma_v6_0_process_trap_irq, 1640 }; 1641 1642 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = { 1643 .process = sdma_v6_0_process_illegal_inst_irq, 1644 }; 1645 1646 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1647 { 1648 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1649 adev->sdma.num_instances; 1650 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs; 1651 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs; 1652 } 1653 1654 /** 1655 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine 1656 * 1657 * @ring: amdgpu_ring structure holding ring information 1658 * @src_offset: src GPU address 1659 * @dst_offset: dst GPU address 1660 * @byte_count: number of bytes to xfer 1661 * 1662 * Copy GPU buffers using the DMA engine. 1663 * Used by the amdgpu ttm implementation to move pages if 1664 * registered as the asic copy callback. 1665 */ 1666 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib, 1667 uint64_t src_offset, 1668 uint64_t dst_offset, 1669 uint32_t byte_count, 1670 bool tmz) 1671 { 1672 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1673 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1674 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1675 ib->ptr[ib->length_dw++] = byte_count - 1; 1676 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1677 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1678 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1679 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1680 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1681 } 1682 1683 /** 1684 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine 1685 * 1686 * @ring: amdgpu_ring structure holding ring information 1687 * @src_data: value to write to buffer 1688 * @dst_offset: dst GPU address 1689 * @byte_count: number of bytes to xfer 1690 * 1691 * Fill GPU buffers using the DMA engine. 1692 */ 1693 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, 1694 uint32_t src_data, 1695 uint64_t dst_offset, 1696 uint32_t byte_count) 1697 { 1698 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL); 1699 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1700 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1701 ib->ptr[ib->length_dw++] = src_data; 1702 ib->ptr[ib->length_dw++] = byte_count - 1; 1703 } 1704 1705 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { 1706 .copy_max_bytes = 0x400000, 1707 .copy_num_dw = 7, 1708 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, 1709 1710 .fill_max_bytes = 0x400000, 1711 .fill_num_dw = 5, 1712 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, 1713 }; 1714 1715 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) 1716 { 1717 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs; 1718 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1719 } 1720 1721 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1722 .copy_pte_num_dw = 7, 1723 .copy_pte = sdma_v6_0_vm_copy_pte, 1724 .write_pte = sdma_v6_0_vm_write_pte, 1725 .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1726 }; 1727 1728 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1729 { 1730 unsigned i; 1731 1732 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs; 1733 for (i = 0; i < adev->sdma.num_instances; i++) { 1734 adev->vm_manager.vm_pte_scheds[i] = 1735 &adev->sdma.instance[i].ring.sched; 1736 } 1737 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1738 } 1739 1740 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { 1741 .type = AMD_IP_BLOCK_TYPE_SDMA, 1742 .major = 6, 1743 .minor = 0, 1744 .rev = 0, 1745 .funcs = &sdma_v6_0_ip_funcs, 1746 }; 1747