1 /*
2  * Copyright 2020 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32 
33 #include "gc/gc_11_0_0_offset.h"
34 #include "gc/gc_11_0_0_sh_mask.h"
35 #include "gc/gc_11_0_0_default.h"
36 #include "hdp/hdp_6_0_0_offset.h"
37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
38 
39 #include "soc15_common.h"
40 #include "soc15.h"
41 #include "sdma_v6_0_0_pkt_open.h"
42 #include "nbio_v4_3.h"
43 #include "sdma_common.h"
44 #include "sdma_v6_0.h"
45 #include "v11_structs.h"
46 
47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
50 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
51 
52 #define SDMA1_REG_OFFSET 0x600
53 #define SDMA0_HYP_DEC_REG_START 0x5880
54 #define SDMA0_HYP_DEC_REG_END 0x589a
55 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
56 
57 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev);
58 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev);
59 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev);
60 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev);
61 static int sdma_v6_0_start(struct amdgpu_device *adev);
62 
63 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
64 {
65 	u32 base;
66 
67 	if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
68 	    internal_offset <= SDMA0_HYP_DEC_REG_END) {
69 		base = adev->reg_offset[GC_HWIP][0][1];
70 		if (instance != 0)
71 			internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
72 	} else {
73 		base = adev->reg_offset[GC_HWIP][0][0];
74 		if (instance == 1)
75 			internal_offset += SDMA1_REG_OFFSET;
76 	}
77 
78 	return base + internal_offset;
79 }
80 
81 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring)
82 {
83 	unsigned ret;
84 
85 	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
86 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
87 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
88 	amdgpu_ring_write(ring, 1);
89 	ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
90 	amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
91 
92 	return ret;
93 }
94 
95 static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
96 					   unsigned offset)
97 {
98 	unsigned cur;
99 
100 	BUG_ON(offset > ring->buf_mask);
101 	BUG_ON(ring->ring[offset] != 0x55aa55aa);
102 
103 	cur = (ring->wptr - 1) & ring->buf_mask;
104 	if (cur > offset)
105 		ring->ring[offset] = cur - offset;
106 	else
107 		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
108 }
109 
110 /**
111  * sdma_v6_0_ring_get_rptr - get the current read pointer
112  *
113  * @ring: amdgpu ring pointer
114  *
115  * Get the current rptr from the hardware.
116  */
117 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
118 {
119 	u64 *rptr;
120 
121 	/* XXX check if swapping is necessary on BE */
122 	rptr = (u64 *)ring->rptr_cpu_addr;
123 
124 	DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
125 	return ((*rptr) >> 2);
126 }
127 
128 /**
129  * sdma_v6_0_ring_get_wptr - get the current write pointer
130  *
131  * @ring: amdgpu ring pointer
132  *
133  * Get the current wptr from the hardware.
134  */
135 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
136 {
137 	u64 wptr = 0;
138 
139 	if (ring->use_doorbell) {
140 		/* XXX check if swapping is necessary on BE */
141 		wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
142 		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
143 	}
144 
145 	return wptr >> 2;
146 }
147 
148 /**
149  * sdma_v6_0_ring_set_wptr - commit the write pointer
150  *
151  * @ring: amdgpu ring pointer
152  *
153  * Write the wptr back to the hardware.
154  */
155 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
156 {
157 	struct amdgpu_device *adev = ring->adev;
158 	uint32_t *wptr_saved;
159 	uint32_t *is_queue_unmap;
160 	uint64_t aggregated_db_index;
161 	uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
162 
163 	DRM_DEBUG("Setting write pointer\n");
164 
165 	if (ring->is_mes_queue) {
166 		wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
167 		is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
168 					      sizeof(uint32_t));
169 		aggregated_db_index =
170 			amdgpu_mes_get_aggregated_doorbell_index(adev,
171 							 ring->hw_prio);
172 
173 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
174 			     ring->wptr << 2);
175 		*wptr_saved = ring->wptr << 2;
176 		if (*is_queue_unmap) {
177 			WDOORBELL64(aggregated_db_index, ring->wptr << 2);
178 			DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
179 					ring->doorbell_index, ring->wptr << 2);
180 			WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
181 		} else {
182 			DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
183 					ring->doorbell_index, ring->wptr << 2);
184 			WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
185 
186 			if (*is_queue_unmap)
187 				WDOORBELL64(aggregated_db_index,
188 					    ring->wptr << 2);
189 		}
190 	} else {
191 		if (ring->use_doorbell) {
192 			DRM_DEBUG("Using doorbell -- "
193 				  "wptr_offs == 0x%08x "
194 				  "lower_32_bits(ring->wptr) << 2 == 0x%08x "
195 				  "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
196 				  ring->wptr_offs,
197 				  lower_32_bits(ring->wptr << 2),
198 				  upper_32_bits(ring->wptr << 2));
199 			/* XXX check if swapping is necessary on BE */
200 			atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
201 				     ring->wptr << 2);
202 			DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
203 				  ring->doorbell_index, ring->wptr << 2);
204 			WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
205 		} else {
206 			DRM_DEBUG("Not using doorbell -- "
207 				  "regSDMA%i_GFX_RB_WPTR == 0x%08x "
208 				  "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
209 				  ring->me,
210 				  lower_32_bits(ring->wptr << 2),
211 				  ring->me,
212 				  upper_32_bits(ring->wptr << 2));
213 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
214 				        ring->me, regSDMA0_QUEUE0_RB_WPTR),
215 					lower_32_bits(ring->wptr << 2));
216 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
217 				        ring->me, regSDMA0_QUEUE0_RB_WPTR_HI),
218 					upper_32_bits(ring->wptr << 2));
219 		}
220 	}
221 }
222 
223 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
224 {
225 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
226 	int i;
227 
228 	for (i = 0; i < count; i++)
229 		if (sdma && sdma->burst_nop && (i == 0))
230 			amdgpu_ring_write(ring, ring->funcs->nop |
231 				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
232 		else
233 			amdgpu_ring_write(ring, ring->funcs->nop);
234 }
235 
236 /**
237  * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine
238  *
239  * @ring: amdgpu ring pointer
240  * @ib: IB object to schedule
241  *
242  * Schedule an IB in the DMA ring.
243  */
244 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
245 				   struct amdgpu_job *job,
246 				   struct amdgpu_ib *ib,
247 				   uint32_t flags)
248 {
249 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
250 	uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
251 
252 	/* An IB packet must end on a 8 DW boundary--the next dword
253 	 * must be on a 8-dword boundary. Our IB packet below is 6
254 	 * dwords long, thus add x number of NOPs, such that, in
255 	 * modular arithmetic,
256 	 * wptr + 6 + x = 8k, k >= 0, which in C is,
257 	 * (wptr + 6 + x) % 8 = 0.
258 	 * The expression below, is a solution of x.
259 	 */
260 	sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
261 
262 	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
263 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
264 	/* base must be 32 byte aligned */
265 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
266 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
267 	amdgpu_ring_write(ring, ib->length_dw);
268 	amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
269 	amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
270 }
271 
272 /**
273  * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
274  *
275  * @ring: amdgpu ring pointer
276  *
277  * flush the IB by graphics cache rinse.
278  */
279 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
280 {
281         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
282                             SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
283                             SDMA_GCR_GLI_INV(1);
284 
285         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
286         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));
287         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
288         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
289                           SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
290         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
291                           SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
292         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
293                           SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
294 }
295 
296 
297 /**
298  * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
299  *
300  * @ring: amdgpu ring pointer
301  *
302  * Emit an hdp flush packet on the requested DMA ring.
303  */
304 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
305 {
306 	struct amdgpu_device *adev = ring->adev;
307 	u32 ref_and_mask = 0;
308 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
309 
310 	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
311 
312 	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
313 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
314 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
315 	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
316 	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
317 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
318 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
319 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
320 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
321 }
322 
323 /**
324  * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring
325  *
326  * @ring: amdgpu ring pointer
327  * @addr: address
328  * @seq: fence seq number
329  * @flags: fence flags
330  *
331  * Add a DMA fence packet to the ring to write
332  * the fence seq number and DMA trap packet to generate
333  * an interrupt if needed.
334  */
335 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
336 				      unsigned flags)
337 {
338 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
339 	/* write the fence */
340 	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
341 			  SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
342 	/* zero in first two bits */
343 	BUG_ON(addr & 0x3);
344 	amdgpu_ring_write(ring, lower_32_bits(addr));
345 	amdgpu_ring_write(ring, upper_32_bits(addr));
346 	amdgpu_ring_write(ring, lower_32_bits(seq));
347 
348 	/* optionally write high bits as well */
349 	if (write64bit) {
350 		addr += 4;
351 		amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
352 				  SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
353 		/* zero in first two bits */
354 		BUG_ON(addr & 0x3);
355 		amdgpu_ring_write(ring, lower_32_bits(addr));
356 		amdgpu_ring_write(ring, upper_32_bits(addr));
357 		amdgpu_ring_write(ring, upper_32_bits(seq));
358 	}
359 
360 	if (flags & AMDGPU_FENCE_FLAG_INT) {
361 		uint32_t ctx = ring->is_mes_queue ?
362 			(ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
363 		/* generate an interrupt */
364 		amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));
365 		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
366 	}
367 }
368 
369 /**
370  * sdma_v6_0_gfx_stop - stop the gfx async dma engines
371  *
372  * @adev: amdgpu_device pointer
373  *
374  * Stop the gfx async dma ring buffers.
375  */
376 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev)
377 {
378 	u32 rb_cntl, ib_cntl;
379 	int i;
380 
381 	amdgpu_sdma_unset_buffer_funcs_helper(adev);
382 
383 	for (i = 0; i < adev->sdma.num_instances; i++) {
384 		rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
385 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);
386 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
387 		ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
388 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);
389 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
390 	}
391 }
392 
393 /**
394  * sdma_v6_0_rlc_stop - stop the compute async dma engines
395  *
396  * @adev: amdgpu_device pointer
397  *
398  * Stop the compute async dma queues.
399  */
400 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev)
401 {
402 	/* XXX todo */
403 }
404 
405 /**
406  * sdma_v6_0_ctx_switch_enable - stop the async dma engines context switch
407  *
408  * @adev: amdgpu_device pointer
409  * @enable: enable/disable the DMA MEs context switch.
410  *
411  * Halt or unhalt the async dma engines context switch.
412  */
413 static void sdma_v6_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
414 {
415 }
416 
417 /**
418  * sdma_v6_0_enable - stop the async dma engines
419  *
420  * @adev: amdgpu_device pointer
421  * @enable: enable/disable the DMA MEs.
422  *
423  * Halt or unhalt the async dma engines.
424  */
425 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
426 {
427 	u32 f32_cntl;
428 	int i;
429 
430 	if (!enable) {
431 		sdma_v6_0_gfx_stop(adev);
432 		sdma_v6_0_rlc_stop(adev);
433 	}
434 
435 	if (amdgpu_sriov_vf(adev))
436 		return;
437 
438 	for (i = 0; i < adev->sdma.num_instances; i++) {
439 		f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
440 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
441 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);
442 	}
443 }
444 
445 /**
446  * sdma_v6_0_gfx_resume - setup and start the async dma engines
447  *
448  * @adev: amdgpu_device pointer
449  *
450  * Set up the gfx DMA ring buffers and enable them.
451  * Returns 0 for success, error for failure.
452  */
453 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
454 {
455 	struct amdgpu_ring *ring;
456 	u32 rb_cntl, ib_cntl;
457 	u32 rb_bufsz;
458 	u32 doorbell;
459 	u32 doorbell_offset;
460 	u32 temp;
461 	u64 wptr_gpu_addr;
462 	int i, r;
463 
464 	for (i = 0; i < adev->sdma.num_instances; i++) {
465 		ring = &adev->sdma.instance[i].ring;
466 
467 		if (!amdgpu_sriov_vf(adev))
468 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
469 
470 		/* Set ring buffer size in dwords */
471 		rb_bufsz = order_base_2(ring->ring_size / 4);
472 		rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
473 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
474 #ifdef __BIG_ENDIAN
475 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
476 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
477 					RPTR_WRITEBACK_SWAP_ENABLE, 1);
478 #endif
479 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
480 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
481 
482 		/* Initialize the ring buffer's read and write pointers */
483 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
484 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
485 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
486 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
487 
488 		/* setup the wptr shadow polling */
489 		wptr_gpu_addr = ring->wptr_gpu_addr;
490 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
491 		       lower_32_bits(wptr_gpu_addr));
492 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
493 		       upper_32_bits(wptr_gpu_addr));
494 
495 		/* set the wb address whether it's enabled or not */
496 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
497 		       upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
498 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
499 		       lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
500 
501 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
502 		if (amdgpu_sriov_vf(adev))
503 			rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1);
504 		else
505 			rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
506 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
507 
508 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
509 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
510 
511 		ring->wptr = 0;
512 
513 		/* before programing wptr to a less value, need set minor_ptr_update first */
514 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
515 
516 		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
517 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
518 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
519 		}
520 
521 		doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
522 		doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
523 
524 		if (ring->use_doorbell) {
525 			doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
526 			doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
527 					OFFSET, ring->doorbell_index);
528 		} else {
529 			doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
530 		}
531 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
532 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
533 
534 		if (i == 0)
535 			adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
536 						      ring->doorbell_index,
537 						      adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
538 
539 		if (amdgpu_sriov_vf(adev))
540 			sdma_v6_0_ring_set_wptr(ring);
541 
542 		/* set minor_ptr_update to 0 after wptr programed */
543 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
544 
545 		/* Set up RESP_MODE to non-copy addresses */
546 		temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
547 		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
548 		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
549 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);
550 
551 		/* program default cache read and write policy */
552 		temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
553 		/* clean read policy and write policy bits */
554 		temp &= 0xFF0FFF;
555 		temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
556 			 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
557 			 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
558 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);
559 
560 		if (!amdgpu_sriov_vf(adev)) {
561 			/* unhalt engine */
562 			temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
563 			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
564 			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);
565 			WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);
566 		}
567 
568 		/* enable DMA RB */
569 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
570 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
571 
572 		ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
573 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
574 #ifdef __BIG_ENDIAN
575 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
576 #endif
577 		/* enable DMA IBs */
578 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
579 
580 		ring->sched.ready = true;
581 
582 		if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
583 			sdma_v6_0_ctx_switch_enable(adev, true);
584 			sdma_v6_0_enable(adev, true);
585 		}
586 
587 		r = amdgpu_ring_test_helper(ring);
588 		if (r) {
589 			ring->sched.ready = false;
590 			return r;
591 		}
592 
593 		if (adev->mman.buffer_funcs_ring == ring)
594 			amdgpu_ttm_set_buffer_funcs_status(adev, true);
595 	}
596 
597 	return 0;
598 }
599 
600 /**
601  * sdma_v6_0_rlc_resume - setup and start the async dma engines
602  *
603  * @adev: amdgpu_device pointer
604  *
605  * Set up the compute DMA queues and enable them.
606  * Returns 0 for success, error for failure.
607  */
608 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev)
609 {
610 	return 0;
611 }
612 
613 /**
614  * sdma_v6_0_load_microcode - load the sDMA ME ucode
615  *
616  * @adev: amdgpu_device pointer
617  *
618  * Loads the sDMA0/1 ucode.
619  * Returns 0 for success, -EINVAL if the ucode is not available.
620  */
621 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)
622 {
623 	const struct sdma_firmware_header_v2_0 *hdr;
624 	const __le32 *fw_data;
625 	u32 fw_size;
626 	int i, j;
627 	bool use_broadcast;
628 
629 	/* halt the MEs */
630 	sdma_v6_0_enable(adev, false);
631 
632 	if (!adev->sdma.instance[0].fw)
633 		return -EINVAL;
634 
635 	/* use broadcast mode to load SDMA microcode by default */
636 	use_broadcast = true;
637 
638 	if (use_broadcast) {
639 		dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n");
640 		/* load Control Thread microcode */
641 		hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
642 		amdgpu_ucode_print_sdma_hdr(&hdr->header);
643 		fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
644 
645 		fw_data = (const __le32 *)
646 			(adev->sdma.instance[0].fw->data +
647 				le32_to_cpu(hdr->header.ucode_array_offset_bytes));
648 
649 		WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);
650 
651 		for (j = 0; j < fw_size; j++) {
652 			if (amdgpu_emu_mode == 1 && j % 500 == 0)
653 				msleep(1);
654 			WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
655 		}
656 
657 		/* load Context Switch microcode */
658 		fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
659 
660 		fw_data = (const __le32 *)
661 			(adev->sdma.instance[0].fw->data +
662 				le32_to_cpu(hdr->ctl_ucode_offset));
663 
664 		WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);
665 
666 		for (j = 0; j < fw_size; j++) {
667 			if (amdgpu_emu_mode == 1 && j % 500 == 0)
668 				msleep(1);
669 			WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
670 		}
671 	} else {
672 		dev_info(adev->dev, "Use legacy method to load SDMA firmware\n");
673 		for (i = 0; i < adev->sdma.num_instances; i++) {
674 			/* load Control Thread microcode */
675 			hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
676 			amdgpu_ucode_print_sdma_hdr(&hdr->header);
677 			fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
678 
679 			fw_data = (const __le32 *)
680 				(adev->sdma.instance[0].fw->data +
681 					le32_to_cpu(hdr->header.ucode_array_offset_bytes));
682 
683 			WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);
684 
685 			for (j = 0; j < fw_size; j++) {
686 				if (amdgpu_emu_mode == 1 && j % 500 == 0)
687 					msleep(1);
688 				WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
689 			}
690 
691 			WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
692 
693 			/* load Context Switch microcode */
694 			fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
695 
696 			fw_data = (const __le32 *)
697 				(adev->sdma.instance[0].fw->data +
698 					le32_to_cpu(hdr->ctl_ucode_offset));
699 
700 			WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);
701 
702 			for (j = 0; j < fw_size; j++) {
703 				if (amdgpu_emu_mode == 1 && j % 500 == 0)
704 					msleep(1);
705 				WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
706 			}
707 
708 			WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
709 		}
710 	}
711 
712 	return 0;
713 }
714 
715 static int sdma_v6_0_soft_reset(void *handle)
716 {
717 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
718 	u32 tmp;
719 	int i;
720 
721 	sdma_v6_0_gfx_stop(adev);
722 
723 	for (i = 0; i < adev->sdma.num_instances; i++) {
724 		tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
725 		tmp |= SDMA0_FREEZE__FREEZE_MASK;
726 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
727 		tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
728 		tmp |= SDMA0_F32_CNTL__HALT_MASK;
729 		tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK;
730 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);
731 
732 		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);
733 
734 		udelay(100);
735 
736 		tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
737 		WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
738 		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
739 
740 		udelay(100);
741 
742 		WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);
743 		tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
744 
745 		udelay(100);
746 	}
747 
748 	return sdma_v6_0_start(adev);
749 }
750 
751 static bool sdma_v6_0_check_soft_reset(void *handle)
752 {
753 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
754 	struct amdgpu_ring *ring;
755 	int i, r;
756 	long tmo = msecs_to_jiffies(1000);
757 
758 	for (i = 0; i < adev->sdma.num_instances; i++) {
759 		ring = &adev->sdma.instance[i].ring;
760 		r = amdgpu_ring_test_ib(ring, tmo);
761 		if (r)
762 			return true;
763 	}
764 
765 	return false;
766 }
767 
768 /**
769  * sdma_v6_0_start - setup and start the async dma engines
770  *
771  * @adev: amdgpu_device pointer
772  *
773  * Set up the DMA engines and enable them.
774  * Returns 0 for success, error for failure.
775  */
776 static int sdma_v6_0_start(struct amdgpu_device *adev)
777 {
778 	int r = 0;
779 
780 	if (amdgpu_sriov_vf(adev)) {
781 		sdma_v6_0_ctx_switch_enable(adev, false);
782 		sdma_v6_0_enable(adev, false);
783 
784 		/* set RB registers */
785 		r = sdma_v6_0_gfx_resume(adev);
786 		return r;
787 	}
788 
789 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
790 		r = sdma_v6_0_load_microcode(adev);
791 		if (r)
792 			return r;
793 
794 		/* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */
795 		if (amdgpu_emu_mode == 1)
796 			msleep(1000);
797 	}
798 
799 	/* unhalt the MEs */
800 	sdma_v6_0_enable(adev, true);
801 	/* enable sdma ring preemption */
802 	sdma_v6_0_ctx_switch_enable(adev, true);
803 
804 	/* start the gfx rings and rlc compute queues */
805 	r = sdma_v6_0_gfx_resume(adev);
806 	if (r)
807 		return r;
808 	r = sdma_v6_0_rlc_resume(adev);
809 
810 	return r;
811 }
812 
813 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd,
814 			      struct amdgpu_mqd_prop *prop)
815 {
816 	struct v11_sdma_mqd *m = mqd;
817 	uint64_t wb_gpu_addr;
818 
819 	m->sdmax_rlcx_rb_cntl =
820 		order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
821 		1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
822 		4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
823 		1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
824 
825 	m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
826 	m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
827 
828 	wb_gpu_addr = prop->wptr_gpu_addr;
829 	m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
830 	m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
831 
832 	wb_gpu_addr = prop->rptr_gpu_addr;
833 	m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
834 	m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
835 
836 	m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,
837 							regSDMA0_QUEUE0_IB_CNTL));
838 
839 	m->sdmax_rlcx_doorbell_offset =
840 		prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
841 
842 	m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
843 
844 	m->sdmax_rlcx_skip_cntl = 0;
845 	m->sdmax_rlcx_context_status = 0;
846 	m->sdmax_rlcx_doorbell_log = 0;
847 
848 	m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
849 	m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
850 
851 	return 0;
852 }
853 
854 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev)
855 {
856 	adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd);
857 	adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init;
858 }
859 
860 /**
861  * sdma_v6_0_ring_test_ring - simple async dma engine test
862  *
863  * @ring: amdgpu_ring structure holding ring information
864  *
865  * Test the DMA engine by writing using it to write an
866  * value to memory.
867  * Returns 0 for success, error for failure.
868  */
869 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)
870 {
871 	struct amdgpu_device *adev = ring->adev;
872 	unsigned i;
873 	unsigned index;
874 	int r;
875 	u32 tmp;
876 	u64 gpu_addr;
877 	volatile uint32_t *cpu_ptr = NULL;
878 
879 	tmp = 0xCAFEDEAD;
880 
881 	if (ring->is_mes_queue) {
882 		uint32_t offset = 0;
883 		offset = amdgpu_mes_ctx_get_offs(ring,
884 					 AMDGPU_MES_CTX_PADDING_OFFS);
885 		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
886 		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
887 		*cpu_ptr = tmp;
888 	} else {
889 		r = amdgpu_device_wb_get(adev, &index);
890 		if (r) {
891 			dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
892 			return r;
893 		}
894 
895 		gpu_addr = adev->wb.gpu_addr + (index * 4);
896 		adev->wb.wb[index] = cpu_to_le32(tmp);
897 	}
898 
899 	r = amdgpu_ring_alloc(ring, 5);
900 	if (r) {
901 		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
902 		amdgpu_device_wb_free(adev, index);
903 		return r;
904 	}
905 
906 	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
907 			  SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
908 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
909 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
910 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
911 	amdgpu_ring_write(ring, 0xDEADBEEF);
912 	amdgpu_ring_commit(ring);
913 
914 	for (i = 0; i < adev->usec_timeout; i++) {
915 		if (ring->is_mes_queue)
916 			tmp = le32_to_cpu(*cpu_ptr);
917 		else
918 			tmp = le32_to_cpu(adev->wb.wb[index]);
919 		if (tmp == 0xDEADBEEF)
920 			break;
921 		if (amdgpu_emu_mode == 1)
922 			msleep(1);
923 		else
924 			udelay(1);
925 	}
926 
927 	if (i >= adev->usec_timeout)
928 		r = -ETIMEDOUT;
929 
930 	if (!ring->is_mes_queue)
931 		amdgpu_device_wb_free(adev, index);
932 
933 	return r;
934 }
935 
936 /**
937  * sdma_v6_0_ring_test_ib - test an IB on the DMA engine
938  *
939  * @ring: amdgpu_ring structure holding ring information
940  *
941  * Test a simple IB in the DMA ring.
942  * Returns 0 on success, error on failure.
943  */
944 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
945 {
946 	struct amdgpu_device *adev = ring->adev;
947 	struct amdgpu_ib ib;
948 	struct dma_fence *f = NULL;
949 	unsigned index;
950 	long r;
951 	u32 tmp = 0;
952 	u64 gpu_addr;
953 	volatile uint32_t *cpu_ptr = NULL;
954 
955 	tmp = 0xCAFEDEAD;
956 	memset(&ib, 0, sizeof(ib));
957 
958 	if (ring->is_mes_queue) {
959 		uint32_t offset = 0;
960 		offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
961 		ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
962 		ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
963 
964 		offset = amdgpu_mes_ctx_get_offs(ring,
965 					 AMDGPU_MES_CTX_PADDING_OFFS);
966 		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
967 		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
968 		*cpu_ptr = tmp;
969 	} else {
970 		r = amdgpu_device_wb_get(adev, &index);
971 		if (r) {
972 			dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
973 			return r;
974 		}
975 
976 		gpu_addr = adev->wb.gpu_addr + (index * 4);
977 		adev->wb.wb[index] = cpu_to_le32(tmp);
978 
979 		r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
980 		if (r) {
981 			DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
982 			goto err0;
983 		}
984 	}
985 
986 	ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
987 		SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
988 	ib.ptr[1] = lower_32_bits(gpu_addr);
989 	ib.ptr[2] = upper_32_bits(gpu_addr);
990 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
991 	ib.ptr[4] = 0xDEADBEEF;
992 	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
993 	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
994 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
995 	ib.length_dw = 8;
996 
997 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
998 	if (r)
999 		goto err1;
1000 
1001 	r = dma_fence_wait_timeout(f, false, timeout);
1002 	if (r == 0) {
1003 		DRM_ERROR("amdgpu: IB test timed out\n");
1004 		r = -ETIMEDOUT;
1005 		goto err1;
1006 	} else if (r < 0) {
1007 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1008 		goto err1;
1009 	}
1010 
1011 	if (ring->is_mes_queue)
1012 		tmp = le32_to_cpu(*cpu_ptr);
1013 	else
1014 		tmp = le32_to_cpu(adev->wb.wb[index]);
1015 
1016 	if (tmp == 0xDEADBEEF)
1017 		r = 0;
1018 	else
1019 		r = -EINVAL;
1020 
1021 err1:
1022 	amdgpu_ib_free(adev, &ib, NULL);
1023 	dma_fence_put(f);
1024 err0:
1025 	if (!ring->is_mes_queue)
1026 		amdgpu_device_wb_free(adev, index);
1027 	return r;
1028 }
1029 
1030 
1031 /**
1032  * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART
1033  *
1034  * @ib: indirect buffer to fill with commands
1035  * @pe: addr of the page entry
1036  * @src: src addr to copy from
1037  * @count: number of page entries to update
1038  *
1039  * Update PTEs by copying them from the GART using sDMA.
1040  */
1041 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib,
1042 				  uint64_t pe, uint64_t src,
1043 				  unsigned count)
1044 {
1045 	unsigned bytes = count * 8;
1046 
1047 	ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1048 		SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1049 	ib->ptr[ib->length_dw++] = bytes - 1;
1050 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1051 	ib->ptr[ib->length_dw++] = lower_32_bits(src);
1052 	ib->ptr[ib->length_dw++] = upper_32_bits(src);
1053 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1054 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1055 
1056 }
1057 
1058 /**
1059  * sdma_v6_0_vm_write_pte - update PTEs by writing them manually
1060  *
1061  * @ib: indirect buffer to fill with commands
1062  * @pe: addr of the page entry
1063  * @value: dst addr to write into pe
1064  * @count: number of page entries to update
1065  * @incr: increase next addr by incr bytes
1066  *
1067  * Update PTEs by writing them manually using sDMA.
1068  */
1069 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1070 				   uint64_t value, unsigned count,
1071 				   uint32_t incr)
1072 {
1073 	unsigned ndw = count * 2;
1074 
1075 	ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1076 		SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1077 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1078 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1079 	ib->ptr[ib->length_dw++] = ndw - 1;
1080 	for (; ndw > 0; ndw -= 2) {
1081 		ib->ptr[ib->length_dw++] = lower_32_bits(value);
1082 		ib->ptr[ib->length_dw++] = upper_32_bits(value);
1083 		value += incr;
1084 	}
1085 }
1086 
1087 /**
1088  * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA
1089  *
1090  * @ib: indirect buffer to fill with commands
1091  * @pe: addr of the page entry
1092  * @addr: dst addr to write into pe
1093  * @count: number of page entries to update
1094  * @incr: increase next addr by incr bytes
1095  * @flags: access flags
1096  *
1097  * Update the page tables using sDMA.
1098  */
1099 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1100 				     uint64_t pe,
1101 				     uint64_t addr, unsigned count,
1102 				     uint32_t incr, uint64_t flags)
1103 {
1104 	/* for physically contiguous pages (vram) */
1105 	ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
1106 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1107 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1108 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1109 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1110 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1111 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1112 	ib->ptr[ib->length_dw++] = incr; /* increment size */
1113 	ib->ptr[ib->length_dw++] = 0;
1114 	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1115 }
1116 
1117 /**
1118  * sdma_v6_0_ring_pad_ib - pad the IB
1119  * @ib: indirect buffer to fill with padding
1120  *
1121  * Pad the IB with NOPs to a boundary multiple of 8.
1122  */
1123 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1124 {
1125 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1126 	u32 pad_count;
1127 	int i;
1128 
1129 	pad_count = (-ib->length_dw) & 0x7;
1130 	for (i = 0; i < pad_count; i++)
1131 		if (sdma && sdma->burst_nop && (i == 0))
1132 			ib->ptr[ib->length_dw++] =
1133 				SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |
1134 				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1135 		else
1136 			ib->ptr[ib->length_dw++] =
1137 				SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);
1138 }
1139 
1140 /**
1141  * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline
1142  *
1143  * @ring: amdgpu_ring pointer
1144  *
1145  * Make sure all previous operations are completed (CIK).
1146  */
1147 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1148 {
1149 	uint32_t seq = ring->fence_drv.sync_seq;
1150 	uint64_t addr = ring->fence_drv.gpu_addr;
1151 
1152 	/* wait for idle */
1153 	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1154 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1155 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1156 			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1157 	amdgpu_ring_write(ring, addr & 0xfffffffc);
1158 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1159 	amdgpu_ring_write(ring, seq); /* reference */
1160 	amdgpu_ring_write(ring, 0xffffffff); /* mask */
1161 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1162 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1163 }
1164 
1165 /**
1166  * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA
1167  *
1168  * @ring: amdgpu_ring pointer
1169  *
1170  * Update the page table base and flush the VM TLB
1171  * using sDMA.
1172  */
1173 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1174 					 unsigned vmid, uint64_t pd_addr)
1175 {
1176 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1177 }
1178 
1179 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1180 				     uint32_t reg, uint32_t val)
1181 {
1182 	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1183 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1184 	amdgpu_ring_write(ring, reg);
1185 	amdgpu_ring_write(ring, val);
1186 }
1187 
1188 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1189 					 uint32_t val, uint32_t mask)
1190 {
1191 	amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1192 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1193 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1194 	amdgpu_ring_write(ring, reg << 2);
1195 	amdgpu_ring_write(ring, 0);
1196 	amdgpu_ring_write(ring, val); /* reference */
1197 	amdgpu_ring_write(ring, mask); /* mask */
1198 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1199 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1200 }
1201 
1202 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1203 						   uint32_t reg0, uint32_t reg1,
1204 						   uint32_t ref, uint32_t mask)
1205 {
1206 	amdgpu_ring_emit_wreg(ring, reg0, ref);
1207 	/* wait for a cycle to reset vm_inv_eng*_ack */
1208 	amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1209 	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1210 }
1211 
1212 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = {
1213 	.ras_block = {
1214 		.ras_late_init = amdgpu_ras_block_late_init,
1215 	},
1216 };
1217 
1218 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev)
1219 {
1220 	switch (adev->ip_versions[SDMA0_HWIP][0]) {
1221 	case IP_VERSION(6, 0, 3):
1222 		adev->sdma.ras = &sdma_v6_0_3_ras;
1223 		break;
1224 	default:
1225 		break;
1226 	}
1227 
1228 }
1229 
1230 static int sdma_v6_0_early_init(void *handle)
1231 {
1232 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1233 
1234 	sdma_v6_0_set_ring_funcs(adev);
1235 	sdma_v6_0_set_buffer_funcs(adev);
1236 	sdma_v6_0_set_vm_pte_funcs(adev);
1237 	sdma_v6_0_set_irq_funcs(adev);
1238 	sdma_v6_0_set_mqd_funcs(adev);
1239 	sdma_v6_0_set_ras_funcs(adev);
1240 
1241 	return 0;
1242 }
1243 
1244 static int sdma_v6_0_sw_init(void *handle)
1245 {
1246 	struct amdgpu_ring *ring;
1247 	int r, i;
1248 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1249 
1250 	/* SDMA trap event */
1251 	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1252 			      GFX_11_0_0__SRCID__SDMA_TRAP,
1253 			      &adev->sdma.trap_irq);
1254 	if (r)
1255 		return r;
1256 
1257 	r = amdgpu_sdma_init_microcode(adev, 0, true);
1258 	if (r) {
1259 		DRM_ERROR("Failed to load sdma firmware!\n");
1260 		return r;
1261 	}
1262 
1263 	for (i = 0; i < adev->sdma.num_instances; i++) {
1264 		ring = &adev->sdma.instance[i].ring;
1265 		ring->ring_obj = NULL;
1266 		ring->use_doorbell = true;
1267 		ring->me = i;
1268 
1269 		DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1270 				ring->use_doorbell?"true":"false");
1271 
1272 		ring->doorbell_index =
1273 			(adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
1274 
1275 		sprintf(ring->name, "sdma%d", i);
1276 		r = amdgpu_ring_init(adev, ring, 1024,
1277 				     &adev->sdma.trap_irq,
1278 				     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1279 				     AMDGPU_RING_PRIO_DEFAULT, NULL);
1280 		if (r)
1281 			return r;
1282 	}
1283 
1284 	if (amdgpu_sdma_ras_sw_init(adev)) {
1285 		dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
1286 		return -EINVAL;
1287 	}
1288 
1289 	return r;
1290 }
1291 
1292 static int sdma_v6_0_sw_fini(void *handle)
1293 {
1294 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1295 	int i;
1296 
1297 	for (i = 0; i < adev->sdma.num_instances; i++)
1298 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1299 
1300 	amdgpu_sdma_destroy_inst_ctx(adev, true);
1301 
1302 	return 0;
1303 }
1304 
1305 static int sdma_v6_0_hw_init(void *handle)
1306 {
1307 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1308 
1309 	return sdma_v6_0_start(adev);
1310 }
1311 
1312 static int sdma_v6_0_hw_fini(void *handle)
1313 {
1314 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1315 
1316 	if (amdgpu_sriov_vf(adev)) {
1317 		/* disable the scheduler for SDMA */
1318 		amdgpu_sdma_unset_buffer_funcs_helper(adev);
1319 		return 0;
1320 	}
1321 
1322 	sdma_v6_0_ctx_switch_enable(adev, false);
1323 	sdma_v6_0_enable(adev, false);
1324 
1325 	return 0;
1326 }
1327 
1328 static int sdma_v6_0_suspend(void *handle)
1329 {
1330 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1331 
1332 	return sdma_v6_0_hw_fini(adev);
1333 }
1334 
1335 static int sdma_v6_0_resume(void *handle)
1336 {
1337 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1338 
1339 	return sdma_v6_0_hw_init(adev);
1340 }
1341 
1342 static bool sdma_v6_0_is_idle(void *handle)
1343 {
1344 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1345 	u32 i;
1346 
1347 	for (i = 0; i < adev->sdma.num_instances; i++) {
1348 		u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
1349 
1350 		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1351 			return false;
1352 	}
1353 
1354 	return true;
1355 }
1356 
1357 static int sdma_v6_0_wait_for_idle(void *handle)
1358 {
1359 	unsigned i;
1360 	u32 sdma0, sdma1;
1361 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1362 
1363 	for (i = 0; i < adev->usec_timeout; i++) {
1364 		sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
1365 		sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
1366 
1367 		if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1368 			return 0;
1369 		udelay(1);
1370 	}
1371 	return -ETIMEDOUT;
1372 }
1373 
1374 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring)
1375 {
1376 	int i, r = 0;
1377 	struct amdgpu_device *adev = ring->adev;
1378 	u32 index = 0;
1379 	u64 sdma_gfx_preempt;
1380 
1381 	amdgpu_sdma_get_index_from_ring(ring, &index);
1382 	sdma_gfx_preempt =
1383 		sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);
1384 
1385 	/* assert preemption condition */
1386 	amdgpu_ring_set_preempt_cond_exec(ring, false);
1387 
1388 	/* emit the trailing fence */
1389 	ring->trail_seq += 1;
1390 	amdgpu_ring_alloc(ring, 10);
1391 	sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1392 				  ring->trail_seq, 0);
1393 	amdgpu_ring_commit(ring);
1394 
1395 	/* assert IB preemption */
1396 	WREG32(sdma_gfx_preempt, 1);
1397 
1398 	/* poll the trailing fence */
1399 	for (i = 0; i < adev->usec_timeout; i++) {
1400 		if (ring->trail_seq ==
1401 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1402 			break;
1403 		udelay(1);
1404 	}
1405 
1406 	if (i >= adev->usec_timeout) {
1407 		r = -EINVAL;
1408 		DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1409 	}
1410 
1411 	/* deassert IB preemption */
1412 	WREG32(sdma_gfx_preempt, 0);
1413 
1414 	/* deassert the preemption condition */
1415 	amdgpu_ring_set_preempt_cond_exec(ring, true);
1416 	return r;
1417 }
1418 
1419 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
1420 					struct amdgpu_irq_src *source,
1421 					unsigned type,
1422 					enum amdgpu_interrupt_state state)
1423 {
1424 	u32 sdma_cntl;
1425 
1426 	u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
1427 
1428 	if (!amdgpu_sriov_vf(adev)) {
1429 		sdma_cntl = RREG32(reg_offset);
1430 		sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1431 				state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1432 		WREG32(reg_offset, sdma_cntl);
1433 	}
1434 
1435 	return 0;
1436 }
1437 
1438 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev,
1439 				      struct amdgpu_irq_src *source,
1440 				      struct amdgpu_iv_entry *entry)
1441 {
1442 	int instances, queue;
1443 	uint32_t mes_queue_id = entry->src_data[0];
1444 
1445 	DRM_DEBUG("IH: SDMA trap\n");
1446 
1447 	if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1448 		struct amdgpu_mes_queue *queue;
1449 
1450 		mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1451 
1452 		spin_lock(&adev->mes.queue_id_lock);
1453 		queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1454 		if (queue) {
1455 			DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1456 			amdgpu_fence_process(queue->ring);
1457 		}
1458 		spin_unlock(&adev->mes.queue_id_lock);
1459 		return 0;
1460 	}
1461 
1462 	queue = entry->ring_id & 0xf;
1463 	instances = (entry->ring_id & 0xf0) >> 4;
1464 	if (instances > 1) {
1465 		DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1466 		return -EINVAL;
1467 	}
1468 
1469 	switch (entry->client_id) {
1470 	case SOC21_IH_CLIENTID_GFX:
1471 		switch (queue) {
1472 		case 0:
1473 			amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1474 			break;
1475 		default:
1476 			break;
1477 		}
1478 		break;
1479 	}
1480 	return 0;
1481 }
1482 
1483 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1484 					      struct amdgpu_irq_src *source,
1485 					      struct amdgpu_iv_entry *entry)
1486 {
1487 	return 0;
1488 }
1489 
1490 static int sdma_v6_0_set_clockgating_state(void *handle,
1491 					   enum amd_clockgating_state state)
1492 {
1493 	return 0;
1494 }
1495 
1496 static int sdma_v6_0_set_powergating_state(void *handle,
1497 					  enum amd_powergating_state state)
1498 {
1499 	return 0;
1500 }
1501 
1502 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags)
1503 {
1504 }
1505 
1506 const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
1507 	.name = "sdma_v6_0",
1508 	.early_init = sdma_v6_0_early_init,
1509 	.late_init = NULL,
1510 	.sw_init = sdma_v6_0_sw_init,
1511 	.sw_fini = sdma_v6_0_sw_fini,
1512 	.hw_init = sdma_v6_0_hw_init,
1513 	.hw_fini = sdma_v6_0_hw_fini,
1514 	.suspend = sdma_v6_0_suspend,
1515 	.resume = sdma_v6_0_resume,
1516 	.is_idle = sdma_v6_0_is_idle,
1517 	.wait_for_idle = sdma_v6_0_wait_for_idle,
1518 	.soft_reset = sdma_v6_0_soft_reset,
1519 	.check_soft_reset = sdma_v6_0_check_soft_reset,
1520 	.set_clockgating_state = sdma_v6_0_set_clockgating_state,
1521 	.set_powergating_state = sdma_v6_0_set_powergating_state,
1522 	.get_clockgating_state = sdma_v6_0_get_clockgating_state,
1523 };
1524 
1525 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
1526 	.type = AMDGPU_RING_TYPE_SDMA,
1527 	.align_mask = 0xf,
1528 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1529 	.support_64bit_ptrs = true,
1530 	.secure_submission_supported = true,
1531 	.vmhub = AMDGPU_GFXHUB_0,
1532 	.get_rptr = sdma_v6_0_ring_get_rptr,
1533 	.get_wptr = sdma_v6_0_ring_get_wptr,
1534 	.set_wptr = sdma_v6_0_ring_set_wptr,
1535 	.emit_frame_size =
1536 		5 + /* sdma_v6_0_ring_init_cond_exec */
1537 		6 + /* sdma_v6_0_ring_emit_hdp_flush */
1538 		6 + /* sdma_v6_0_ring_emit_pipeline_sync */
1539 		/* sdma_v6_0_ring_emit_vm_flush */
1540 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1541 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1542 		10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */
1543 	.emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */
1544 	.emit_ib = sdma_v6_0_ring_emit_ib,
1545 	.emit_mem_sync = sdma_v6_0_ring_emit_mem_sync,
1546 	.emit_fence = sdma_v6_0_ring_emit_fence,
1547 	.emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync,
1548 	.emit_vm_flush = sdma_v6_0_ring_emit_vm_flush,
1549 	.emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush,
1550 	.test_ring = sdma_v6_0_ring_test_ring,
1551 	.test_ib = sdma_v6_0_ring_test_ib,
1552 	.insert_nop = sdma_v6_0_ring_insert_nop,
1553 	.pad_ib = sdma_v6_0_ring_pad_ib,
1554 	.emit_wreg = sdma_v6_0_ring_emit_wreg,
1555 	.emit_reg_wait = sdma_v6_0_ring_emit_reg_wait,
1556 	.emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
1557 	.init_cond_exec = sdma_v6_0_ring_init_cond_exec,
1558 	.patch_cond_exec = sdma_v6_0_ring_patch_cond_exec,
1559 	.preempt_ib = sdma_v6_0_ring_preempt_ib,
1560 };
1561 
1562 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1563 {
1564 	int i;
1565 
1566 	for (i = 0; i < adev->sdma.num_instances; i++) {
1567 		adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;
1568 		adev->sdma.instance[i].ring.me = i;
1569 	}
1570 }
1571 
1572 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = {
1573 	.set = sdma_v6_0_set_trap_irq_state,
1574 	.process = sdma_v6_0_process_trap_irq,
1575 };
1576 
1577 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = {
1578 	.process = sdma_v6_0_process_illegal_inst_irq,
1579 };
1580 
1581 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1582 {
1583 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1584 					adev->sdma.num_instances;
1585 	adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;
1586 	adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;
1587 }
1588 
1589 /**
1590  * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine
1591  *
1592  * @ib: indirect buffer to fill with commands
1593  * @src_offset: src GPU address
1594  * @dst_offset: dst GPU address
1595  * @byte_count: number of bytes to xfer
1596  * @tmz: if a secure copy should be used
1597  *
1598  * Copy GPU buffers using the DMA engine.
1599  * Used by the amdgpu ttm implementation to move pages if
1600  * registered as the asic copy callback.
1601  */
1602 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib,
1603 				       uint64_t src_offset,
1604 				       uint64_t dst_offset,
1605 				       uint32_t byte_count,
1606 				       bool tmz)
1607 {
1608 	ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1609 		SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1610 		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1611 	ib->ptr[ib->length_dw++] = byte_count - 1;
1612 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1613 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1614 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1615 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1616 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1617 }
1618 
1619 /**
1620  * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine
1621  *
1622  * @ib: indirect buffer to fill
1623  * @src_data: value to write to buffer
1624  * @dst_offset: dst GPU address
1625  * @byte_count: number of bytes to xfer
1626  *
1627  * Fill GPU buffers using the DMA engine.
1628  */
1629 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,
1630 				       uint32_t src_data,
1631 				       uint64_t dst_offset,
1632 				       uint32_t byte_count)
1633 {
1634 	ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL);
1635 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1636 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1637 	ib->ptr[ib->length_dw++] = src_data;
1638 	ib->ptr[ib->length_dw++] = byte_count - 1;
1639 }
1640 
1641 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
1642 	.copy_max_bytes = 0x400000,
1643 	.copy_num_dw = 7,
1644 	.emit_copy_buffer = sdma_v6_0_emit_copy_buffer,
1645 
1646 	.fill_max_bytes = 0x400000,
1647 	.fill_num_dw = 5,
1648 	.emit_fill_buffer = sdma_v6_0_emit_fill_buffer,
1649 };
1650 
1651 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev)
1652 {
1653 	adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs;
1654 	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1655 }
1656 
1657 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
1658 	.copy_pte_num_dw = 7,
1659 	.copy_pte = sdma_v6_0_vm_copy_pte,
1660 	.write_pte = sdma_v6_0_vm_write_pte,
1661 	.set_pte_pde = sdma_v6_0_vm_set_pte_pde,
1662 };
1663 
1664 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1665 {
1666 	unsigned i;
1667 
1668 	adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs;
1669 	for (i = 0; i < adev->sdma.num_instances; i++) {
1670 		adev->vm_manager.vm_pte_scheds[i] =
1671 			&adev->sdma.instance[i].ring.sched;
1672 	}
1673 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1674 }
1675 
1676 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
1677 	.type = AMD_IP_BLOCK_TYPE_SDMA,
1678 	.major = 6,
1679 	.minor = 0,
1680 	.rev = 0,
1681 	.funcs = &sdma_v6_0_ip_funcs,
1682 };
1683