1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_11_0_0_offset.h" 34 #include "gc/gc_11_0_0_sh_mask.h" 35 #include "gc/gc_11_0_0_default.h" 36 #include "hdp/hdp_6_0_0_offset.h" 37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "sdma_v6_0_0_pkt_open.h" 42 #include "nbio_v4_3.h" 43 #include "sdma_common.h" 44 #include "sdma_v6_0.h" 45 #include "v11_structs.h" 46 47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin"); 48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin"); 49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin"); 50 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin"); 51 52 #define SDMA1_REG_OFFSET 0x600 53 #define SDMA0_HYP_DEC_REG_START 0x5880 54 #define SDMA0_HYP_DEC_REG_END 0x589a 55 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 56 57 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); 58 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); 59 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); 60 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); 61 static int sdma_v6_0_start(struct amdgpu_device *adev); 62 63 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 64 { 65 u32 base; 66 67 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 68 internal_offset <= SDMA0_HYP_DEC_REG_END) { 69 base = adev->reg_offset[GC_HWIP][0][1]; 70 if (instance != 0) 71 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 72 } else { 73 base = adev->reg_offset[GC_HWIP][0][0]; 74 if (instance == 1) 75 internal_offset += SDMA1_REG_OFFSET; 76 } 77 78 return base + internal_offset; 79 } 80 81 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring) 82 { 83 unsigned ret; 84 85 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); 86 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 87 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 88 amdgpu_ring_write(ring, 1); 89 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 90 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 91 92 return ret; 93 } 94 95 static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 96 unsigned offset) 97 { 98 unsigned cur; 99 100 BUG_ON(offset > ring->buf_mask); 101 BUG_ON(ring->ring[offset] != 0x55aa55aa); 102 103 cur = (ring->wptr - 1) & ring->buf_mask; 104 if (cur > offset) 105 ring->ring[offset] = cur - offset; 106 else 107 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 108 } 109 110 /** 111 * sdma_v6_0_ring_get_rptr - get the current read pointer 112 * 113 * @ring: amdgpu ring pointer 114 * 115 * Get the current rptr from the hardware. 116 */ 117 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 118 { 119 u64 *rptr; 120 121 /* XXX check if swapping is necessary on BE */ 122 rptr = (u64 *)ring->rptr_cpu_addr; 123 124 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 125 return ((*rptr) >> 2); 126 } 127 128 /** 129 * sdma_v6_0_ring_get_wptr - get the current write pointer 130 * 131 * @ring: amdgpu ring pointer 132 * 133 * Get the current wptr from the hardware. 134 */ 135 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 136 { 137 u64 wptr = 0; 138 139 if (ring->use_doorbell) { 140 /* XXX check if swapping is necessary on BE */ 141 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 142 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 143 } 144 145 return wptr >> 2; 146 } 147 148 /** 149 * sdma_v6_0_ring_set_wptr - commit the write pointer 150 * 151 * @ring: amdgpu ring pointer 152 * 153 * Write the wptr back to the hardware. 154 */ 155 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 156 { 157 struct amdgpu_device *adev = ring->adev; 158 uint32_t *wptr_saved; 159 uint32_t *is_queue_unmap; 160 uint64_t aggregated_db_index; 161 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size; 162 163 DRM_DEBUG("Setting write pointer\n"); 164 165 if (ring->is_mes_queue) { 166 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 167 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 168 sizeof(uint32_t)); 169 aggregated_db_index = 170 amdgpu_mes_get_aggregated_doorbell_index(adev, 171 ring->hw_prio); 172 173 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 174 ring->wptr << 2); 175 *wptr_saved = ring->wptr << 2; 176 if (*is_queue_unmap) { 177 WDOORBELL64(aggregated_db_index, ring->wptr << 2); 178 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 179 ring->doorbell_index, ring->wptr << 2); 180 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 181 } else { 182 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 183 ring->doorbell_index, ring->wptr << 2); 184 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 185 186 if (*is_queue_unmap) 187 WDOORBELL64(aggregated_db_index, 188 ring->wptr << 2); 189 } 190 } else { 191 if (ring->use_doorbell) { 192 DRM_DEBUG("Using doorbell -- " 193 "wptr_offs == 0x%08x " 194 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 195 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 196 ring->wptr_offs, 197 lower_32_bits(ring->wptr << 2), 198 upper_32_bits(ring->wptr << 2)); 199 /* XXX check if swapping is necessary on BE */ 200 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 201 ring->wptr << 2); 202 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 203 ring->doorbell_index, ring->wptr << 2); 204 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 205 } else { 206 DRM_DEBUG("Not using doorbell -- " 207 "regSDMA%i_GFX_RB_WPTR == 0x%08x " 208 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 209 ring->me, 210 lower_32_bits(ring->wptr << 2), 211 ring->me, 212 upper_32_bits(ring->wptr << 2)); 213 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 214 ring->me, regSDMA0_QUEUE0_RB_WPTR), 215 lower_32_bits(ring->wptr << 2)); 216 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 217 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI), 218 upper_32_bits(ring->wptr << 2)); 219 } 220 } 221 } 222 223 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 224 { 225 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 226 int i; 227 228 for (i = 0; i < count; i++) 229 if (sdma && sdma->burst_nop && (i == 0)) 230 amdgpu_ring_write(ring, ring->funcs->nop | 231 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 232 else 233 amdgpu_ring_write(ring, ring->funcs->nop); 234 } 235 236 /** 237 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine 238 * 239 * @ring: amdgpu ring pointer 240 * @ib: IB object to schedule 241 * 242 * Schedule an IB in the DMA ring. 243 */ 244 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 245 struct amdgpu_job *job, 246 struct amdgpu_ib *ib, 247 uint32_t flags) 248 { 249 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 250 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 251 252 /* An IB packet must end on a 8 DW boundary--the next dword 253 * must be on a 8-dword boundary. Our IB packet below is 6 254 * dwords long, thus add x number of NOPs, such that, in 255 * modular arithmetic, 256 * wptr + 6 + x = 8k, k >= 0, which in C is, 257 * (wptr + 6 + x) % 8 = 0. 258 * The expression below, is a solution of x. 259 */ 260 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 261 262 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | 263 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 264 /* base must be 32 byte aligned */ 265 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 266 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 267 amdgpu_ring_write(ring, ib->length_dw); 268 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 269 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 270 } 271 272 /** 273 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 274 * 275 * @ring: amdgpu ring pointer 276 * 277 * flush the IB by graphics cache rinse. 278 */ 279 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 280 { 281 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 282 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 283 SDMA_GCR_GLI_INV(1); 284 285 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 286 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); 287 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 288 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 289 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 290 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 291 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 292 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 293 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 294 } 295 296 297 /** 298 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 299 * 300 * @ring: amdgpu ring pointer 301 * 302 * Emit an hdp flush packet on the requested DMA ring. 303 */ 304 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 305 { 306 struct amdgpu_device *adev = ring->adev; 307 u32 ref_and_mask = 0; 308 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 309 310 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 311 312 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 313 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 314 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 315 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 316 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 317 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 318 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 319 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 320 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 321 } 322 323 /** 324 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring 325 * 326 * @ring: amdgpu ring pointer 327 * @addr: address 328 * @seq: fence seq number 329 * @flags: fence flags 330 * 331 * Add a DMA fence packet to the ring to write 332 * the fence seq number and DMA trap packet to generate 333 * an interrupt if needed. 334 */ 335 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 336 unsigned flags) 337 { 338 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 339 /* write the fence */ 340 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 341 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 342 /* zero in first two bits */ 343 BUG_ON(addr & 0x3); 344 amdgpu_ring_write(ring, lower_32_bits(addr)); 345 amdgpu_ring_write(ring, upper_32_bits(addr)); 346 amdgpu_ring_write(ring, lower_32_bits(seq)); 347 348 /* optionally write high bits as well */ 349 if (write64bit) { 350 addr += 4; 351 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | 352 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 353 /* zero in first two bits */ 354 BUG_ON(addr & 0x3); 355 amdgpu_ring_write(ring, lower_32_bits(addr)); 356 amdgpu_ring_write(ring, upper_32_bits(addr)); 357 amdgpu_ring_write(ring, upper_32_bits(seq)); 358 } 359 360 if (flags & AMDGPU_FENCE_FLAG_INT) { 361 uint32_t ctx = ring->is_mes_queue ? 362 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 363 /* generate an interrupt */ 364 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); 365 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 366 } 367 } 368 369 /** 370 * sdma_v6_0_gfx_stop - stop the gfx async dma engines 371 * 372 * @adev: amdgpu_device pointer 373 * 374 * Stop the gfx async dma ring buffers. 375 */ 376 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev) 377 { 378 u32 rb_cntl, ib_cntl; 379 int i; 380 381 amdgpu_sdma_unset_buffer_funcs_helper(adev); 382 383 for (i = 0; i < adev->sdma.num_instances; i++) { 384 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 385 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); 386 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 387 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 388 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0); 389 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 390 } 391 } 392 393 /** 394 * sdma_v6_0_rlc_stop - stop the compute async dma engines 395 * 396 * @adev: amdgpu_device pointer 397 * 398 * Stop the compute async dma queues. 399 */ 400 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev) 401 { 402 /* XXX todo */ 403 } 404 405 /** 406 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts 407 * 408 * @adev: amdgpu_device pointer 409 * @enable: enable/disable context switching due to queue empty conditions 410 * 411 * Enable or disable the async dma engines queue empty context switch. 412 */ 413 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable) 414 { 415 u32 f32_cntl; 416 int i; 417 418 if (!amdgpu_sriov_vf(adev)) { 419 for (i = 0; i < adev->sdma.num_instances; i++) { 420 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL)); 421 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 422 CTXEMPTY_INT_ENABLE, enable ? 1 : 0); 423 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl); 424 } 425 } 426 } 427 428 /** 429 * sdma_v6_0_enable - stop the async dma engines 430 * 431 * @adev: amdgpu_device pointer 432 * @enable: enable/disable the DMA MEs. 433 * 434 * Halt or unhalt the async dma engines. 435 */ 436 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) 437 { 438 u32 f32_cntl; 439 int i; 440 441 if (!enable) { 442 sdma_v6_0_gfx_stop(adev); 443 sdma_v6_0_rlc_stop(adev); 444 } 445 446 if (amdgpu_sriov_vf(adev)) 447 return; 448 449 for (i = 0; i < adev->sdma.num_instances; i++) { 450 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 451 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 452 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); 453 } 454 } 455 456 /** 457 * sdma_v6_0_gfx_resume - setup and start the async dma engines 458 * 459 * @adev: amdgpu_device pointer 460 * 461 * Set up the gfx DMA ring buffers and enable them. 462 * Returns 0 for success, error for failure. 463 */ 464 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) 465 { 466 struct amdgpu_ring *ring; 467 u32 rb_cntl, ib_cntl; 468 u32 rb_bufsz; 469 u32 doorbell; 470 u32 doorbell_offset; 471 u32 temp; 472 u64 wptr_gpu_addr; 473 int i, r; 474 475 for (i = 0; i < adev->sdma.num_instances; i++) { 476 ring = &adev->sdma.instance[i].ring; 477 478 if (!amdgpu_sriov_vf(adev)) 479 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 480 481 /* Set ring buffer size in dwords */ 482 rb_bufsz = order_base_2(ring->ring_size / 4); 483 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 484 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); 485 #ifdef __BIG_ENDIAN 486 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); 487 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, 488 RPTR_WRITEBACK_SWAP_ENABLE, 1); 489 #endif 490 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); 491 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 492 493 /* Initialize the ring buffer's read and write pointers */ 494 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); 495 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); 496 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); 497 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); 498 499 /* setup the wptr shadow polling */ 500 wptr_gpu_addr = ring->wptr_gpu_addr; 501 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), 502 lower_32_bits(wptr_gpu_addr)); 503 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), 504 upper_32_bits(wptr_gpu_addr)); 505 506 /* set the wb address whether it's enabled or not */ 507 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), 508 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 509 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), 510 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 511 512 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 513 if (amdgpu_sriov_vf(adev)) 514 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1); 515 else 516 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); 517 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); 518 519 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); 520 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); 521 522 ring->wptr = 0; 523 524 /* before programing wptr to a less value, need set minor_ptr_update first */ 525 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); 526 527 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 528 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); 529 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 530 } 531 532 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); 533 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); 534 535 if (ring->use_doorbell) { 536 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 537 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, 538 OFFSET, ring->doorbell_index); 539 } else { 540 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); 541 } 542 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); 543 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); 544 545 if (i == 0) 546 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 547 ring->doorbell_index, 548 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); 549 550 if (amdgpu_sriov_vf(adev)) 551 sdma_v6_0_ring_set_wptr(ring); 552 553 /* set minor_ptr_update to 0 after wptr programed */ 554 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); 555 556 /* Set up RESP_MODE to non-copy addresses */ 557 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); 558 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 559 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 560 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); 561 562 /* program default cache read and write policy */ 563 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); 564 /* clean read policy and write policy bits */ 565 temp &= 0xFF0FFF; 566 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 567 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 568 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 569 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); 570 571 if (!amdgpu_sriov_vf(adev)) { 572 /* unhalt engine */ 573 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 574 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 575 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); 576 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); 577 } 578 579 /* enable DMA RB */ 580 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); 581 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 582 583 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); 584 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); 585 #ifdef __BIG_ENDIAN 586 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); 587 #endif 588 /* enable DMA IBs */ 589 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); 590 591 ring->sched.ready = true; 592 593 if (amdgpu_sriov_vf(adev)) 594 sdma_v6_0_enable(adev, true); 595 596 r = amdgpu_ring_test_helper(ring); 597 if (r) { 598 ring->sched.ready = false; 599 return r; 600 } 601 602 if (adev->mman.buffer_funcs_ring == ring) 603 amdgpu_ttm_set_buffer_funcs_status(adev, true); 604 } 605 606 return 0; 607 } 608 609 /** 610 * sdma_v6_0_rlc_resume - setup and start the async dma engines 611 * 612 * @adev: amdgpu_device pointer 613 * 614 * Set up the compute DMA queues and enable them. 615 * Returns 0 for success, error for failure. 616 */ 617 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev) 618 { 619 return 0; 620 } 621 622 /** 623 * sdma_v6_0_load_microcode - load the sDMA ME ucode 624 * 625 * @adev: amdgpu_device pointer 626 * 627 * Loads the sDMA0/1 ucode. 628 * Returns 0 for success, -EINVAL if the ucode is not available. 629 */ 630 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev) 631 { 632 const struct sdma_firmware_header_v2_0 *hdr; 633 const __le32 *fw_data; 634 u32 fw_size; 635 int i, j; 636 bool use_broadcast; 637 638 /* halt the MEs */ 639 sdma_v6_0_enable(adev, false); 640 641 if (!adev->sdma.instance[0].fw) 642 return -EINVAL; 643 644 /* use broadcast mode to load SDMA microcode by default */ 645 use_broadcast = true; 646 647 if (use_broadcast) { 648 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n"); 649 /* load Control Thread microcode */ 650 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 651 amdgpu_ucode_print_sdma_hdr(&hdr->header); 652 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 653 654 fw_data = (const __le32 *) 655 (adev->sdma.instance[0].fw->data + 656 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 657 658 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0); 659 660 for (j = 0; j < fw_size; j++) { 661 if (amdgpu_emu_mode == 1 && j % 500 == 0) 662 msleep(1); 663 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 664 } 665 666 /* load Context Switch microcode */ 667 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 668 669 fw_data = (const __le32 *) 670 (adev->sdma.instance[0].fw->data + 671 le32_to_cpu(hdr->ctl_ucode_offset)); 672 673 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000); 674 675 for (j = 0; j < fw_size; j++) { 676 if (amdgpu_emu_mode == 1 && j % 500 == 0) 677 msleep(1); 678 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++)); 679 } 680 } else { 681 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n"); 682 for (i = 0; i < adev->sdma.num_instances; i++) { 683 /* load Control Thread microcode */ 684 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data; 685 amdgpu_ucode_print_sdma_hdr(&hdr->header); 686 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4; 687 688 fw_data = (const __le32 *) 689 (adev->sdma.instance[0].fw->data + 690 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 691 692 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0); 693 694 for (j = 0; j < fw_size; j++) { 695 if (amdgpu_emu_mode == 1 && j % 500 == 0) 696 msleep(1); 697 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 698 } 699 700 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 701 702 /* load Context Switch microcode */ 703 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4; 704 705 fw_data = (const __le32 *) 706 (adev->sdma.instance[0].fw->data + 707 le32_to_cpu(hdr->ctl_ucode_offset)); 708 709 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000); 710 711 for (j = 0; j < fw_size; j++) { 712 if (amdgpu_emu_mode == 1 && j % 500 == 0) 713 msleep(1); 714 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 715 } 716 717 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version); 718 } 719 } 720 721 return 0; 722 } 723 724 static int sdma_v6_0_soft_reset(void *handle) 725 { 726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 727 u32 tmp; 728 int i; 729 730 sdma_v6_0_gfx_stop(adev); 731 732 for (i = 0; i < adev->sdma.num_instances; i++) { 733 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE)); 734 tmp |= SDMA0_FREEZE__FREEZE_MASK; 735 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp); 736 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); 737 tmp |= SDMA0_F32_CNTL__HALT_MASK; 738 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK; 739 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp); 740 741 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0); 742 743 udelay(100); 744 745 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; 746 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); 747 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 748 749 udelay(100); 750 751 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); 752 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); 753 754 udelay(100); 755 } 756 757 return sdma_v6_0_start(adev); 758 } 759 760 static bool sdma_v6_0_check_soft_reset(void *handle) 761 { 762 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 763 struct amdgpu_ring *ring; 764 int i, r; 765 long tmo = msecs_to_jiffies(1000); 766 767 for (i = 0; i < adev->sdma.num_instances; i++) { 768 ring = &adev->sdma.instance[i].ring; 769 r = amdgpu_ring_test_ib(ring, tmo); 770 if (r) 771 return true; 772 } 773 774 return false; 775 } 776 777 /** 778 * sdma_v6_0_start - setup and start the async dma engines 779 * 780 * @adev: amdgpu_device pointer 781 * 782 * Set up the DMA engines and enable them. 783 * Returns 0 for success, error for failure. 784 */ 785 static int sdma_v6_0_start(struct amdgpu_device *adev) 786 { 787 int r = 0; 788 789 if (amdgpu_sriov_vf(adev)) { 790 sdma_v6_0_enable(adev, false); 791 792 /* set RB registers */ 793 r = sdma_v6_0_gfx_resume(adev); 794 return r; 795 } 796 797 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 798 r = sdma_v6_0_load_microcode(adev); 799 if (r) 800 return r; 801 802 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */ 803 if (amdgpu_emu_mode == 1) 804 msleep(1000); 805 } 806 807 /* unhalt the MEs */ 808 sdma_v6_0_enable(adev, true); 809 /* enable sdma ring preemption */ 810 sdma_v6_0_ctxempty_int_enable(adev, true); 811 812 /* start the gfx rings and rlc compute queues */ 813 r = sdma_v6_0_gfx_resume(adev); 814 if (r) 815 return r; 816 r = sdma_v6_0_rlc_resume(adev); 817 818 return r; 819 } 820 821 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd, 822 struct amdgpu_mqd_prop *prop) 823 { 824 struct v11_sdma_mqd *m = mqd; 825 uint64_t wb_gpu_addr; 826 827 m->sdmax_rlcx_rb_cntl = 828 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | 829 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 830 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 831 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; 832 833 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 834 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 835 836 wb_gpu_addr = prop->wptr_gpu_addr; 837 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 838 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 839 840 wb_gpu_addr = prop->rptr_gpu_addr; 841 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 842 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 843 844 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0, 845 regSDMA0_QUEUE0_IB_CNTL)); 846 847 m->sdmax_rlcx_doorbell_offset = 848 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; 849 850 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); 851 852 m->sdmax_rlcx_skip_cntl = 0; 853 m->sdmax_rlcx_context_status = 0; 854 m->sdmax_rlcx_doorbell_log = 0; 855 856 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT; 857 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT; 858 859 return 0; 860 } 861 862 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev) 863 { 864 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd); 865 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init; 866 } 867 868 /** 869 * sdma_v6_0_ring_test_ring - simple async dma engine test 870 * 871 * @ring: amdgpu_ring structure holding ring information 872 * 873 * Test the DMA engine by writing using it to write an 874 * value to memory. 875 * Returns 0 for success, error for failure. 876 */ 877 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) 878 { 879 struct amdgpu_device *adev = ring->adev; 880 unsigned i; 881 unsigned index; 882 int r; 883 u32 tmp; 884 u64 gpu_addr; 885 volatile uint32_t *cpu_ptr = NULL; 886 887 tmp = 0xCAFEDEAD; 888 889 if (ring->is_mes_queue) { 890 uint32_t offset = 0; 891 offset = amdgpu_mes_ctx_get_offs(ring, 892 AMDGPU_MES_CTX_PADDING_OFFS); 893 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 894 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 895 *cpu_ptr = tmp; 896 } else { 897 r = amdgpu_device_wb_get(adev, &index); 898 if (r) { 899 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 900 return r; 901 } 902 903 gpu_addr = adev->wb.gpu_addr + (index * 4); 904 adev->wb.wb[index] = cpu_to_le32(tmp); 905 } 906 907 r = amdgpu_ring_alloc(ring, 5); 908 if (r) { 909 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 910 amdgpu_device_wb_free(adev, index); 911 return r; 912 } 913 914 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 915 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 916 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 917 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 918 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 919 amdgpu_ring_write(ring, 0xDEADBEEF); 920 amdgpu_ring_commit(ring); 921 922 for (i = 0; i < adev->usec_timeout; i++) { 923 if (ring->is_mes_queue) 924 tmp = le32_to_cpu(*cpu_ptr); 925 else 926 tmp = le32_to_cpu(adev->wb.wb[index]); 927 if (tmp == 0xDEADBEEF) 928 break; 929 if (amdgpu_emu_mode == 1) 930 msleep(1); 931 else 932 udelay(1); 933 } 934 935 if (i >= adev->usec_timeout) 936 r = -ETIMEDOUT; 937 938 if (!ring->is_mes_queue) 939 amdgpu_device_wb_free(adev, index); 940 941 return r; 942 } 943 944 /** 945 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine 946 * 947 * @ring: amdgpu_ring structure holding ring information 948 * 949 * Test a simple IB in the DMA ring. 950 * Returns 0 on success, error on failure. 951 */ 952 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 953 { 954 struct amdgpu_device *adev = ring->adev; 955 struct amdgpu_ib ib; 956 struct dma_fence *f = NULL; 957 unsigned index; 958 long r; 959 u32 tmp = 0; 960 u64 gpu_addr; 961 volatile uint32_t *cpu_ptr = NULL; 962 963 tmp = 0xCAFEDEAD; 964 memset(&ib, 0, sizeof(ib)); 965 966 if (ring->is_mes_queue) { 967 uint32_t offset = 0; 968 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 969 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 970 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 971 972 offset = amdgpu_mes_ctx_get_offs(ring, 973 AMDGPU_MES_CTX_PADDING_OFFS); 974 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 975 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 976 *cpu_ptr = tmp; 977 } else { 978 r = amdgpu_device_wb_get(adev, &index); 979 if (r) { 980 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 981 return r; 982 } 983 984 gpu_addr = adev->wb.gpu_addr + (index * 4); 985 adev->wb.wb[index] = cpu_to_le32(tmp); 986 987 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 988 if (r) { 989 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 990 goto err0; 991 } 992 } 993 994 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 995 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 996 ib.ptr[1] = lower_32_bits(gpu_addr); 997 ib.ptr[2] = upper_32_bits(gpu_addr); 998 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 999 ib.ptr[4] = 0xDEADBEEF; 1000 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1001 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1002 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1003 ib.length_dw = 8; 1004 1005 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1006 if (r) 1007 goto err1; 1008 1009 r = dma_fence_wait_timeout(f, false, timeout); 1010 if (r == 0) { 1011 DRM_ERROR("amdgpu: IB test timed out\n"); 1012 r = -ETIMEDOUT; 1013 goto err1; 1014 } else if (r < 0) { 1015 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1016 goto err1; 1017 } 1018 1019 if (ring->is_mes_queue) 1020 tmp = le32_to_cpu(*cpu_ptr); 1021 else 1022 tmp = le32_to_cpu(adev->wb.wb[index]); 1023 1024 if (tmp == 0xDEADBEEF) 1025 r = 0; 1026 else 1027 r = -EINVAL; 1028 1029 err1: 1030 amdgpu_ib_free(adev, &ib, NULL); 1031 dma_fence_put(f); 1032 err0: 1033 if (!ring->is_mes_queue) 1034 amdgpu_device_wb_free(adev, index); 1035 return r; 1036 } 1037 1038 1039 /** 1040 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART 1041 * 1042 * @ib: indirect buffer to fill with commands 1043 * @pe: addr of the page entry 1044 * @src: src addr to copy from 1045 * @count: number of page entries to update 1046 * 1047 * Update PTEs by copying them from the GART using sDMA. 1048 */ 1049 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib, 1050 uint64_t pe, uint64_t src, 1051 unsigned count) 1052 { 1053 unsigned bytes = count * 8; 1054 1055 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1056 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1057 ib->ptr[ib->length_dw++] = bytes - 1; 1058 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1059 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1060 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1061 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1062 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1063 1064 } 1065 1066 /** 1067 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually 1068 * 1069 * @ib: indirect buffer to fill with commands 1070 * @pe: addr of the page entry 1071 * @value: dst addr to write into pe 1072 * @count: number of page entries to update 1073 * @incr: increase next addr by incr bytes 1074 * 1075 * Update PTEs by writing them manually using sDMA. 1076 */ 1077 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1078 uint64_t value, unsigned count, 1079 uint32_t incr) 1080 { 1081 unsigned ndw = count * 2; 1082 1083 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | 1084 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1085 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1086 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1087 ib->ptr[ib->length_dw++] = ndw - 1; 1088 for (; ndw > 0; ndw -= 2) { 1089 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1090 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1091 value += incr; 1092 } 1093 } 1094 1095 /** 1096 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA 1097 * 1098 * @ib: indirect buffer to fill with commands 1099 * @pe: addr of the page entry 1100 * @addr: dst addr to write into pe 1101 * @count: number of page entries to update 1102 * @incr: increase next addr by incr bytes 1103 * @flags: access flags 1104 * 1105 * Update the page tables using sDMA. 1106 */ 1107 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1108 uint64_t pe, 1109 uint64_t addr, unsigned count, 1110 uint32_t incr, uint64_t flags) 1111 { 1112 /* for physically contiguous pages (vram) */ 1113 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); 1114 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1115 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1116 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1117 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1118 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1119 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1120 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1121 ib->ptr[ib->length_dw++] = 0; 1122 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1123 } 1124 1125 /** 1126 * sdma_v6_0_ring_pad_ib - pad the IB 1127 * @ib: indirect buffer to fill with padding 1128 * 1129 * Pad the IB with NOPs to a boundary multiple of 8. 1130 */ 1131 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1132 { 1133 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1134 u32 pad_count; 1135 int i; 1136 1137 pad_count = (-ib->length_dw) & 0x7; 1138 for (i = 0; i < pad_count; i++) 1139 if (sdma && sdma->burst_nop && (i == 0)) 1140 ib->ptr[ib->length_dw++] = 1141 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | 1142 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1143 else 1144 ib->ptr[ib->length_dw++] = 1145 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); 1146 } 1147 1148 /** 1149 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline 1150 * 1151 * @ring: amdgpu_ring pointer 1152 * 1153 * Make sure all previous operations are completed (CIK). 1154 */ 1155 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1156 { 1157 uint32_t seq = ring->fence_drv.sync_seq; 1158 uint64_t addr = ring->fence_drv.gpu_addr; 1159 1160 /* wait for idle */ 1161 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1162 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1163 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1164 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1165 amdgpu_ring_write(ring, addr & 0xfffffffc); 1166 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1167 amdgpu_ring_write(ring, seq); /* reference */ 1168 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1169 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1170 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1171 } 1172 1173 /** 1174 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA 1175 * 1176 * @ring: amdgpu_ring pointer 1177 * 1178 * Update the page table base and flush the VM TLB 1179 * using sDMA. 1180 */ 1181 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1182 unsigned vmid, uint64_t pd_addr) 1183 { 1184 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1185 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 1186 1187 /* Update the PD address for this VMID. */ 1188 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 1189 (hub->ctx_addr_distance * vmid), 1190 lower_32_bits(pd_addr)); 1191 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 1192 (hub->ctx_addr_distance * vmid), 1193 upper_32_bits(pd_addr)); 1194 1195 /* Trigger invalidation. */ 1196 amdgpu_ring_write(ring, 1197 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1198 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) | 1199 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) | 1200 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f)); 1201 amdgpu_ring_write(ring, req); 1202 amdgpu_ring_write(ring, 0xFFFFFFFF); 1203 amdgpu_ring_write(ring, 1204 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) | 1205 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F)); 1206 } 1207 1208 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1209 uint32_t reg, uint32_t val) 1210 { 1211 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1212 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1213 amdgpu_ring_write(ring, reg); 1214 amdgpu_ring_write(ring, val); 1215 } 1216 1217 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1218 uint32_t val, uint32_t mask) 1219 { 1220 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1221 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1222 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1223 amdgpu_ring_write(ring, reg << 2); 1224 amdgpu_ring_write(ring, 0); 1225 amdgpu_ring_write(ring, val); /* reference */ 1226 amdgpu_ring_write(ring, mask); /* mask */ 1227 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1228 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1229 } 1230 1231 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1232 uint32_t reg0, uint32_t reg1, 1233 uint32_t ref, uint32_t mask) 1234 { 1235 amdgpu_ring_emit_wreg(ring, reg0, ref); 1236 /* wait for a cycle to reset vm_inv_eng*_ack */ 1237 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1238 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1239 } 1240 1241 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = { 1242 .ras_block = { 1243 .ras_late_init = amdgpu_ras_block_late_init, 1244 }, 1245 }; 1246 1247 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev) 1248 { 1249 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1250 case IP_VERSION(6, 0, 3): 1251 adev->sdma.ras = &sdma_v6_0_3_ras; 1252 break; 1253 default: 1254 break; 1255 } 1256 1257 } 1258 1259 static int sdma_v6_0_early_init(void *handle) 1260 { 1261 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1262 1263 sdma_v6_0_set_ring_funcs(adev); 1264 sdma_v6_0_set_buffer_funcs(adev); 1265 sdma_v6_0_set_vm_pte_funcs(adev); 1266 sdma_v6_0_set_irq_funcs(adev); 1267 sdma_v6_0_set_mqd_funcs(adev); 1268 sdma_v6_0_set_ras_funcs(adev); 1269 1270 return 0; 1271 } 1272 1273 static int sdma_v6_0_sw_init(void *handle) 1274 { 1275 struct amdgpu_ring *ring; 1276 int r, i; 1277 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1278 1279 /* SDMA trap event */ 1280 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 1281 GFX_11_0_0__SRCID__SDMA_TRAP, 1282 &adev->sdma.trap_irq); 1283 if (r) 1284 return r; 1285 1286 r = amdgpu_sdma_init_microcode(adev, 0, true); 1287 if (r) { 1288 DRM_ERROR("Failed to load sdma firmware!\n"); 1289 return r; 1290 } 1291 1292 for (i = 0; i < adev->sdma.num_instances; i++) { 1293 ring = &adev->sdma.instance[i].ring; 1294 ring->ring_obj = NULL; 1295 ring->use_doorbell = true; 1296 ring->me = i; 1297 1298 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1299 ring->use_doorbell?"true":"false"); 1300 1301 ring->doorbell_index = 1302 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset 1303 1304 ring->vm_hub = AMDGPU_GFXHUB_0; 1305 sprintf(ring->name, "sdma%d", i); 1306 r = amdgpu_ring_init(adev, ring, 1024, 1307 &adev->sdma.trap_irq, 1308 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1309 AMDGPU_RING_PRIO_DEFAULT, NULL); 1310 if (r) 1311 return r; 1312 } 1313 1314 if (amdgpu_sdma_ras_sw_init(adev)) { 1315 dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); 1316 return -EINVAL; 1317 } 1318 1319 return r; 1320 } 1321 1322 static int sdma_v6_0_sw_fini(void *handle) 1323 { 1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1325 int i; 1326 1327 for (i = 0; i < adev->sdma.num_instances; i++) 1328 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1329 1330 amdgpu_sdma_destroy_inst_ctx(adev, true); 1331 1332 return 0; 1333 } 1334 1335 static int sdma_v6_0_hw_init(void *handle) 1336 { 1337 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1338 1339 return sdma_v6_0_start(adev); 1340 } 1341 1342 static int sdma_v6_0_hw_fini(void *handle) 1343 { 1344 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1345 1346 if (amdgpu_sriov_vf(adev)) { 1347 /* disable the scheduler for SDMA */ 1348 amdgpu_sdma_unset_buffer_funcs_helper(adev); 1349 return 0; 1350 } 1351 1352 sdma_v6_0_ctxempty_int_enable(adev, false); 1353 sdma_v6_0_enable(adev, false); 1354 1355 return 0; 1356 } 1357 1358 static int sdma_v6_0_suspend(void *handle) 1359 { 1360 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1361 1362 return sdma_v6_0_hw_fini(adev); 1363 } 1364 1365 static int sdma_v6_0_resume(void *handle) 1366 { 1367 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1368 1369 return sdma_v6_0_hw_init(adev); 1370 } 1371 1372 static bool sdma_v6_0_is_idle(void *handle) 1373 { 1374 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1375 u32 i; 1376 1377 for (i = 0; i < adev->sdma.num_instances; i++) { 1378 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); 1379 1380 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1381 return false; 1382 } 1383 1384 return true; 1385 } 1386 1387 static int sdma_v6_0_wait_for_idle(void *handle) 1388 { 1389 unsigned i; 1390 u32 sdma0, sdma1; 1391 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1392 1393 for (i = 0; i < adev->usec_timeout; i++) { 1394 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); 1395 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); 1396 1397 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1398 return 0; 1399 udelay(1); 1400 } 1401 return -ETIMEDOUT; 1402 } 1403 1404 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) 1405 { 1406 int i, r = 0; 1407 struct amdgpu_device *adev = ring->adev; 1408 u32 index = 0; 1409 u64 sdma_gfx_preempt; 1410 1411 amdgpu_sdma_get_index_from_ring(ring, &index); 1412 sdma_gfx_preempt = 1413 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT); 1414 1415 /* assert preemption condition */ 1416 amdgpu_ring_set_preempt_cond_exec(ring, false); 1417 1418 /* emit the trailing fence */ 1419 ring->trail_seq += 1; 1420 amdgpu_ring_alloc(ring, 10); 1421 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1422 ring->trail_seq, 0); 1423 amdgpu_ring_commit(ring); 1424 1425 /* assert IB preemption */ 1426 WREG32(sdma_gfx_preempt, 1); 1427 1428 /* poll the trailing fence */ 1429 for (i = 0; i < adev->usec_timeout; i++) { 1430 if (ring->trail_seq == 1431 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1432 break; 1433 udelay(1); 1434 } 1435 1436 if (i >= adev->usec_timeout) { 1437 r = -EINVAL; 1438 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1439 } 1440 1441 /* deassert IB preemption */ 1442 WREG32(sdma_gfx_preempt, 0); 1443 1444 /* deassert the preemption condition */ 1445 amdgpu_ring_set_preempt_cond_exec(ring, true); 1446 return r; 1447 } 1448 1449 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, 1450 struct amdgpu_irq_src *source, 1451 unsigned type, 1452 enum amdgpu_interrupt_state state) 1453 { 1454 u32 sdma_cntl; 1455 1456 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL); 1457 1458 if (!amdgpu_sriov_vf(adev)) { 1459 sdma_cntl = RREG32(reg_offset); 1460 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1461 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1462 WREG32(reg_offset, sdma_cntl); 1463 } 1464 1465 return 0; 1466 } 1467 1468 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev, 1469 struct amdgpu_irq_src *source, 1470 struct amdgpu_iv_entry *entry) 1471 { 1472 int instances, queue; 1473 uint32_t mes_queue_id = entry->src_data[0]; 1474 1475 DRM_DEBUG("IH: SDMA trap\n"); 1476 1477 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1478 struct amdgpu_mes_queue *queue; 1479 1480 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1481 1482 spin_lock(&adev->mes.queue_id_lock); 1483 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1484 if (queue) { 1485 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1486 amdgpu_fence_process(queue->ring); 1487 } 1488 spin_unlock(&adev->mes.queue_id_lock); 1489 return 0; 1490 } 1491 1492 queue = entry->ring_id & 0xf; 1493 instances = (entry->ring_id & 0xf0) >> 4; 1494 if (instances > 1) { 1495 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); 1496 return -EINVAL; 1497 } 1498 1499 switch (entry->client_id) { 1500 case SOC21_IH_CLIENTID_GFX: 1501 switch (queue) { 1502 case 0: 1503 amdgpu_fence_process(&adev->sdma.instance[instances].ring); 1504 break; 1505 default: 1506 break; 1507 } 1508 break; 1509 } 1510 return 0; 1511 } 1512 1513 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1514 struct amdgpu_irq_src *source, 1515 struct amdgpu_iv_entry *entry) 1516 { 1517 return 0; 1518 } 1519 1520 static int sdma_v6_0_set_clockgating_state(void *handle, 1521 enum amd_clockgating_state state) 1522 { 1523 return 0; 1524 } 1525 1526 static int sdma_v6_0_set_powergating_state(void *handle, 1527 enum amd_powergating_state state) 1528 { 1529 return 0; 1530 } 1531 1532 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags) 1533 { 1534 } 1535 1536 const struct amd_ip_funcs sdma_v6_0_ip_funcs = { 1537 .name = "sdma_v6_0", 1538 .early_init = sdma_v6_0_early_init, 1539 .late_init = NULL, 1540 .sw_init = sdma_v6_0_sw_init, 1541 .sw_fini = sdma_v6_0_sw_fini, 1542 .hw_init = sdma_v6_0_hw_init, 1543 .hw_fini = sdma_v6_0_hw_fini, 1544 .suspend = sdma_v6_0_suspend, 1545 .resume = sdma_v6_0_resume, 1546 .is_idle = sdma_v6_0_is_idle, 1547 .wait_for_idle = sdma_v6_0_wait_for_idle, 1548 .soft_reset = sdma_v6_0_soft_reset, 1549 .check_soft_reset = sdma_v6_0_check_soft_reset, 1550 .set_clockgating_state = sdma_v6_0_set_clockgating_state, 1551 .set_powergating_state = sdma_v6_0_set_powergating_state, 1552 .get_clockgating_state = sdma_v6_0_get_clockgating_state, 1553 }; 1554 1555 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { 1556 .type = AMDGPU_RING_TYPE_SDMA, 1557 .align_mask = 0xf, 1558 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1559 .support_64bit_ptrs = true, 1560 .secure_submission_supported = true, 1561 .get_rptr = sdma_v6_0_ring_get_rptr, 1562 .get_wptr = sdma_v6_0_ring_get_wptr, 1563 .set_wptr = sdma_v6_0_ring_set_wptr, 1564 .emit_frame_size = 1565 5 + /* sdma_v6_0_ring_init_cond_exec */ 1566 6 + /* sdma_v6_0_ring_emit_hdp_flush */ 1567 6 + /* sdma_v6_0_ring_emit_pipeline_sync */ 1568 /* sdma_v6_0_ring_emit_vm_flush */ 1569 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1570 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1571 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */ 1572 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */ 1573 .emit_ib = sdma_v6_0_ring_emit_ib, 1574 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync, 1575 .emit_fence = sdma_v6_0_ring_emit_fence, 1576 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync, 1577 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush, 1578 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush, 1579 .test_ring = sdma_v6_0_ring_test_ring, 1580 .test_ib = sdma_v6_0_ring_test_ib, 1581 .insert_nop = sdma_v6_0_ring_insert_nop, 1582 .pad_ib = sdma_v6_0_ring_pad_ib, 1583 .emit_wreg = sdma_v6_0_ring_emit_wreg, 1584 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait, 1585 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait, 1586 .init_cond_exec = sdma_v6_0_ring_init_cond_exec, 1587 .patch_cond_exec = sdma_v6_0_ring_patch_cond_exec, 1588 .preempt_ib = sdma_v6_0_ring_preempt_ib, 1589 }; 1590 1591 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1592 { 1593 int i; 1594 1595 for (i = 0; i < adev->sdma.num_instances; i++) { 1596 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs; 1597 adev->sdma.instance[i].ring.me = i; 1598 } 1599 } 1600 1601 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = { 1602 .set = sdma_v6_0_set_trap_irq_state, 1603 .process = sdma_v6_0_process_trap_irq, 1604 }; 1605 1606 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = { 1607 .process = sdma_v6_0_process_illegal_inst_irq, 1608 }; 1609 1610 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1611 { 1612 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1613 adev->sdma.num_instances; 1614 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs; 1615 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs; 1616 } 1617 1618 /** 1619 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine 1620 * 1621 * @ib: indirect buffer to fill with commands 1622 * @src_offset: src GPU address 1623 * @dst_offset: dst GPU address 1624 * @byte_count: number of bytes to xfer 1625 * @tmz: if a secure copy should be used 1626 * 1627 * Copy GPU buffers using the DMA engine. 1628 * Used by the amdgpu ttm implementation to move pages if 1629 * registered as the asic copy callback. 1630 */ 1631 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib, 1632 uint64_t src_offset, 1633 uint64_t dst_offset, 1634 uint32_t byte_count, 1635 bool tmz) 1636 { 1637 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | 1638 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1639 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1640 ib->ptr[ib->length_dw++] = byte_count - 1; 1641 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1642 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1643 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1644 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1645 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1646 } 1647 1648 /** 1649 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine 1650 * 1651 * @ib: indirect buffer to fill 1652 * @src_data: value to write to buffer 1653 * @dst_offset: dst GPU address 1654 * @byte_count: number of bytes to xfer 1655 * 1656 * Fill GPU buffers using the DMA engine. 1657 */ 1658 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, 1659 uint32_t src_data, 1660 uint64_t dst_offset, 1661 uint32_t byte_count) 1662 { 1663 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL); 1664 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1665 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1666 ib->ptr[ib->length_dw++] = src_data; 1667 ib->ptr[ib->length_dw++] = byte_count - 1; 1668 } 1669 1670 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { 1671 .copy_max_bytes = 0x400000, 1672 .copy_num_dw = 7, 1673 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, 1674 1675 .fill_max_bytes = 0x400000, 1676 .fill_num_dw = 5, 1677 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, 1678 }; 1679 1680 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) 1681 { 1682 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs; 1683 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1684 } 1685 1686 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { 1687 .copy_pte_num_dw = 7, 1688 .copy_pte = sdma_v6_0_vm_copy_pte, 1689 .write_pte = sdma_v6_0_vm_write_pte, 1690 .set_pte_pde = sdma_v6_0_vm_set_pte_pde, 1691 }; 1692 1693 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1694 { 1695 unsigned i; 1696 1697 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs; 1698 for (i = 0; i < adev->sdma.num_instances; i++) { 1699 adev->vm_manager.vm_pte_scheds[i] = 1700 &adev->sdma.instance[i].ring.sched; 1701 } 1702 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1703 } 1704 1705 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { 1706 .type = AMD_IP_BLOCK_TYPE_SDMA, 1707 .major = 6, 1708 .minor = 0, 1709 .rev = 0, 1710 .funcs = &sdma_v6_0_ip_funcs, 1711 }; 1712