1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_3_0_offset.h" 34 #include "gc/gc_10_3_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" 38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "navi10_sdma_pkt_open.h" 43 #include "nbio_v2_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v5_2.h" 46 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); 50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); 51 52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); 54 55 #define SDMA1_REG_OFFSET 0x600 56 #define SDMA3_REG_OFFSET 0x400 57 #define SDMA0_HYP_DEC_REG_START 0x5880 58 #define SDMA0_HYP_DEC_REG_END 0x5893 59 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 60 61 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 62 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 63 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 64 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 65 66 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 67 { 68 u32 base; 69 70 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 71 internal_offset <= SDMA0_HYP_DEC_REG_END) { 72 base = adev->reg_offset[GC_HWIP][0][1]; 73 if (instance != 0) 74 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 75 } else { 76 if (instance < 2) { 77 base = adev->reg_offset[GC_HWIP][0][0]; 78 if (instance == 1) 79 internal_offset += SDMA1_REG_OFFSET; 80 } else { 81 base = adev->reg_offset[GC_HWIP][0][2]; 82 if (instance == 3) 83 internal_offset += SDMA3_REG_OFFSET; 84 } 85 } 86 87 return base + internal_offset; 88 } 89 90 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 91 { 92 int err = 0; 93 const struct sdma_firmware_header_v1_0 *hdr; 94 95 err = amdgpu_ucode_validate(sdma_inst->fw); 96 if (err) 97 return err; 98 99 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 100 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 101 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 102 103 if (sdma_inst->feature_version >= 20) 104 sdma_inst->burst_nop = true; 105 106 return 0; 107 } 108 109 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev) 110 { 111 release_firmware(adev->sdma.instance[0].fw); 112 113 memset((void *)adev->sdma.instance, 0, 114 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 115 } 116 117 /** 118 * sdma_v5_2_init_microcode - load ucode images from disk 119 * 120 * @adev: amdgpu_device pointer 121 * 122 * Use the firmware interface to load the ucode images into 123 * the driver (not loaded into hw). 124 * Returns 0 on success, error on failure. 125 */ 126 127 // emulation only, won't work on real chip 128 // navi10 real chip need to use PSP to load firmware 129 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) 130 { 131 const char *chip_name; 132 char fw_name[40]; 133 int err = 0, i; 134 struct amdgpu_firmware_info *info = NULL; 135 const struct common_firmware_header *header = NULL; 136 137 DRM_DEBUG("\n"); 138 139 switch (adev->ip_versions[SDMA0_HWIP][0]) { 140 case IP_VERSION(5, 2, 0): 141 chip_name = "sienna_cichlid"; 142 break; 143 case IP_VERSION(5, 2, 2): 144 chip_name = "navy_flounder"; 145 break; 146 case IP_VERSION(5, 2, 1): 147 chip_name = "vangogh"; 148 break; 149 case IP_VERSION(5, 2, 4): 150 chip_name = "dimgrey_cavefish"; 151 break; 152 case IP_VERSION(5, 2, 5): 153 chip_name = "beige_goby"; 154 break; 155 case IP_VERSION(5, 2, 3): 156 chip_name = "yellow_carp"; 157 break; 158 default: 159 BUG(); 160 } 161 162 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 163 164 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 165 if (err) 166 goto out; 167 168 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]); 169 if (err) 170 goto out; 171 172 for (i = 1; i < adev->sdma.num_instances; i++) 173 memcpy((void *)&adev->sdma.instance[i], 174 (void *)&adev->sdma.instance[0], 175 sizeof(struct amdgpu_sdma_instance)); 176 177 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0))) 178 return 0; 179 180 DRM_DEBUG("psp_load == '%s'\n", 181 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 182 183 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 184 for (i = 0; i < adev->sdma.num_instances; i++) { 185 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 186 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 187 info->fw = adev->sdma.instance[i].fw; 188 header = (const struct common_firmware_header *)info->fw->data; 189 adev->firmware.fw_size += 190 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 191 } 192 } 193 194 out: 195 if (err) { 196 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name); 197 sdma_v5_2_destroy_inst_ctx(adev); 198 } 199 return err; 200 } 201 202 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) 203 { 204 unsigned ret; 205 206 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 207 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 208 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 209 amdgpu_ring_write(ring, 1); 210 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 211 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 212 213 return ret; 214 } 215 216 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring, 217 unsigned offset) 218 { 219 unsigned cur; 220 221 BUG_ON(offset > ring->buf_mask); 222 BUG_ON(ring->ring[offset] != 0x55aa55aa); 223 224 cur = (ring->wptr - 1) & ring->buf_mask; 225 if (cur > offset) 226 ring->ring[offset] = cur - offset; 227 else 228 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 229 } 230 231 /** 232 * sdma_v5_2_ring_get_rptr - get the current read pointer 233 * 234 * @ring: amdgpu ring pointer 235 * 236 * Get the current rptr from the hardware (NAVI10+). 237 */ 238 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) 239 { 240 u64 *rptr; 241 242 /* XXX check if swapping is necessary on BE */ 243 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 244 245 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 246 return ((*rptr) >> 2); 247 } 248 249 /** 250 * sdma_v5_2_ring_get_wptr - get the current write pointer 251 * 252 * @ring: amdgpu ring pointer 253 * 254 * Get the current wptr from the hardware (NAVI10+). 255 */ 256 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) 257 { 258 struct amdgpu_device *adev = ring->adev; 259 u64 wptr; 260 261 if (ring->use_doorbell) { 262 /* XXX check if swapping is necessary on BE */ 263 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 264 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 265 } else { 266 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 267 wptr = wptr << 32; 268 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 269 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 270 } 271 272 return wptr >> 2; 273 } 274 275 /** 276 * sdma_v5_2_ring_set_wptr - commit the write pointer 277 * 278 * @ring: amdgpu ring pointer 279 * 280 * Write the wptr back to the hardware (NAVI10+). 281 */ 282 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) 283 { 284 struct amdgpu_device *adev = ring->adev; 285 286 DRM_DEBUG("Setting write pointer\n"); 287 if (ring->use_doorbell) { 288 DRM_DEBUG("Using doorbell -- " 289 "wptr_offs == 0x%08x " 290 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 291 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 292 ring->wptr_offs, 293 lower_32_bits(ring->wptr << 2), 294 upper_32_bits(ring->wptr << 2)); 295 /* XXX check if swapping is necessary on BE */ 296 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 297 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 298 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 299 ring->doorbell_index, ring->wptr << 2); 300 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 301 } else { 302 DRM_DEBUG("Not using doorbell -- " 303 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 304 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 305 ring->me, 306 lower_32_bits(ring->wptr << 2), 307 ring->me, 308 upper_32_bits(ring->wptr << 2)); 309 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 310 lower_32_bits(ring->wptr << 2)); 311 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 312 upper_32_bits(ring->wptr << 2)); 313 } 314 } 315 316 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 317 { 318 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 319 int i; 320 321 for (i = 0; i < count; i++) 322 if (sdma && sdma->burst_nop && (i == 0)) 323 amdgpu_ring_write(ring, ring->funcs->nop | 324 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 325 else 326 amdgpu_ring_write(ring, ring->funcs->nop); 327 } 328 329 /** 330 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine 331 * 332 * @ring: amdgpu ring pointer 333 * @job: job to retrieve vmid from 334 * @ib: IB object to schedule 335 * @flags: unused 336 * 337 * Schedule an IB in the DMA ring. 338 */ 339 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, 340 struct amdgpu_job *job, 341 struct amdgpu_ib *ib, 342 uint32_t flags) 343 { 344 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 345 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 346 347 /* An IB packet must end on a 8 DW boundary--the next dword 348 * must be on a 8-dword boundary. Our IB packet below is 6 349 * dwords long, thus add x number of NOPs, such that, in 350 * modular arithmetic, 351 * wptr + 6 + x = 8k, k >= 0, which in C is, 352 * (wptr + 6 + x) % 8 = 0. 353 * The expression below, is a solution of x. 354 */ 355 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 356 357 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 358 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 359 /* base must be 32 byte aligned */ 360 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 361 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 362 amdgpu_ring_write(ring, ib->length_dw); 363 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 364 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 365 } 366 367 /** 368 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse 369 * 370 * @ring: amdgpu ring pointer 371 * @job: job to retrieve vmid from 372 * @ib: IB object to schedule 373 * 374 * flush the IB by graphics cache rinse. 375 */ 376 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) 377 { 378 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | 379 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV | 380 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 381 SDMA_GCR_GLI_INV(1); 382 383 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 384 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 385 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 386 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 387 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 388 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 389 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 390 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 391 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 392 } 393 394 /** 395 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 396 * 397 * @ring: amdgpu ring pointer 398 * 399 * Emit an hdp flush packet on the requested DMA ring. 400 */ 401 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 402 { 403 struct amdgpu_device *adev = ring->adev; 404 u32 ref_and_mask = 0; 405 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 406 407 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 408 409 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 410 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 411 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 412 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 413 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 414 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 415 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 416 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 417 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 418 } 419 420 /** 421 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring 422 * 423 * @ring: amdgpu ring pointer 424 * @addr: address 425 * @seq: sequence number 426 * @flags: fence related flags 427 * 428 * Add a DMA fence packet to the ring to write 429 * the fence seq number and DMA trap packet to generate 430 * an interrupt if needed. 431 */ 432 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 433 unsigned flags) 434 { 435 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 436 /* write the fence */ 437 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 438 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 439 /* zero in first two bits */ 440 BUG_ON(addr & 0x3); 441 amdgpu_ring_write(ring, lower_32_bits(addr)); 442 amdgpu_ring_write(ring, upper_32_bits(addr)); 443 amdgpu_ring_write(ring, lower_32_bits(seq)); 444 445 /* optionally write high bits as well */ 446 if (write64bit) { 447 addr += 4; 448 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 449 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 450 /* zero in first two bits */ 451 BUG_ON(addr & 0x3); 452 amdgpu_ring_write(ring, lower_32_bits(addr)); 453 amdgpu_ring_write(ring, upper_32_bits(addr)); 454 amdgpu_ring_write(ring, upper_32_bits(seq)); 455 } 456 457 if (flags & AMDGPU_FENCE_FLAG_INT) { 458 /* generate an interrupt */ 459 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 460 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 461 } 462 } 463 464 465 /** 466 * sdma_v5_2_gfx_stop - stop the gfx async dma engines 467 * 468 * @adev: amdgpu_device pointer 469 * 470 * Stop the gfx async dma ring buffers. 471 */ 472 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) 473 { 474 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 475 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 476 struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring; 477 struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring; 478 u32 rb_cntl, ib_cntl; 479 int i; 480 481 if ((adev->mman.buffer_funcs_ring == sdma0) || 482 (adev->mman.buffer_funcs_ring == sdma1) || 483 (adev->mman.buffer_funcs_ring == sdma2) || 484 (adev->mman.buffer_funcs_ring == sdma3)) 485 amdgpu_ttm_set_buffer_funcs_status(adev, false); 486 487 for (i = 0; i < adev->sdma.num_instances; i++) { 488 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 489 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 490 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 491 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 492 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 493 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 494 } 495 } 496 497 /** 498 * sdma_v5_2_rlc_stop - stop the compute async dma engines 499 * 500 * @adev: amdgpu_device pointer 501 * 502 * Stop the compute async dma queues. 503 */ 504 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) 505 { 506 /* XXX todo */ 507 } 508 509 /** 510 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch 511 * 512 * @adev: amdgpu_device pointer 513 * @enable: enable/disable the DMA MEs context switch. 514 * 515 * Halt or unhalt the async dma engines context switch. 516 */ 517 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 518 { 519 u32 f32_cntl, phase_quantum = 0; 520 int i; 521 522 if (amdgpu_sdma_phase_quantum) { 523 unsigned value = amdgpu_sdma_phase_quantum; 524 unsigned unit = 0; 525 526 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 527 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 528 value = (value + 1) >> 1; 529 unit++; 530 } 531 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 532 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 533 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 534 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 535 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 536 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 537 WARN_ONCE(1, 538 "clamping sdma_phase_quantum to %uK clock cycles\n", 539 value << unit); 540 } 541 phase_quantum = 542 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 543 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 544 } 545 546 for (i = 0; i < adev->sdma.num_instances; i++) { 547 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 548 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 549 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 550 if (enable && amdgpu_sdma_phase_quantum) { 551 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 552 phase_quantum); 553 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 554 phase_quantum); 555 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 556 phase_quantum); 557 } 558 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 559 } 560 561 } 562 563 /** 564 * sdma_v5_2_enable - stop the async dma engines 565 * 566 * @adev: amdgpu_device pointer 567 * @enable: enable/disable the DMA MEs. 568 * 569 * Halt or unhalt the async dma engines. 570 */ 571 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) 572 { 573 u32 f32_cntl; 574 int i; 575 576 if (!enable) { 577 sdma_v5_2_gfx_stop(adev); 578 sdma_v5_2_rlc_stop(adev); 579 } 580 581 for (i = 0; i < adev->sdma.num_instances; i++) { 582 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 583 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 584 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 585 } 586 } 587 588 /** 589 * sdma_v5_2_gfx_resume - setup and start the async dma engines 590 * 591 * @adev: amdgpu_device pointer 592 * 593 * Set up the gfx DMA ring buffers and enable them. 594 * Returns 0 for success, error for failure. 595 */ 596 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 597 { 598 struct amdgpu_ring *ring; 599 u32 rb_cntl, ib_cntl; 600 u32 rb_bufsz; 601 u32 wb_offset; 602 u32 doorbell; 603 u32 doorbell_offset; 604 u32 temp; 605 u32 wptr_poll_cntl; 606 u64 wptr_gpu_addr; 607 int i, r; 608 609 for (i = 0; i < adev->sdma.num_instances; i++) { 610 ring = &adev->sdma.instance[i].ring; 611 wb_offset = (ring->rptr_offs * 4); 612 613 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 614 615 /* Set ring buffer size in dwords */ 616 rb_bufsz = order_base_2(ring->ring_size / 4); 617 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 618 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 619 #ifdef __BIG_ENDIAN 620 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 621 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 622 RPTR_WRITEBACK_SWAP_ENABLE, 1); 623 #endif 624 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 625 626 /* Initialize the ring buffer's read and write pointers */ 627 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 628 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 629 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 630 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 631 632 /* setup the wptr shadow polling */ 633 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 634 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 635 lower_32_bits(wptr_gpu_addr)); 636 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 637 upper_32_bits(wptr_gpu_addr)); 638 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 639 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 640 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 641 SDMA0_GFX_RB_WPTR_POLL_CNTL, 642 F32_POLL_ENABLE, 1); 643 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 644 wptr_poll_cntl); 645 646 /* set the wb address whether it's enabled or not */ 647 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 648 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 649 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 650 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 651 652 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 653 654 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 655 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 656 657 ring->wptr = 0; 658 659 /* before programing wptr to a less value, need set minor_ptr_update first */ 660 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 661 662 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 663 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 664 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 665 } 666 667 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 668 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 669 670 if (ring->use_doorbell) { 671 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 672 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 673 OFFSET, ring->doorbell_index); 674 } else { 675 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 676 } 677 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 678 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 679 680 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 681 ring->doorbell_index, 682 adev->doorbell_index.sdma_doorbell_range); 683 684 if (amdgpu_sriov_vf(adev)) 685 sdma_v5_2_ring_set_wptr(ring); 686 687 /* set minor_ptr_update to 0 after wptr programed */ 688 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 689 690 /* set utc l1 enable flag always to 1 */ 691 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 692 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 693 694 /* enable MCBP */ 695 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 696 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 697 698 /* Set up RESP_MODE to non-copy addresses */ 699 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 700 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 701 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 702 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 703 704 /* program default cache read and write policy */ 705 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 706 /* clean read policy and write policy bits */ 707 temp &= 0xFF0FFF; 708 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 709 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 710 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 711 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 712 713 if (!amdgpu_sriov_vf(adev)) { 714 /* unhalt engine */ 715 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 716 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 717 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 718 } 719 720 /* enable DMA RB */ 721 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 722 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 723 724 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 725 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 726 #ifdef __BIG_ENDIAN 727 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 728 #endif 729 /* enable DMA IBs */ 730 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 731 732 ring->sched.ready = true; 733 734 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 735 sdma_v5_2_ctx_switch_enable(adev, true); 736 sdma_v5_2_enable(adev, true); 737 } 738 739 r = amdgpu_ring_test_ring(ring); 740 if (r) { 741 ring->sched.ready = false; 742 return r; 743 } 744 745 if (adev->mman.buffer_funcs_ring == ring) 746 amdgpu_ttm_set_buffer_funcs_status(adev, true); 747 } 748 749 return 0; 750 } 751 752 /** 753 * sdma_v5_2_rlc_resume - setup and start the async dma engines 754 * 755 * @adev: amdgpu_device pointer 756 * 757 * Set up the compute DMA queues and enable them. 758 * Returns 0 for success, error for failure. 759 */ 760 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) 761 { 762 return 0; 763 } 764 765 /** 766 * sdma_v5_2_load_microcode - load the sDMA ME ucode 767 * 768 * @adev: amdgpu_device pointer 769 * 770 * Loads the sDMA0/1/2/3 ucode. 771 * Returns 0 for success, -EINVAL if the ucode is not available. 772 */ 773 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) 774 { 775 const struct sdma_firmware_header_v1_0 *hdr; 776 const __le32 *fw_data; 777 u32 fw_size; 778 int i, j; 779 780 /* halt the MEs */ 781 sdma_v5_2_enable(adev, false); 782 783 for (i = 0; i < adev->sdma.num_instances; i++) { 784 if (!adev->sdma.instance[i].fw) 785 return -EINVAL; 786 787 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 788 amdgpu_ucode_print_sdma_hdr(&hdr->header); 789 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 790 791 fw_data = (const __le32 *) 792 (adev->sdma.instance[i].fw->data + 793 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 794 795 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 796 797 for (j = 0; j < fw_size; j++) { 798 if (amdgpu_emu_mode == 1 && j % 500 == 0) 799 msleep(1); 800 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 801 } 802 803 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 804 } 805 806 return 0; 807 } 808 809 static int sdma_v5_2_soft_reset(void *handle) 810 { 811 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 812 u32 grbm_soft_reset; 813 u32 tmp; 814 int i; 815 816 for (i = 0; i < adev->sdma.num_instances; i++) { 817 grbm_soft_reset = REG_SET_FIELD(0, 818 GRBM_SOFT_RESET, SOFT_RESET_SDMA0, 819 1); 820 grbm_soft_reset <<= i; 821 822 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 823 tmp |= grbm_soft_reset; 824 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp); 825 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 826 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 827 828 udelay(50); 829 830 tmp &= ~grbm_soft_reset; 831 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 832 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 833 834 udelay(50); 835 } 836 837 return 0; 838 } 839 840 /** 841 * sdma_v5_2_start - setup and start the async dma engines 842 * 843 * @adev: amdgpu_device pointer 844 * 845 * Set up the DMA engines and enable them. 846 * Returns 0 for success, error for failure. 847 */ 848 static int sdma_v5_2_start(struct amdgpu_device *adev) 849 { 850 int r = 0; 851 852 if (amdgpu_sriov_vf(adev)) { 853 sdma_v5_2_ctx_switch_enable(adev, false); 854 sdma_v5_2_enable(adev, false); 855 856 /* set RB registers */ 857 r = sdma_v5_2_gfx_resume(adev); 858 return r; 859 } 860 861 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 862 r = sdma_v5_2_load_microcode(adev); 863 if (r) 864 return r; 865 866 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 867 if (amdgpu_emu_mode == 1) 868 msleep(1000); 869 } 870 871 /* TODO: check whether can submit a doorbell request to raise 872 * a doorbell fence to exit gfxoff. 873 */ 874 if (adev->in_s0ix) 875 amdgpu_gfx_off_ctrl(adev, false); 876 877 sdma_v5_2_soft_reset(adev); 878 /* unhalt the MEs */ 879 sdma_v5_2_enable(adev, true); 880 /* enable sdma ring preemption */ 881 sdma_v5_2_ctx_switch_enable(adev, true); 882 883 /* start the gfx rings and rlc compute queues */ 884 r = sdma_v5_2_gfx_resume(adev); 885 if (adev->in_s0ix) 886 amdgpu_gfx_off_ctrl(adev, true); 887 if (r) 888 return r; 889 r = sdma_v5_2_rlc_resume(adev); 890 891 return r; 892 } 893 894 /** 895 * sdma_v5_2_ring_test_ring - simple async dma engine test 896 * 897 * @ring: amdgpu_ring structure holding ring information 898 * 899 * Test the DMA engine by writing using it to write an 900 * value to memory. 901 * Returns 0 for success, error for failure. 902 */ 903 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) 904 { 905 struct amdgpu_device *adev = ring->adev; 906 unsigned i; 907 unsigned index; 908 int r; 909 u32 tmp; 910 u64 gpu_addr; 911 912 r = amdgpu_device_wb_get(adev, &index); 913 if (r) { 914 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 915 return r; 916 } 917 918 gpu_addr = adev->wb.gpu_addr + (index * 4); 919 tmp = 0xCAFEDEAD; 920 adev->wb.wb[index] = cpu_to_le32(tmp); 921 922 r = amdgpu_ring_alloc(ring, 5); 923 if (r) { 924 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 925 amdgpu_device_wb_free(adev, index); 926 return r; 927 } 928 929 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 930 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 931 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 932 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 933 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 934 amdgpu_ring_write(ring, 0xDEADBEEF); 935 amdgpu_ring_commit(ring); 936 937 for (i = 0; i < adev->usec_timeout; i++) { 938 tmp = le32_to_cpu(adev->wb.wb[index]); 939 if (tmp == 0xDEADBEEF) 940 break; 941 if (amdgpu_emu_mode == 1) 942 msleep(1); 943 else 944 udelay(1); 945 } 946 947 if (i >= adev->usec_timeout) 948 r = -ETIMEDOUT; 949 950 amdgpu_device_wb_free(adev, index); 951 952 return r; 953 } 954 955 /** 956 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine 957 * 958 * @ring: amdgpu_ring structure holding ring information 959 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 960 * 961 * Test a simple IB in the DMA ring. 962 * Returns 0 on success, error on failure. 963 */ 964 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 965 { 966 struct amdgpu_device *adev = ring->adev; 967 struct amdgpu_ib ib; 968 struct dma_fence *f = NULL; 969 unsigned index; 970 long r; 971 u32 tmp = 0; 972 u64 gpu_addr; 973 974 r = amdgpu_device_wb_get(adev, &index); 975 if (r) { 976 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 977 return r; 978 } 979 980 gpu_addr = adev->wb.gpu_addr + (index * 4); 981 tmp = 0xCAFEDEAD; 982 adev->wb.wb[index] = cpu_to_le32(tmp); 983 memset(&ib, 0, sizeof(ib)); 984 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 985 if (r) { 986 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 987 goto err0; 988 } 989 990 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 991 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 992 ib.ptr[1] = lower_32_bits(gpu_addr); 993 ib.ptr[2] = upper_32_bits(gpu_addr); 994 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 995 ib.ptr[4] = 0xDEADBEEF; 996 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 997 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 998 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 999 ib.length_dw = 8; 1000 1001 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1002 if (r) 1003 goto err1; 1004 1005 r = dma_fence_wait_timeout(f, false, timeout); 1006 if (r == 0) { 1007 DRM_ERROR("amdgpu: IB test timed out\n"); 1008 r = -ETIMEDOUT; 1009 goto err1; 1010 } else if (r < 0) { 1011 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1012 goto err1; 1013 } 1014 tmp = le32_to_cpu(adev->wb.wb[index]); 1015 if (tmp == 0xDEADBEEF) 1016 r = 0; 1017 else 1018 r = -EINVAL; 1019 1020 err1: 1021 amdgpu_ib_free(adev, &ib, NULL); 1022 dma_fence_put(f); 1023 err0: 1024 amdgpu_device_wb_free(adev, index); 1025 return r; 1026 } 1027 1028 1029 /** 1030 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART 1031 * 1032 * @ib: indirect buffer to fill with commands 1033 * @pe: addr of the page entry 1034 * @src: src addr to copy from 1035 * @count: number of page entries to update 1036 * 1037 * Update PTEs by copying them from the GART using sDMA. 1038 */ 1039 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, 1040 uint64_t pe, uint64_t src, 1041 unsigned count) 1042 { 1043 unsigned bytes = count * 8; 1044 1045 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1046 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1047 ib->ptr[ib->length_dw++] = bytes - 1; 1048 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1049 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1050 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1051 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1052 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1053 1054 } 1055 1056 /** 1057 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually 1058 * 1059 * @ib: indirect buffer to fill with commands 1060 * @pe: addr of the page entry 1061 * @value: dst addr to write into pe 1062 * @count: number of page entries to update 1063 * @incr: increase next addr by incr bytes 1064 * 1065 * Update PTEs by writing them manually using sDMA. 1066 */ 1067 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1068 uint64_t value, unsigned count, 1069 uint32_t incr) 1070 { 1071 unsigned ndw = count * 2; 1072 1073 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1074 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1075 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1076 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1077 ib->ptr[ib->length_dw++] = ndw - 1; 1078 for (; ndw > 0; ndw -= 2) { 1079 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1080 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1081 value += incr; 1082 } 1083 } 1084 1085 /** 1086 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA 1087 * 1088 * @ib: indirect buffer to fill with commands 1089 * @pe: addr of the page entry 1090 * @addr: dst addr to write into pe 1091 * @count: number of page entries to update 1092 * @incr: increase next addr by incr bytes 1093 * @flags: access flags 1094 * 1095 * Update the page tables using sDMA. 1096 */ 1097 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1098 uint64_t pe, 1099 uint64_t addr, unsigned count, 1100 uint32_t incr, uint64_t flags) 1101 { 1102 /* for physically contiguous pages (vram) */ 1103 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1104 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1105 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1106 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1107 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1108 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1109 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1110 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1111 ib->ptr[ib->length_dw++] = 0; 1112 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1113 } 1114 1115 /** 1116 * sdma_v5_2_ring_pad_ib - pad the IB 1117 * 1118 * @ib: indirect buffer to fill with padding 1119 * @ring: amdgpu_ring structure holding ring information 1120 * 1121 * Pad the IB with NOPs to a boundary multiple of 8. 1122 */ 1123 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1124 { 1125 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1126 u32 pad_count; 1127 int i; 1128 1129 pad_count = (-ib->length_dw) & 0x7; 1130 for (i = 0; i < pad_count; i++) 1131 if (sdma && sdma->burst_nop && (i == 0)) 1132 ib->ptr[ib->length_dw++] = 1133 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1134 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1135 else 1136 ib->ptr[ib->length_dw++] = 1137 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1138 } 1139 1140 1141 /** 1142 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline 1143 * 1144 * @ring: amdgpu_ring pointer 1145 * 1146 * Make sure all previous operations are completed (CIK). 1147 */ 1148 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1149 { 1150 uint32_t seq = ring->fence_drv.sync_seq; 1151 uint64_t addr = ring->fence_drv.gpu_addr; 1152 1153 /* wait for idle */ 1154 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1155 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1156 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1157 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1158 amdgpu_ring_write(ring, addr & 0xfffffffc); 1159 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1160 amdgpu_ring_write(ring, seq); /* reference */ 1161 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1162 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1163 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1164 } 1165 1166 1167 /** 1168 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA 1169 * 1170 * @ring: amdgpu_ring pointer 1171 * @vmid: vmid number to use 1172 * @pd_addr: address 1173 * 1174 * Update the page table base and flush the VM TLB 1175 * using sDMA. 1176 */ 1177 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1178 unsigned vmid, uint64_t pd_addr) 1179 { 1180 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1181 } 1182 1183 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, 1184 uint32_t reg, uint32_t val) 1185 { 1186 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1187 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1188 amdgpu_ring_write(ring, reg); 1189 amdgpu_ring_write(ring, val); 1190 } 1191 1192 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1193 uint32_t val, uint32_t mask) 1194 { 1195 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1196 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1197 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1198 amdgpu_ring_write(ring, reg << 2); 1199 amdgpu_ring_write(ring, 0); 1200 amdgpu_ring_write(ring, val); /* reference */ 1201 amdgpu_ring_write(ring, mask); /* mask */ 1202 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1203 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1204 } 1205 1206 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1207 uint32_t reg0, uint32_t reg1, 1208 uint32_t ref, uint32_t mask) 1209 { 1210 amdgpu_ring_emit_wreg(ring, reg0, ref); 1211 /* wait for a cycle to reset vm_inv_eng*_ack */ 1212 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1213 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1214 } 1215 1216 static int sdma_v5_2_early_init(void *handle) 1217 { 1218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1219 1220 sdma_v5_2_set_ring_funcs(adev); 1221 sdma_v5_2_set_buffer_funcs(adev); 1222 sdma_v5_2_set_vm_pte_funcs(adev); 1223 sdma_v5_2_set_irq_funcs(adev); 1224 1225 return 0; 1226 } 1227 1228 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) 1229 { 1230 switch (seq_num) { 1231 case 0: 1232 return SOC15_IH_CLIENTID_SDMA0; 1233 case 1: 1234 return SOC15_IH_CLIENTID_SDMA1; 1235 case 2: 1236 return SOC15_IH_CLIENTID_SDMA2; 1237 case 3: 1238 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; 1239 default: 1240 break; 1241 } 1242 return -EINVAL; 1243 } 1244 1245 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) 1246 { 1247 switch (seq_num) { 1248 case 0: 1249 return SDMA0_5_0__SRCID__SDMA_TRAP; 1250 case 1: 1251 return SDMA1_5_0__SRCID__SDMA_TRAP; 1252 case 2: 1253 return SDMA2_5_0__SRCID__SDMA_TRAP; 1254 case 3: 1255 return SDMA3_5_0__SRCID__SDMA_TRAP; 1256 default: 1257 break; 1258 } 1259 return -EINVAL; 1260 } 1261 1262 static int sdma_v5_2_sw_init(void *handle) 1263 { 1264 struct amdgpu_ring *ring; 1265 int r, i; 1266 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1267 1268 /* SDMA trap event */ 1269 for (i = 0; i < adev->sdma.num_instances; i++) { 1270 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), 1271 sdma_v5_2_seq_to_trap_id(i), 1272 &adev->sdma.trap_irq); 1273 if (r) 1274 return r; 1275 } 1276 1277 r = sdma_v5_2_init_microcode(adev); 1278 if (r) { 1279 DRM_ERROR("Failed to load sdma firmware!\n"); 1280 return r; 1281 } 1282 1283 for (i = 0; i < adev->sdma.num_instances; i++) { 1284 ring = &adev->sdma.instance[i].ring; 1285 ring->ring_obj = NULL; 1286 ring->use_doorbell = true; 1287 ring->me = i; 1288 1289 DRM_INFO("use_doorbell being set to: [%s]\n", 1290 ring->use_doorbell?"true":"false"); 1291 1292 ring->doorbell_index = 1293 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1294 1295 sprintf(ring->name, "sdma%d", i); 1296 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1297 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1298 AMDGPU_RING_PRIO_DEFAULT, NULL); 1299 if (r) 1300 return r; 1301 } 1302 1303 return r; 1304 } 1305 1306 static int sdma_v5_2_sw_fini(void *handle) 1307 { 1308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1309 int i; 1310 1311 for (i = 0; i < adev->sdma.num_instances; i++) 1312 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1313 1314 sdma_v5_2_destroy_inst_ctx(adev); 1315 1316 return 0; 1317 } 1318 1319 static int sdma_v5_2_hw_init(void *handle) 1320 { 1321 int r; 1322 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1323 1324 r = sdma_v5_2_start(adev); 1325 1326 return r; 1327 } 1328 1329 static int sdma_v5_2_hw_fini(void *handle) 1330 { 1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1332 1333 if (amdgpu_sriov_vf(adev)) 1334 return 0; 1335 1336 sdma_v5_2_ctx_switch_enable(adev, false); 1337 sdma_v5_2_enable(adev, false); 1338 1339 return 0; 1340 } 1341 1342 static int sdma_v5_2_suspend(void *handle) 1343 { 1344 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1345 1346 return sdma_v5_2_hw_fini(adev); 1347 } 1348 1349 static int sdma_v5_2_resume(void *handle) 1350 { 1351 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1352 1353 return sdma_v5_2_hw_init(adev); 1354 } 1355 1356 static bool sdma_v5_2_is_idle(void *handle) 1357 { 1358 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1359 u32 i; 1360 1361 for (i = 0; i < adev->sdma.num_instances; i++) { 1362 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1363 1364 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1365 return false; 1366 } 1367 1368 return true; 1369 } 1370 1371 static int sdma_v5_2_wait_for_idle(void *handle) 1372 { 1373 unsigned i; 1374 u32 sdma0, sdma1, sdma2, sdma3; 1375 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1376 1377 for (i = 0; i < adev->usec_timeout; i++) { 1378 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1379 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1380 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); 1381 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); 1382 1383 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK) 1384 return 0; 1385 udelay(1); 1386 } 1387 return -ETIMEDOUT; 1388 } 1389 1390 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) 1391 { 1392 int i, r = 0; 1393 struct amdgpu_device *adev = ring->adev; 1394 u32 index = 0; 1395 u64 sdma_gfx_preempt; 1396 1397 amdgpu_sdma_get_index_from_ring(ring, &index); 1398 sdma_gfx_preempt = 1399 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT); 1400 1401 /* assert preemption condition */ 1402 amdgpu_ring_set_preempt_cond_exec(ring, false); 1403 1404 /* emit the trailing fence */ 1405 ring->trail_seq += 1; 1406 amdgpu_ring_alloc(ring, 10); 1407 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1408 ring->trail_seq, 0); 1409 amdgpu_ring_commit(ring); 1410 1411 /* assert IB preemption */ 1412 WREG32(sdma_gfx_preempt, 1); 1413 1414 /* poll the trailing fence */ 1415 for (i = 0; i < adev->usec_timeout; i++) { 1416 if (ring->trail_seq == 1417 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1418 break; 1419 udelay(1); 1420 } 1421 1422 if (i >= adev->usec_timeout) { 1423 r = -EINVAL; 1424 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1425 } 1426 1427 /* deassert IB preemption */ 1428 WREG32(sdma_gfx_preempt, 0); 1429 1430 /* deassert the preemption condition */ 1431 amdgpu_ring_set_preempt_cond_exec(ring, true); 1432 return r; 1433 } 1434 1435 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, 1436 struct amdgpu_irq_src *source, 1437 unsigned type, 1438 enum amdgpu_interrupt_state state) 1439 { 1440 u32 sdma_cntl; 1441 1442 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); 1443 1444 sdma_cntl = RREG32(reg_offset); 1445 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1446 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1447 WREG32(reg_offset, sdma_cntl); 1448 1449 return 0; 1450 } 1451 1452 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, 1453 struct amdgpu_irq_src *source, 1454 struct amdgpu_iv_entry *entry) 1455 { 1456 DRM_DEBUG("IH: SDMA trap\n"); 1457 switch (entry->client_id) { 1458 case SOC15_IH_CLIENTID_SDMA0: 1459 switch (entry->ring_id) { 1460 case 0: 1461 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1462 break; 1463 case 1: 1464 /* XXX compute */ 1465 break; 1466 case 2: 1467 /* XXX compute */ 1468 break; 1469 case 3: 1470 /* XXX page queue*/ 1471 break; 1472 } 1473 break; 1474 case SOC15_IH_CLIENTID_SDMA1: 1475 switch (entry->ring_id) { 1476 case 0: 1477 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1478 break; 1479 case 1: 1480 /* XXX compute */ 1481 break; 1482 case 2: 1483 /* XXX compute */ 1484 break; 1485 case 3: 1486 /* XXX page queue*/ 1487 break; 1488 } 1489 break; 1490 case SOC15_IH_CLIENTID_SDMA2: 1491 switch (entry->ring_id) { 1492 case 0: 1493 amdgpu_fence_process(&adev->sdma.instance[2].ring); 1494 break; 1495 case 1: 1496 /* XXX compute */ 1497 break; 1498 case 2: 1499 /* XXX compute */ 1500 break; 1501 case 3: 1502 /* XXX page queue*/ 1503 break; 1504 } 1505 break; 1506 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: 1507 switch (entry->ring_id) { 1508 case 0: 1509 amdgpu_fence_process(&adev->sdma.instance[3].ring); 1510 break; 1511 case 1: 1512 /* XXX compute */ 1513 break; 1514 case 2: 1515 /* XXX compute */ 1516 break; 1517 case 3: 1518 /* XXX page queue*/ 1519 break; 1520 } 1521 break; 1522 } 1523 return 0; 1524 } 1525 1526 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1527 struct amdgpu_irq_src *source, 1528 struct amdgpu_iv_entry *entry) 1529 { 1530 return 0; 1531 } 1532 1533 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1534 bool enable) 1535 { 1536 uint32_t data, def; 1537 int i; 1538 1539 for (i = 0; i < adev->sdma.num_instances; i++) { 1540 1541 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1)) 1542 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG; 1543 1544 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1545 /* Enable sdma clock gating */ 1546 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1547 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1548 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1549 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1550 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1551 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1552 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1553 if (def != data) 1554 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1555 } else { 1556 /* Disable sdma clock gating */ 1557 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1558 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1559 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1560 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1561 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1562 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1563 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1564 if (def != data) 1565 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1566 } 1567 } 1568 } 1569 1570 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1571 bool enable) 1572 { 1573 uint32_t data, def; 1574 int i; 1575 1576 for (i = 0; i < adev->sdma.num_instances; i++) { 1577 1578 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1)) 1579 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS; 1580 1581 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1582 /* Enable sdma mem light sleep */ 1583 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1584 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1585 if (def != data) 1586 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1587 1588 } else { 1589 /* Disable sdma mem light sleep */ 1590 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1591 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1592 if (def != data) 1593 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1594 1595 } 1596 } 1597 } 1598 1599 static int sdma_v5_2_set_clockgating_state(void *handle, 1600 enum amd_clockgating_state state) 1601 { 1602 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1603 1604 if (amdgpu_sriov_vf(adev)) 1605 return 0; 1606 1607 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1608 case IP_VERSION(5, 2, 0): 1609 case IP_VERSION(5, 2, 2): 1610 case IP_VERSION(5, 2, 1): 1611 case IP_VERSION(5, 2, 4): 1612 case IP_VERSION(5, 2, 5): 1613 case IP_VERSION(5, 2, 3): 1614 sdma_v5_2_update_medium_grain_clock_gating(adev, 1615 state == AMD_CG_STATE_GATE); 1616 sdma_v5_2_update_medium_grain_light_sleep(adev, 1617 state == AMD_CG_STATE_GATE); 1618 break; 1619 default: 1620 break; 1621 } 1622 1623 return 0; 1624 } 1625 1626 static int sdma_v5_2_set_powergating_state(void *handle, 1627 enum amd_powergating_state state) 1628 { 1629 return 0; 1630 } 1631 1632 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags) 1633 { 1634 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1635 int data; 1636 1637 if (amdgpu_sriov_vf(adev)) 1638 *flags = 0; 1639 1640 /* AMD_CG_SUPPORT_SDMA_LS */ 1641 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1642 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1643 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1644 } 1645 1646 const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1647 .name = "sdma_v5_2", 1648 .early_init = sdma_v5_2_early_init, 1649 .late_init = NULL, 1650 .sw_init = sdma_v5_2_sw_init, 1651 .sw_fini = sdma_v5_2_sw_fini, 1652 .hw_init = sdma_v5_2_hw_init, 1653 .hw_fini = sdma_v5_2_hw_fini, 1654 .suspend = sdma_v5_2_suspend, 1655 .resume = sdma_v5_2_resume, 1656 .is_idle = sdma_v5_2_is_idle, 1657 .wait_for_idle = sdma_v5_2_wait_for_idle, 1658 .soft_reset = sdma_v5_2_soft_reset, 1659 .set_clockgating_state = sdma_v5_2_set_clockgating_state, 1660 .set_powergating_state = sdma_v5_2_set_powergating_state, 1661 .get_clockgating_state = sdma_v5_2_get_clockgating_state, 1662 }; 1663 1664 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 1665 .type = AMDGPU_RING_TYPE_SDMA, 1666 .align_mask = 0xf, 1667 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1668 .support_64bit_ptrs = true, 1669 .vmhub = AMDGPU_GFXHUB_0, 1670 .get_rptr = sdma_v5_2_ring_get_rptr, 1671 .get_wptr = sdma_v5_2_ring_get_wptr, 1672 .set_wptr = sdma_v5_2_ring_set_wptr, 1673 .emit_frame_size = 1674 5 + /* sdma_v5_2_ring_init_cond_exec */ 1675 6 + /* sdma_v5_2_ring_emit_hdp_flush */ 1676 3 + /* hdp_invalidate */ 1677 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ 1678 /* sdma_v5_2_ring_emit_vm_flush */ 1679 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1680 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1681 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ 1682 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ 1683 .emit_ib = sdma_v5_2_ring_emit_ib, 1684 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync, 1685 .emit_fence = sdma_v5_2_ring_emit_fence, 1686 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, 1687 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, 1688 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, 1689 .test_ring = sdma_v5_2_ring_test_ring, 1690 .test_ib = sdma_v5_2_ring_test_ib, 1691 .insert_nop = sdma_v5_2_ring_insert_nop, 1692 .pad_ib = sdma_v5_2_ring_pad_ib, 1693 .emit_wreg = sdma_v5_2_ring_emit_wreg, 1694 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, 1695 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, 1696 .init_cond_exec = sdma_v5_2_ring_init_cond_exec, 1697 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec, 1698 .preempt_ib = sdma_v5_2_ring_preempt_ib, 1699 }; 1700 1701 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) 1702 { 1703 int i; 1704 1705 for (i = 0; i < adev->sdma.num_instances; i++) { 1706 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; 1707 adev->sdma.instance[i].ring.me = i; 1708 } 1709 } 1710 1711 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { 1712 .set = sdma_v5_2_set_trap_irq_state, 1713 .process = sdma_v5_2_process_trap_irq, 1714 }; 1715 1716 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { 1717 .process = sdma_v5_2_process_illegal_inst_irq, 1718 }; 1719 1720 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) 1721 { 1722 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1723 adev->sdma.num_instances; 1724 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; 1725 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; 1726 } 1727 1728 /** 1729 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine 1730 * 1731 * @ib: indirect buffer to copy to 1732 * @src_offset: src GPU address 1733 * @dst_offset: dst GPU address 1734 * @byte_count: number of bytes to xfer 1735 * @tmz: if a secure copy should be used 1736 * 1737 * Copy GPU buffers using the DMA engine. 1738 * Used by the amdgpu ttm implementation to move pages if 1739 * registered as the asic copy callback. 1740 */ 1741 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, 1742 uint64_t src_offset, 1743 uint64_t dst_offset, 1744 uint32_t byte_count, 1745 bool tmz) 1746 { 1747 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1748 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1749 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1750 ib->ptr[ib->length_dw++] = byte_count - 1; 1751 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1752 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1753 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1754 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1755 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1756 } 1757 1758 /** 1759 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine 1760 * 1761 * @ib: indirect buffer to fill 1762 * @src_data: value to write to buffer 1763 * @dst_offset: dst GPU address 1764 * @byte_count: number of bytes to xfer 1765 * 1766 * Fill GPU buffers using the DMA engine. 1767 */ 1768 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, 1769 uint32_t src_data, 1770 uint64_t dst_offset, 1771 uint32_t byte_count) 1772 { 1773 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1774 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1775 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1776 ib->ptr[ib->length_dw++] = src_data; 1777 ib->ptr[ib->length_dw++] = byte_count - 1; 1778 } 1779 1780 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { 1781 .copy_max_bytes = 0x400000, 1782 .copy_num_dw = 7, 1783 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, 1784 1785 .fill_max_bytes = 0x400000, 1786 .fill_num_dw = 5, 1787 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, 1788 }; 1789 1790 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) 1791 { 1792 if (adev->mman.buffer_funcs == NULL) { 1793 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 1794 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1795 } 1796 } 1797 1798 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 1799 .copy_pte_num_dw = 7, 1800 .copy_pte = sdma_v5_2_vm_copy_pte, 1801 .write_pte = sdma_v5_2_vm_write_pte, 1802 .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 1803 }; 1804 1805 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 1806 { 1807 unsigned i; 1808 1809 if (adev->vm_manager.vm_pte_funcs == NULL) { 1810 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 1811 for (i = 0; i < adev->sdma.num_instances; i++) { 1812 adev->vm_manager.vm_pte_scheds[i] = 1813 &adev->sdma.instance[i].ring.sched; 1814 } 1815 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1816 } 1817 } 1818 1819 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { 1820 .type = AMD_IP_BLOCK_TYPE_SDMA, 1821 .major = 5, 1822 .minor = 2, 1823 .rev = 0, 1824 .funcs = &sdma_v5_2_ip_funcs, 1825 }; 1826