1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_3_0_offset.h" 34 #include "gc/gc_10_3_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" 38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "navi10_sdma_pkt_open.h" 43 #include "nbio_v2_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v5_2.h" 46 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); 50 51 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); 52 53 #define SDMA1_REG_OFFSET 0x600 54 #define SDMA3_REG_OFFSET 0x400 55 #define SDMA0_HYP_DEC_REG_START 0x5880 56 #define SDMA0_HYP_DEC_REG_END 0x5893 57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 58 59 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 60 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 61 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 62 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 63 64 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 65 { 66 u32 base; 67 68 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 69 internal_offset <= SDMA0_HYP_DEC_REG_END) { 70 base = adev->reg_offset[GC_HWIP][0][1]; 71 if (instance != 0) 72 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 73 } else { 74 if (instance < 2) { 75 base = adev->reg_offset[GC_HWIP][0][0]; 76 if (instance == 1) 77 internal_offset += SDMA1_REG_OFFSET; 78 } else { 79 base = adev->reg_offset[GC_HWIP][0][2]; 80 if (instance == 3) 81 internal_offset += SDMA3_REG_OFFSET; 82 } 83 } 84 85 return base + internal_offset; 86 } 87 88 static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev) 89 { 90 switch (adev->asic_type) { 91 case CHIP_SIENNA_CICHLID: 92 case CHIP_NAVY_FLOUNDER: 93 case CHIP_VANGOGH: 94 case CHIP_DIMGREY_CAVEFISH: 95 break; 96 default: 97 break; 98 } 99 } 100 101 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 102 { 103 int err = 0; 104 const struct sdma_firmware_header_v1_0 *hdr; 105 106 err = amdgpu_ucode_validate(sdma_inst->fw); 107 if (err) 108 return err; 109 110 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 111 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 112 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 113 114 if (sdma_inst->feature_version >= 20) 115 sdma_inst->burst_nop = true; 116 117 return 0; 118 } 119 120 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev) 121 { 122 int i; 123 124 for (i = 0; i < adev->sdma.num_instances; i++) { 125 release_firmware(adev->sdma.instance[i].fw); 126 adev->sdma.instance[i].fw = NULL; 127 128 if (adev->asic_type == CHIP_SIENNA_CICHLID) 129 break; 130 } 131 132 memset((void *)adev->sdma.instance, 0, 133 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 134 } 135 136 /** 137 * sdma_v5_2_init_microcode - load ucode images from disk 138 * 139 * @adev: amdgpu_device pointer 140 * 141 * Use the firmware interface to load the ucode images into 142 * the driver (not loaded into hw). 143 * Returns 0 on success, error on failure. 144 */ 145 146 // emulation only, won't work on real chip 147 // navi10 real chip need to use PSP to load firmware 148 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) 149 { 150 const char *chip_name; 151 char fw_name[40]; 152 int err = 0, i; 153 struct amdgpu_firmware_info *info = NULL; 154 const struct common_firmware_header *header = NULL; 155 156 DRM_DEBUG("\n"); 157 158 switch (adev->asic_type) { 159 case CHIP_SIENNA_CICHLID: 160 chip_name = "sienna_cichlid"; 161 break; 162 case CHIP_NAVY_FLOUNDER: 163 chip_name = "navy_flounder"; 164 break; 165 case CHIP_VANGOGH: 166 chip_name = "vangogh"; 167 break; 168 case CHIP_DIMGREY_CAVEFISH: 169 chip_name = "dimgrey_cavefish"; 170 break; 171 default: 172 BUG(); 173 } 174 175 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 176 177 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 178 if (err) 179 goto out; 180 181 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]); 182 if (err) 183 goto out; 184 185 for (i = 1; i < adev->sdma.num_instances; i++) { 186 if (adev->asic_type >= CHIP_SIENNA_CICHLID && 187 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) { 188 memcpy((void *)&adev->sdma.instance[i], 189 (void *)&adev->sdma.instance[0], 190 sizeof(struct amdgpu_sdma_instance)); 191 } else { 192 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 193 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 194 if (err) 195 goto out; 196 197 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]); 198 if (err) 199 goto out; 200 } 201 } 202 203 DRM_DEBUG("psp_load == '%s'\n", 204 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 205 206 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 207 for (i = 0; i < adev->sdma.num_instances; i++) { 208 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 209 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 210 info->fw = adev->sdma.instance[i].fw; 211 header = (const struct common_firmware_header *)info->fw->data; 212 adev->firmware.fw_size += 213 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 214 } 215 } 216 217 out: 218 if (err) { 219 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name); 220 sdma_v5_2_destroy_inst_ctx(adev); 221 } 222 return err; 223 } 224 225 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) 226 { 227 unsigned ret; 228 229 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 230 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 231 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 232 amdgpu_ring_write(ring, 1); 233 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 234 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 235 236 return ret; 237 } 238 239 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring, 240 unsigned offset) 241 { 242 unsigned cur; 243 244 BUG_ON(offset > ring->buf_mask); 245 BUG_ON(ring->ring[offset] != 0x55aa55aa); 246 247 cur = (ring->wptr - 1) & ring->buf_mask; 248 if (cur > offset) 249 ring->ring[offset] = cur - offset; 250 else 251 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 252 } 253 254 /** 255 * sdma_v5_2_ring_get_rptr - get the current read pointer 256 * 257 * @ring: amdgpu ring pointer 258 * 259 * Get the current rptr from the hardware (NAVI10+). 260 */ 261 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) 262 { 263 u64 *rptr; 264 265 /* XXX check if swapping is necessary on BE */ 266 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 267 268 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 269 return ((*rptr) >> 2); 270 } 271 272 /** 273 * sdma_v5_2_ring_get_wptr - get the current write pointer 274 * 275 * @ring: amdgpu ring pointer 276 * 277 * Get the current wptr from the hardware (NAVI10+). 278 */ 279 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) 280 { 281 struct amdgpu_device *adev = ring->adev; 282 u64 wptr; 283 284 if (ring->use_doorbell) { 285 /* XXX check if swapping is necessary on BE */ 286 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 287 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 288 } else { 289 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 290 wptr = wptr << 32; 291 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 292 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 293 } 294 295 return wptr >> 2; 296 } 297 298 /** 299 * sdma_v5_2_ring_set_wptr - commit the write pointer 300 * 301 * @ring: amdgpu ring pointer 302 * 303 * Write the wptr back to the hardware (NAVI10+). 304 */ 305 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) 306 { 307 struct amdgpu_device *adev = ring->adev; 308 309 DRM_DEBUG("Setting write pointer\n"); 310 if (ring->use_doorbell) { 311 DRM_DEBUG("Using doorbell -- " 312 "wptr_offs == 0x%08x " 313 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 314 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 315 ring->wptr_offs, 316 lower_32_bits(ring->wptr << 2), 317 upper_32_bits(ring->wptr << 2)); 318 /* XXX check if swapping is necessary on BE */ 319 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 320 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 321 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 322 ring->doorbell_index, ring->wptr << 2); 323 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 324 } else { 325 DRM_DEBUG("Not using doorbell -- " 326 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 327 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 328 ring->me, 329 lower_32_bits(ring->wptr << 2), 330 ring->me, 331 upper_32_bits(ring->wptr << 2)); 332 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 333 lower_32_bits(ring->wptr << 2)); 334 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 335 upper_32_bits(ring->wptr << 2)); 336 } 337 } 338 339 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 340 { 341 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 342 int i; 343 344 for (i = 0; i < count; i++) 345 if (sdma && sdma->burst_nop && (i == 0)) 346 amdgpu_ring_write(ring, ring->funcs->nop | 347 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 348 else 349 amdgpu_ring_write(ring, ring->funcs->nop); 350 } 351 352 /** 353 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine 354 * 355 * @ring: amdgpu ring pointer 356 * @ib: IB object to schedule 357 * 358 * Schedule an IB in the DMA ring. 359 */ 360 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, 361 struct amdgpu_job *job, 362 struct amdgpu_ib *ib, 363 uint32_t flags) 364 { 365 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 366 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 367 368 /* An IB packet must end on a 8 DW boundary--the next dword 369 * must be on a 8-dword boundary. Our IB packet below is 6 370 * dwords long, thus add x number of NOPs, such that, in 371 * modular arithmetic, 372 * wptr + 6 + x = 8k, k >= 0, which in C is, 373 * (wptr + 6 + x) % 8 = 0. 374 * The expression below, is a solution of x. 375 */ 376 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 377 378 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 379 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 380 /* base must be 32 byte aligned */ 381 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 382 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 383 amdgpu_ring_write(ring, ib->length_dw); 384 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 385 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 386 } 387 388 /** 389 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 390 * 391 * @ring: amdgpu ring pointer 392 * 393 * Emit an hdp flush packet on the requested DMA ring. 394 */ 395 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 396 { 397 struct amdgpu_device *adev = ring->adev; 398 u32 ref_and_mask = 0; 399 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 400 401 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 402 403 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 404 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 405 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 406 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 407 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 408 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 409 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 410 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 411 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 412 } 413 414 /** 415 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring 416 * 417 * @ring: amdgpu ring pointer 418 * @fence: amdgpu fence object 419 * 420 * Add a DMA fence packet to the ring to write 421 * the fence seq number and DMA trap packet to generate 422 * an interrupt if needed. 423 */ 424 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 425 unsigned flags) 426 { 427 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 428 /* write the fence */ 429 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 430 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 431 /* zero in first two bits */ 432 BUG_ON(addr & 0x3); 433 amdgpu_ring_write(ring, lower_32_bits(addr)); 434 amdgpu_ring_write(ring, upper_32_bits(addr)); 435 amdgpu_ring_write(ring, lower_32_bits(seq)); 436 437 /* optionally write high bits as well */ 438 if (write64bit) { 439 addr += 4; 440 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 441 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 442 /* zero in first two bits */ 443 BUG_ON(addr & 0x3); 444 amdgpu_ring_write(ring, lower_32_bits(addr)); 445 amdgpu_ring_write(ring, upper_32_bits(addr)); 446 amdgpu_ring_write(ring, upper_32_bits(seq)); 447 } 448 449 if (flags & AMDGPU_FENCE_FLAG_INT) { 450 /* generate an interrupt */ 451 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 452 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 453 } 454 } 455 456 457 /** 458 * sdma_v5_2_gfx_stop - stop the gfx async dma engines 459 * 460 * @adev: amdgpu_device pointer 461 * 462 * Stop the gfx async dma ring buffers. 463 */ 464 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) 465 { 466 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 467 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 468 struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring; 469 struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring; 470 u32 rb_cntl, ib_cntl; 471 int i; 472 473 if ((adev->mman.buffer_funcs_ring == sdma0) || 474 (adev->mman.buffer_funcs_ring == sdma1) || 475 (adev->mman.buffer_funcs_ring == sdma2) || 476 (adev->mman.buffer_funcs_ring == sdma3)) 477 amdgpu_ttm_set_buffer_funcs_status(adev, false); 478 479 for (i = 0; i < adev->sdma.num_instances; i++) { 480 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 481 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 482 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 483 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 484 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 485 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 486 } 487 488 sdma0->sched.ready = false; 489 sdma1->sched.ready = false; 490 sdma2->sched.ready = false; 491 sdma3->sched.ready = false; 492 } 493 494 /** 495 * sdma_v5_2_rlc_stop - stop the compute async dma engines 496 * 497 * @adev: amdgpu_device pointer 498 * 499 * Stop the compute async dma queues. 500 */ 501 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) 502 { 503 /* XXX todo */ 504 } 505 506 /** 507 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 508 * 509 * @adev: amdgpu_device pointer 510 * @enable: enable/disable the DMA MEs context switch. 511 * 512 * Halt or unhalt the async dma engines context switch. 513 */ 514 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 515 { 516 u32 f32_cntl, phase_quantum = 0; 517 int i; 518 519 if (amdgpu_sdma_phase_quantum) { 520 unsigned value = amdgpu_sdma_phase_quantum; 521 unsigned unit = 0; 522 523 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 524 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 525 value = (value + 1) >> 1; 526 unit++; 527 } 528 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 529 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 530 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 531 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 532 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 533 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 534 WARN_ONCE(1, 535 "clamping sdma_phase_quantum to %uK clock cycles\n", 536 value << unit); 537 } 538 phase_quantum = 539 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 540 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 541 } 542 543 for (i = 0; i < adev->sdma.num_instances; i++) { 544 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 545 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 546 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 547 if (enable && amdgpu_sdma_phase_quantum) { 548 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 549 phase_quantum); 550 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 551 phase_quantum); 552 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 553 phase_quantum); 554 } 555 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 556 } 557 558 } 559 560 /** 561 * sdma_v5_2_enable - stop the async dma engines 562 * 563 * @adev: amdgpu_device pointer 564 * @enable: enable/disable the DMA MEs. 565 * 566 * Halt or unhalt the async dma engines. 567 */ 568 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) 569 { 570 u32 f32_cntl; 571 int i; 572 573 if (!enable) { 574 sdma_v5_2_gfx_stop(adev); 575 sdma_v5_2_rlc_stop(adev); 576 } 577 578 for (i = 0; i < adev->sdma.num_instances; i++) { 579 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 580 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 581 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 582 } 583 } 584 585 /** 586 * sdma_v5_2_gfx_resume - setup and start the async dma engines 587 * 588 * @adev: amdgpu_device pointer 589 * 590 * Set up the gfx DMA ring buffers and enable them. 591 * Returns 0 for success, error for failure. 592 */ 593 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 594 { 595 struct amdgpu_ring *ring; 596 u32 rb_cntl, ib_cntl; 597 u32 rb_bufsz; 598 u32 wb_offset; 599 u32 doorbell; 600 u32 doorbell_offset; 601 u32 temp; 602 u32 wptr_poll_cntl; 603 u64 wptr_gpu_addr; 604 int i, r; 605 606 for (i = 0; i < adev->sdma.num_instances; i++) { 607 ring = &adev->sdma.instance[i].ring; 608 wb_offset = (ring->rptr_offs * 4); 609 610 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 611 612 /* Set ring buffer size in dwords */ 613 rb_bufsz = order_base_2(ring->ring_size / 4); 614 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 615 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 616 #ifdef __BIG_ENDIAN 617 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 618 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 619 RPTR_WRITEBACK_SWAP_ENABLE, 1); 620 #endif 621 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 622 623 /* Initialize the ring buffer's read and write pointers */ 624 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 625 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 626 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 627 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 628 629 /* setup the wptr shadow polling */ 630 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 631 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 632 lower_32_bits(wptr_gpu_addr)); 633 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 634 upper_32_bits(wptr_gpu_addr)); 635 wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, 636 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 637 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 638 SDMA0_GFX_RB_WPTR_POLL_CNTL, 639 F32_POLL_ENABLE, 1); 640 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 641 wptr_poll_cntl); 642 643 /* set the wb address whether it's enabled or not */ 644 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 645 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 646 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 647 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 648 649 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 650 651 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 652 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 653 654 ring->wptr = 0; 655 656 /* before programing wptr to a less value, need set minor_ptr_update first */ 657 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 658 659 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 660 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 661 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 662 } 663 664 doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 665 doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 666 667 if (ring->use_doorbell) { 668 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 669 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 670 OFFSET, ring->doorbell_index); 671 } else { 672 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 673 } 674 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 675 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 676 677 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 678 ring->doorbell_index, 679 adev->doorbell_index.sdma_doorbell_range); 680 681 if (amdgpu_sriov_vf(adev)) 682 sdma_v5_2_ring_set_wptr(ring); 683 684 /* set minor_ptr_update to 0 after wptr programed */ 685 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 686 687 /* set utc l1 enable flag always to 1 */ 688 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 689 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 690 691 /* enable MCBP */ 692 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 693 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 694 695 /* Set up RESP_MODE to non-copy addresses */ 696 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 697 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 698 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 699 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 700 701 /* program default cache read and write policy */ 702 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 703 /* clean read policy and write policy bits */ 704 temp &= 0xFF0FFF; 705 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 706 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 707 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 708 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 709 710 if (!amdgpu_sriov_vf(adev)) { 711 /* unhalt engine */ 712 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 713 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 714 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 715 } 716 717 /* enable DMA RB */ 718 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 719 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 720 721 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 722 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 723 #ifdef __BIG_ENDIAN 724 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 725 #endif 726 /* enable DMA IBs */ 727 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 728 729 ring->sched.ready = true; 730 731 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 732 sdma_v5_2_ctx_switch_enable(adev, true); 733 sdma_v5_2_enable(adev, true); 734 } 735 736 r = amdgpu_ring_test_ring(ring); 737 if (r) { 738 ring->sched.ready = false; 739 return r; 740 } 741 742 if (adev->mman.buffer_funcs_ring == ring) 743 amdgpu_ttm_set_buffer_funcs_status(adev, true); 744 } 745 746 return 0; 747 } 748 749 /** 750 * sdma_v5_2_rlc_resume - setup and start the async dma engines 751 * 752 * @adev: amdgpu_device pointer 753 * 754 * Set up the compute DMA queues and enable them. 755 * Returns 0 for success, error for failure. 756 */ 757 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) 758 { 759 return 0; 760 } 761 762 /** 763 * sdma_v5_2_load_microcode - load the sDMA ME ucode 764 * 765 * @adev: amdgpu_device pointer 766 * 767 * Loads the sDMA0/1/2/3 ucode. 768 * Returns 0 for success, -EINVAL if the ucode is not available. 769 */ 770 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) 771 { 772 const struct sdma_firmware_header_v1_0 *hdr; 773 const __le32 *fw_data; 774 u32 fw_size; 775 int i, j; 776 777 /* halt the MEs */ 778 sdma_v5_2_enable(adev, false); 779 780 for (i = 0; i < adev->sdma.num_instances; i++) { 781 if (!adev->sdma.instance[i].fw) 782 return -EINVAL; 783 784 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 785 amdgpu_ucode_print_sdma_hdr(&hdr->header); 786 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 787 788 fw_data = (const __le32 *) 789 (adev->sdma.instance[i].fw->data + 790 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 791 792 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 793 794 for (j = 0; j < fw_size; j++) { 795 if (amdgpu_emu_mode == 1 && j % 500 == 0) 796 msleep(1); 797 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 798 } 799 800 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 801 } 802 803 return 0; 804 } 805 806 /** 807 * sdma_v5_2_start - setup and start the async dma engines 808 * 809 * @adev: amdgpu_device pointer 810 * 811 * Set up the DMA engines and enable them. 812 * Returns 0 for success, error for failure. 813 */ 814 static int sdma_v5_2_start(struct amdgpu_device *adev) 815 { 816 int r = 0; 817 818 if (amdgpu_sriov_vf(adev)) { 819 sdma_v5_2_ctx_switch_enable(adev, false); 820 sdma_v5_2_enable(adev, false); 821 822 /* set RB registers */ 823 r = sdma_v5_2_gfx_resume(adev); 824 return r; 825 } 826 827 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 828 r = sdma_v5_2_load_microcode(adev); 829 if (r) 830 return r; 831 832 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 833 if (amdgpu_emu_mode == 1) 834 msleep(1000); 835 } 836 837 /* unhalt the MEs */ 838 sdma_v5_2_enable(adev, true); 839 /* enable sdma ring preemption */ 840 sdma_v5_2_ctx_switch_enable(adev, true); 841 842 /* start the gfx rings and rlc compute queues */ 843 r = sdma_v5_2_gfx_resume(adev); 844 if (r) 845 return r; 846 r = sdma_v5_2_rlc_resume(adev); 847 848 return r; 849 } 850 851 /** 852 * sdma_v5_2_ring_test_ring - simple async dma engine test 853 * 854 * @ring: amdgpu_ring structure holding ring information 855 * 856 * Test the DMA engine by writing using it to write an 857 * value to memory. 858 * Returns 0 for success, error for failure. 859 */ 860 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) 861 { 862 struct amdgpu_device *adev = ring->adev; 863 unsigned i; 864 unsigned index; 865 int r; 866 u32 tmp; 867 u64 gpu_addr; 868 869 r = amdgpu_device_wb_get(adev, &index); 870 if (r) { 871 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 872 return r; 873 } 874 875 gpu_addr = adev->wb.gpu_addr + (index * 4); 876 tmp = 0xCAFEDEAD; 877 adev->wb.wb[index] = cpu_to_le32(tmp); 878 879 r = amdgpu_ring_alloc(ring, 5); 880 if (r) { 881 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 882 amdgpu_device_wb_free(adev, index); 883 return r; 884 } 885 886 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 887 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 888 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 889 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 890 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 891 amdgpu_ring_write(ring, 0xDEADBEEF); 892 amdgpu_ring_commit(ring); 893 894 for (i = 0; i < adev->usec_timeout; i++) { 895 tmp = le32_to_cpu(adev->wb.wb[index]); 896 if (tmp == 0xDEADBEEF) 897 break; 898 if (amdgpu_emu_mode == 1) 899 msleep(1); 900 else 901 udelay(1); 902 } 903 904 if (i >= adev->usec_timeout) 905 r = -ETIMEDOUT; 906 907 amdgpu_device_wb_free(adev, index); 908 909 return r; 910 } 911 912 /** 913 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine 914 * 915 * @ring: amdgpu_ring structure holding ring information 916 * 917 * Test a simple IB in the DMA ring. 918 * Returns 0 on success, error on failure. 919 */ 920 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 921 { 922 struct amdgpu_device *adev = ring->adev; 923 struct amdgpu_ib ib; 924 struct dma_fence *f = NULL; 925 unsigned index; 926 long r; 927 u32 tmp = 0; 928 u64 gpu_addr; 929 930 r = amdgpu_device_wb_get(adev, &index); 931 if (r) { 932 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 933 return r; 934 } 935 936 gpu_addr = adev->wb.gpu_addr + (index * 4); 937 tmp = 0xCAFEDEAD; 938 adev->wb.wb[index] = cpu_to_le32(tmp); 939 memset(&ib, 0, sizeof(ib)); 940 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 941 if (r) { 942 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 943 goto err0; 944 } 945 946 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 947 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 948 ib.ptr[1] = lower_32_bits(gpu_addr); 949 ib.ptr[2] = upper_32_bits(gpu_addr); 950 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 951 ib.ptr[4] = 0xDEADBEEF; 952 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 953 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 954 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 955 ib.length_dw = 8; 956 957 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 958 if (r) 959 goto err1; 960 961 r = dma_fence_wait_timeout(f, false, timeout); 962 if (r == 0) { 963 DRM_ERROR("amdgpu: IB test timed out\n"); 964 r = -ETIMEDOUT; 965 goto err1; 966 } else if (r < 0) { 967 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 968 goto err1; 969 } 970 tmp = le32_to_cpu(adev->wb.wb[index]); 971 if (tmp == 0xDEADBEEF) 972 r = 0; 973 else 974 r = -EINVAL; 975 976 err1: 977 amdgpu_ib_free(adev, &ib, NULL); 978 dma_fence_put(f); 979 err0: 980 amdgpu_device_wb_free(adev, index); 981 return r; 982 } 983 984 985 /** 986 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART 987 * 988 * @ib: indirect buffer to fill with commands 989 * @pe: addr of the page entry 990 * @src: src addr to copy from 991 * @count: number of page entries to update 992 * 993 * Update PTEs by copying them from the GART using sDMA. 994 */ 995 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, 996 uint64_t pe, uint64_t src, 997 unsigned count) 998 { 999 unsigned bytes = count * 8; 1000 1001 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1002 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1003 ib->ptr[ib->length_dw++] = bytes - 1; 1004 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1005 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1006 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1007 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1008 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1009 1010 } 1011 1012 /** 1013 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually 1014 * 1015 * @ib: indirect buffer to fill with commands 1016 * @pe: addr of the page entry 1017 * @addr: dst addr to write into pe 1018 * @count: number of page entries to update 1019 * @incr: increase next addr by incr bytes 1020 * @flags: access flags 1021 * 1022 * Update PTEs by writing them manually using sDMA. 1023 */ 1024 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1025 uint64_t value, unsigned count, 1026 uint32_t incr) 1027 { 1028 unsigned ndw = count * 2; 1029 1030 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1031 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1032 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1033 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1034 ib->ptr[ib->length_dw++] = ndw - 1; 1035 for (; ndw > 0; ndw -= 2) { 1036 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1037 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1038 value += incr; 1039 } 1040 } 1041 1042 /** 1043 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA 1044 * 1045 * @ib: indirect buffer to fill with commands 1046 * @pe: addr of the page entry 1047 * @addr: dst addr to write into pe 1048 * @count: number of page entries to update 1049 * @incr: increase next addr by incr bytes 1050 * @flags: access flags 1051 * 1052 * Update the page tables using sDMA. 1053 */ 1054 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1055 uint64_t pe, 1056 uint64_t addr, unsigned count, 1057 uint32_t incr, uint64_t flags) 1058 { 1059 /* for physically contiguous pages (vram) */ 1060 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1061 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1062 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1063 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1064 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1065 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1066 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1067 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1068 ib->ptr[ib->length_dw++] = 0; 1069 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1070 } 1071 1072 /** 1073 * sdma_v5_2_ring_pad_ib - pad the IB 1074 * 1075 * @ib: indirect buffer to fill with padding 1076 * 1077 * Pad the IB with NOPs to a boundary multiple of 8. 1078 */ 1079 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1080 { 1081 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1082 u32 pad_count; 1083 int i; 1084 1085 pad_count = (-ib->length_dw) & 0x7; 1086 for (i = 0; i < pad_count; i++) 1087 if (sdma && sdma->burst_nop && (i == 0)) 1088 ib->ptr[ib->length_dw++] = 1089 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1090 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1091 else 1092 ib->ptr[ib->length_dw++] = 1093 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1094 } 1095 1096 1097 /** 1098 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline 1099 * 1100 * @ring: amdgpu_ring pointer 1101 * 1102 * Make sure all previous operations are completed (CIK). 1103 */ 1104 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1105 { 1106 uint32_t seq = ring->fence_drv.sync_seq; 1107 uint64_t addr = ring->fence_drv.gpu_addr; 1108 1109 /* wait for idle */ 1110 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1111 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1112 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1113 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1114 amdgpu_ring_write(ring, addr & 0xfffffffc); 1115 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1116 amdgpu_ring_write(ring, seq); /* reference */ 1117 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1118 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1119 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1120 } 1121 1122 1123 /** 1124 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA 1125 * 1126 * @ring: amdgpu_ring pointer 1127 * @vm: amdgpu_vm pointer 1128 * 1129 * Update the page table base and flush the VM TLB 1130 * using sDMA. 1131 */ 1132 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1133 unsigned vmid, uint64_t pd_addr) 1134 { 1135 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1136 } 1137 1138 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, 1139 uint32_t reg, uint32_t val) 1140 { 1141 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1142 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1143 amdgpu_ring_write(ring, reg); 1144 amdgpu_ring_write(ring, val); 1145 } 1146 1147 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1148 uint32_t val, uint32_t mask) 1149 { 1150 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1151 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1152 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1153 amdgpu_ring_write(ring, reg << 2); 1154 amdgpu_ring_write(ring, 0); 1155 amdgpu_ring_write(ring, val); /* reference */ 1156 amdgpu_ring_write(ring, mask); /* mask */ 1157 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1158 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1159 } 1160 1161 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1162 uint32_t reg0, uint32_t reg1, 1163 uint32_t ref, uint32_t mask) 1164 { 1165 amdgpu_ring_emit_wreg(ring, reg0, ref); 1166 /* wait for a cycle to reset vm_inv_eng*_ack */ 1167 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1168 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1169 } 1170 1171 static int sdma_v5_2_early_init(void *handle) 1172 { 1173 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1174 1175 switch (adev->asic_type) { 1176 case CHIP_SIENNA_CICHLID: 1177 adev->sdma.num_instances = 4; 1178 break; 1179 case CHIP_NAVY_FLOUNDER: 1180 case CHIP_DIMGREY_CAVEFISH: 1181 adev->sdma.num_instances = 2; 1182 break; 1183 case CHIP_VANGOGH: 1184 adev->sdma.num_instances = 1; 1185 break; 1186 default: 1187 break; 1188 } 1189 1190 sdma_v5_2_set_ring_funcs(adev); 1191 sdma_v5_2_set_buffer_funcs(adev); 1192 sdma_v5_2_set_vm_pte_funcs(adev); 1193 sdma_v5_2_set_irq_funcs(adev); 1194 1195 return 0; 1196 } 1197 1198 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) 1199 { 1200 switch (seq_num) { 1201 case 0: 1202 return SOC15_IH_CLIENTID_SDMA0; 1203 case 1: 1204 return SOC15_IH_CLIENTID_SDMA1; 1205 case 2: 1206 return SOC15_IH_CLIENTID_SDMA2; 1207 case 3: 1208 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; 1209 default: 1210 break; 1211 } 1212 return -EINVAL; 1213 } 1214 1215 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) 1216 { 1217 switch (seq_num) { 1218 case 0: 1219 return SDMA0_5_0__SRCID__SDMA_TRAP; 1220 case 1: 1221 return SDMA1_5_0__SRCID__SDMA_TRAP; 1222 case 2: 1223 return SDMA2_5_0__SRCID__SDMA_TRAP; 1224 case 3: 1225 return SDMA3_5_0__SRCID__SDMA_TRAP; 1226 default: 1227 break; 1228 } 1229 return -EINVAL; 1230 } 1231 1232 static int sdma_v5_2_sw_init(void *handle) 1233 { 1234 struct amdgpu_ring *ring; 1235 int r, i; 1236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1237 1238 /* SDMA trap event */ 1239 for (i = 0; i < adev->sdma.num_instances; i++) { 1240 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), 1241 sdma_v5_2_seq_to_trap_id(i), 1242 &adev->sdma.trap_irq); 1243 if (r) 1244 return r; 1245 } 1246 1247 r = sdma_v5_2_init_microcode(adev); 1248 if (r) { 1249 DRM_ERROR("Failed to load sdma firmware!\n"); 1250 return r; 1251 } 1252 1253 for (i = 0; i < adev->sdma.num_instances; i++) { 1254 ring = &adev->sdma.instance[i].ring; 1255 ring->ring_obj = NULL; 1256 ring->use_doorbell = true; 1257 ring->me = i; 1258 1259 DRM_INFO("use_doorbell being set to: [%s]\n", 1260 ring->use_doorbell?"true":"false"); 1261 1262 ring->doorbell_index = 1263 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1264 1265 sprintf(ring->name, "sdma%d", i); 1266 r = amdgpu_ring_init(adev, ring, 1024, 1267 &adev->sdma.trap_irq, 1268 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1269 AMDGPU_RING_PRIO_DEFAULT); 1270 if (r) 1271 return r; 1272 } 1273 1274 return r; 1275 } 1276 1277 static int sdma_v5_2_sw_fini(void *handle) 1278 { 1279 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1280 int i; 1281 1282 for (i = 0; i < adev->sdma.num_instances; i++) 1283 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1284 1285 sdma_v5_2_destroy_inst_ctx(adev); 1286 1287 return 0; 1288 } 1289 1290 static int sdma_v5_2_hw_init(void *handle) 1291 { 1292 int r; 1293 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1294 1295 sdma_v5_2_init_golden_registers(adev); 1296 1297 r = sdma_v5_2_start(adev); 1298 1299 return r; 1300 } 1301 1302 static int sdma_v5_2_hw_fini(void *handle) 1303 { 1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1305 1306 if (amdgpu_sriov_vf(adev)) 1307 return 0; 1308 1309 sdma_v5_2_ctx_switch_enable(adev, false); 1310 sdma_v5_2_enable(adev, false); 1311 1312 return 0; 1313 } 1314 1315 static int sdma_v5_2_suspend(void *handle) 1316 { 1317 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1318 1319 return sdma_v5_2_hw_fini(adev); 1320 } 1321 1322 static int sdma_v5_2_resume(void *handle) 1323 { 1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1325 1326 return sdma_v5_2_hw_init(adev); 1327 } 1328 1329 static bool sdma_v5_2_is_idle(void *handle) 1330 { 1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1332 u32 i; 1333 1334 for (i = 0; i < adev->sdma.num_instances; i++) { 1335 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1336 1337 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1338 return false; 1339 } 1340 1341 return true; 1342 } 1343 1344 static int sdma_v5_2_wait_for_idle(void *handle) 1345 { 1346 unsigned i; 1347 u32 sdma0, sdma1, sdma2, sdma3; 1348 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1349 1350 for (i = 0; i < adev->usec_timeout; i++) { 1351 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1352 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1353 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); 1354 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); 1355 1356 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK) 1357 return 0; 1358 udelay(1); 1359 } 1360 return -ETIMEDOUT; 1361 } 1362 1363 static int sdma_v5_2_soft_reset(void *handle) 1364 { 1365 /* todo */ 1366 1367 return 0; 1368 } 1369 1370 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) 1371 { 1372 int i, r = 0; 1373 struct amdgpu_device *adev = ring->adev; 1374 u32 index = 0; 1375 u64 sdma_gfx_preempt; 1376 1377 amdgpu_sdma_get_index_from_ring(ring, &index); 1378 sdma_gfx_preempt = 1379 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT); 1380 1381 /* assert preemption condition */ 1382 amdgpu_ring_set_preempt_cond_exec(ring, false); 1383 1384 /* emit the trailing fence */ 1385 ring->trail_seq += 1; 1386 amdgpu_ring_alloc(ring, 10); 1387 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1388 ring->trail_seq, 0); 1389 amdgpu_ring_commit(ring); 1390 1391 /* assert IB preemption */ 1392 WREG32(sdma_gfx_preempt, 1); 1393 1394 /* poll the trailing fence */ 1395 for (i = 0; i < adev->usec_timeout; i++) { 1396 if (ring->trail_seq == 1397 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1398 break; 1399 udelay(1); 1400 } 1401 1402 if (i >= adev->usec_timeout) { 1403 r = -EINVAL; 1404 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1405 } 1406 1407 /* deassert IB preemption */ 1408 WREG32(sdma_gfx_preempt, 0); 1409 1410 /* deassert the preemption condition */ 1411 amdgpu_ring_set_preempt_cond_exec(ring, true); 1412 return r; 1413 } 1414 1415 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, 1416 struct amdgpu_irq_src *source, 1417 unsigned type, 1418 enum amdgpu_interrupt_state state) 1419 { 1420 u32 sdma_cntl; 1421 1422 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); 1423 1424 sdma_cntl = RREG32(reg_offset); 1425 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1426 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1427 WREG32(reg_offset, sdma_cntl); 1428 1429 return 0; 1430 } 1431 1432 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, 1433 struct amdgpu_irq_src *source, 1434 struct amdgpu_iv_entry *entry) 1435 { 1436 DRM_DEBUG("IH: SDMA trap\n"); 1437 switch (entry->client_id) { 1438 case SOC15_IH_CLIENTID_SDMA0: 1439 switch (entry->ring_id) { 1440 case 0: 1441 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1442 break; 1443 case 1: 1444 /* XXX compute */ 1445 break; 1446 case 2: 1447 /* XXX compute */ 1448 break; 1449 case 3: 1450 /* XXX page queue*/ 1451 break; 1452 } 1453 break; 1454 case SOC15_IH_CLIENTID_SDMA1: 1455 switch (entry->ring_id) { 1456 case 0: 1457 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1458 break; 1459 case 1: 1460 /* XXX compute */ 1461 break; 1462 case 2: 1463 /* XXX compute */ 1464 break; 1465 case 3: 1466 /* XXX page queue*/ 1467 break; 1468 } 1469 break; 1470 case SOC15_IH_CLIENTID_SDMA2: 1471 switch (entry->ring_id) { 1472 case 0: 1473 amdgpu_fence_process(&adev->sdma.instance[2].ring); 1474 break; 1475 case 1: 1476 /* XXX compute */ 1477 break; 1478 case 2: 1479 /* XXX compute */ 1480 break; 1481 case 3: 1482 /* XXX page queue*/ 1483 break; 1484 } 1485 break; 1486 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: 1487 switch (entry->ring_id) { 1488 case 0: 1489 amdgpu_fence_process(&adev->sdma.instance[3].ring); 1490 break; 1491 case 1: 1492 /* XXX compute */ 1493 break; 1494 case 2: 1495 /* XXX compute */ 1496 break; 1497 case 3: 1498 /* XXX page queue*/ 1499 break; 1500 } 1501 break; 1502 } 1503 return 0; 1504 } 1505 1506 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1507 struct amdgpu_irq_src *source, 1508 struct amdgpu_iv_entry *entry) 1509 { 1510 return 0; 1511 } 1512 1513 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1514 bool enable) 1515 { 1516 uint32_t data, def; 1517 int i; 1518 1519 for (i = 0; i < adev->sdma.num_instances; i++) { 1520 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1521 /* Enable sdma clock gating */ 1522 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1523 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1524 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1525 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1526 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1527 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1528 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1529 if (def != data) 1530 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1531 } else { 1532 /* Disable sdma clock gating */ 1533 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1534 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1535 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1536 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1537 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1538 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1539 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1540 if (def != data) 1541 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1542 } 1543 } 1544 } 1545 1546 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1547 bool enable) 1548 { 1549 uint32_t data, def; 1550 int i; 1551 1552 for (i = 0; i < adev->sdma.num_instances; i++) { 1553 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1554 /* Enable sdma mem light sleep */ 1555 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1556 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1557 if (def != data) 1558 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1559 1560 } else { 1561 /* Disable sdma mem light sleep */ 1562 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1563 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1564 if (def != data) 1565 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1566 1567 } 1568 } 1569 } 1570 1571 static int sdma_v5_2_set_clockgating_state(void *handle, 1572 enum amd_clockgating_state state) 1573 { 1574 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1575 1576 if (amdgpu_sriov_vf(adev)) 1577 return 0; 1578 1579 switch (adev->asic_type) { 1580 case CHIP_SIENNA_CICHLID: 1581 case CHIP_NAVY_FLOUNDER: 1582 case CHIP_VANGOGH: 1583 case CHIP_DIMGREY_CAVEFISH: 1584 sdma_v5_2_update_medium_grain_clock_gating(adev, 1585 state == AMD_CG_STATE_GATE ? true : false); 1586 sdma_v5_2_update_medium_grain_light_sleep(adev, 1587 state == AMD_CG_STATE_GATE ? true : false); 1588 break; 1589 default: 1590 break; 1591 } 1592 1593 return 0; 1594 } 1595 1596 static int sdma_v5_2_set_powergating_state(void *handle, 1597 enum amd_powergating_state state) 1598 { 1599 return 0; 1600 } 1601 1602 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags) 1603 { 1604 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1605 int data; 1606 1607 if (amdgpu_sriov_vf(adev)) 1608 *flags = 0; 1609 1610 /* AMD_CG_SUPPORT_SDMA_LS */ 1611 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1612 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1613 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1614 } 1615 1616 const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1617 .name = "sdma_v5_2", 1618 .early_init = sdma_v5_2_early_init, 1619 .late_init = NULL, 1620 .sw_init = sdma_v5_2_sw_init, 1621 .sw_fini = sdma_v5_2_sw_fini, 1622 .hw_init = sdma_v5_2_hw_init, 1623 .hw_fini = sdma_v5_2_hw_fini, 1624 .suspend = sdma_v5_2_suspend, 1625 .resume = sdma_v5_2_resume, 1626 .is_idle = sdma_v5_2_is_idle, 1627 .wait_for_idle = sdma_v5_2_wait_for_idle, 1628 .soft_reset = sdma_v5_2_soft_reset, 1629 .set_clockgating_state = sdma_v5_2_set_clockgating_state, 1630 .set_powergating_state = sdma_v5_2_set_powergating_state, 1631 .get_clockgating_state = sdma_v5_2_get_clockgating_state, 1632 }; 1633 1634 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 1635 .type = AMDGPU_RING_TYPE_SDMA, 1636 .align_mask = 0xf, 1637 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1638 .support_64bit_ptrs = true, 1639 .vmhub = AMDGPU_GFXHUB_0, 1640 .get_rptr = sdma_v5_2_ring_get_rptr, 1641 .get_wptr = sdma_v5_2_ring_get_wptr, 1642 .set_wptr = sdma_v5_2_ring_set_wptr, 1643 .emit_frame_size = 1644 5 + /* sdma_v5_2_ring_init_cond_exec */ 1645 6 + /* sdma_v5_2_ring_emit_hdp_flush */ 1646 3 + /* hdp_invalidate */ 1647 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ 1648 /* sdma_v5_2_ring_emit_vm_flush */ 1649 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1650 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1651 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ 1652 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ 1653 .emit_ib = sdma_v5_2_ring_emit_ib, 1654 .emit_fence = sdma_v5_2_ring_emit_fence, 1655 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, 1656 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, 1657 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, 1658 .test_ring = sdma_v5_2_ring_test_ring, 1659 .test_ib = sdma_v5_2_ring_test_ib, 1660 .insert_nop = sdma_v5_2_ring_insert_nop, 1661 .pad_ib = sdma_v5_2_ring_pad_ib, 1662 .emit_wreg = sdma_v5_2_ring_emit_wreg, 1663 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, 1664 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, 1665 .init_cond_exec = sdma_v5_2_ring_init_cond_exec, 1666 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec, 1667 .preempt_ib = sdma_v5_2_ring_preempt_ib, 1668 }; 1669 1670 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) 1671 { 1672 int i; 1673 1674 for (i = 0; i < adev->sdma.num_instances; i++) { 1675 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; 1676 adev->sdma.instance[i].ring.me = i; 1677 } 1678 } 1679 1680 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { 1681 .set = sdma_v5_2_set_trap_irq_state, 1682 .process = sdma_v5_2_process_trap_irq, 1683 }; 1684 1685 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { 1686 .process = sdma_v5_2_process_illegal_inst_irq, 1687 }; 1688 1689 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) 1690 { 1691 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1692 adev->sdma.num_instances; 1693 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; 1694 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; 1695 } 1696 1697 /** 1698 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine 1699 * 1700 * @ring: amdgpu_ring structure holding ring information 1701 * @src_offset: src GPU address 1702 * @dst_offset: dst GPU address 1703 * @byte_count: number of bytes to xfer 1704 * 1705 * Copy GPU buffers using the DMA engine. 1706 * Used by the amdgpu ttm implementation to move pages if 1707 * registered as the asic copy callback. 1708 */ 1709 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, 1710 uint64_t src_offset, 1711 uint64_t dst_offset, 1712 uint32_t byte_count, 1713 bool tmz) 1714 { 1715 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1716 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1717 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1718 ib->ptr[ib->length_dw++] = byte_count - 1; 1719 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1720 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1721 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1722 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1723 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1724 } 1725 1726 /** 1727 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine 1728 * 1729 * @ring: amdgpu_ring structure holding ring information 1730 * @src_data: value to write to buffer 1731 * @dst_offset: dst GPU address 1732 * @byte_count: number of bytes to xfer 1733 * 1734 * Fill GPU buffers using the DMA engine. 1735 */ 1736 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, 1737 uint32_t src_data, 1738 uint64_t dst_offset, 1739 uint32_t byte_count) 1740 { 1741 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1742 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1743 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1744 ib->ptr[ib->length_dw++] = src_data; 1745 ib->ptr[ib->length_dw++] = byte_count - 1; 1746 } 1747 1748 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { 1749 .copy_max_bytes = 0x400000, 1750 .copy_num_dw = 7, 1751 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, 1752 1753 .fill_max_bytes = 0x400000, 1754 .fill_num_dw = 5, 1755 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, 1756 }; 1757 1758 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) 1759 { 1760 if (adev->mman.buffer_funcs == NULL) { 1761 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 1762 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1763 } 1764 } 1765 1766 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 1767 .copy_pte_num_dw = 7, 1768 .copy_pte = sdma_v5_2_vm_copy_pte, 1769 .write_pte = sdma_v5_2_vm_write_pte, 1770 .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 1771 }; 1772 1773 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 1774 { 1775 unsigned i; 1776 1777 if (adev->vm_manager.vm_pte_funcs == NULL) { 1778 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 1779 for (i = 0; i < adev->sdma.num_instances; i++) { 1780 adev->vm_manager.vm_pte_scheds[i] = 1781 &adev->sdma.instance[i].ring.sched; 1782 } 1783 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1784 } 1785 } 1786 1787 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { 1788 .type = AMD_IP_BLOCK_TYPE_SDMA, 1789 .major = 5, 1790 .minor = 2, 1791 .rev = 0, 1792 .funcs = &sdma_v5_2_ip_funcs, 1793 }; 1794