1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32 
33 #include "gc/gc_10_3_0_offset.h"
34 #include "gc/gc_10_3_0_sh_mask.h"
35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
39 
40 #include "soc15_common.h"
41 #include "soc15.h"
42 #include "navi10_sdma_pkt_open.h"
43 #include "nbio_v2_3.h"
44 #include "sdma_common.h"
45 #include "sdma_v5_2.h"
46 
47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
51 
52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin");
55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
56 
57 #define SDMA1_REG_OFFSET 0x600
58 #define SDMA3_REG_OFFSET 0x400
59 #define SDMA0_HYP_DEC_REG_START 0x5880
60 #define SDMA0_HYP_DEC_REG_END 0x5893
61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
62 
63 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
64 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
65 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
66 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
67 
68 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
69 {
70 	u32 base;
71 
72 	if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
73 	    internal_offset <= SDMA0_HYP_DEC_REG_END) {
74 		base = adev->reg_offset[GC_HWIP][0][1];
75 		if (instance != 0)
76 			internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
77 	} else {
78 		if (instance < 2) {
79 			base = adev->reg_offset[GC_HWIP][0][0];
80 			if (instance == 1)
81 				internal_offset += SDMA1_REG_OFFSET;
82 		} else {
83 			base = adev->reg_offset[GC_HWIP][0][2];
84 			if (instance == 3)
85 				internal_offset += SDMA3_REG_OFFSET;
86 		}
87 	}
88 
89 	return base + internal_offset;
90 }
91 
92 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
93 {
94 	unsigned ret;
95 
96 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
97 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
98 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
99 	amdgpu_ring_write(ring, 1);
100 	ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
101 	amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
102 
103 	return ret;
104 }
105 
106 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
107 					   unsigned offset)
108 {
109 	unsigned cur;
110 
111 	BUG_ON(offset > ring->buf_mask);
112 	BUG_ON(ring->ring[offset] != 0x55aa55aa);
113 
114 	cur = (ring->wptr - 1) & ring->buf_mask;
115 	if (cur > offset)
116 		ring->ring[offset] = cur - offset;
117 	else
118 		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
119 }
120 
121 /**
122  * sdma_v5_2_ring_get_rptr - get the current read pointer
123  *
124  * @ring: amdgpu ring pointer
125  *
126  * Get the current rptr from the hardware (NAVI10+).
127  */
128 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
129 {
130 	u64 *rptr;
131 
132 	/* XXX check if swapping is necessary on BE */
133 	rptr = (u64 *)ring->rptr_cpu_addr;
134 
135 	DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
136 	return ((*rptr) >> 2);
137 }
138 
139 /**
140  * sdma_v5_2_ring_get_wptr - get the current write pointer
141  *
142  * @ring: amdgpu ring pointer
143  *
144  * Get the current wptr from the hardware (NAVI10+).
145  */
146 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
147 {
148 	struct amdgpu_device *adev = ring->adev;
149 	u64 wptr;
150 
151 	if (ring->use_doorbell) {
152 		/* XXX check if swapping is necessary on BE */
153 		wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
154 		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
155 	} else {
156 		wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
157 		wptr = wptr << 32;
158 		wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
159 		DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
160 	}
161 
162 	return wptr >> 2;
163 }
164 
165 /**
166  * sdma_v5_2_ring_set_wptr - commit the write pointer
167  *
168  * @ring: amdgpu ring pointer
169  *
170  * Write the wptr back to the hardware (NAVI10+).
171  */
172 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
173 {
174 	struct amdgpu_device *adev = ring->adev;
175 
176 	DRM_DEBUG("Setting write pointer\n");
177 	if (ring->use_doorbell) {
178 		DRM_DEBUG("Using doorbell -- "
179 				"wptr_offs == 0x%08x "
180 				"lower_32_bits(ring->wptr << 2) == 0x%08x "
181 				"upper_32_bits(ring->wptr << 2) == 0x%08x\n",
182 				ring->wptr_offs,
183 				lower_32_bits(ring->wptr << 2),
184 				upper_32_bits(ring->wptr << 2));
185 		/* XXX check if swapping is necessary on BE */
186 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
187 			     ring->wptr << 2);
188 		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
189 				ring->doorbell_index, ring->wptr << 2);
190 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
191 	} else {
192 		DRM_DEBUG("Not using doorbell -- "
193 				"mmSDMA%i_GFX_RB_WPTR == 0x%08x "
194 				"mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
195 				ring->me,
196 				lower_32_bits(ring->wptr << 2),
197 				ring->me,
198 				upper_32_bits(ring->wptr << 2));
199 		WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
200 			lower_32_bits(ring->wptr << 2));
201 		WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
202 			upper_32_bits(ring->wptr << 2));
203 	}
204 }
205 
206 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
207 {
208 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
209 	int i;
210 
211 	for (i = 0; i < count; i++)
212 		if (sdma && sdma->burst_nop && (i == 0))
213 			amdgpu_ring_write(ring, ring->funcs->nop |
214 				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
215 		else
216 			amdgpu_ring_write(ring, ring->funcs->nop);
217 }
218 
219 /**
220  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
221  *
222  * @ring: amdgpu ring pointer
223  * @job: job to retrieve vmid from
224  * @ib: IB object to schedule
225  * @flags: unused
226  *
227  * Schedule an IB in the DMA ring.
228  */
229 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
230 				   struct amdgpu_job *job,
231 				   struct amdgpu_ib *ib,
232 				   uint32_t flags)
233 {
234 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
235 	uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
236 
237 	/* An IB packet must end on a 8 DW boundary--the next dword
238 	 * must be on a 8-dword boundary. Our IB packet below is 6
239 	 * dwords long, thus add x number of NOPs, such that, in
240 	 * modular arithmetic,
241 	 * wptr + 6 + x = 8k, k >= 0, which in C is,
242 	 * (wptr + 6 + x) % 8 = 0.
243 	 * The expression below, is a solution of x.
244 	 */
245 	sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
246 
247 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
248 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
249 	/* base must be 32 byte aligned */
250 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
251 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
252 	amdgpu_ring_write(ring, ib->length_dw);
253 	amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
254 	amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
255 }
256 
257 /**
258  * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
259  *
260  * @ring: amdgpu ring pointer
261  *
262  * flush the IB by graphics cache rinse.
263  */
264 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
265 {
266 	uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |
267 			    SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV |
268 			    SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
269 			    SDMA_GCR_GLI_INV(1);
270 
271 	/* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
272 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
273 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
274 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
275 			SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
276 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
277 			SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
278 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
279 			SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
280 }
281 
282 /**
283  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
284  *
285  * @ring: amdgpu ring pointer
286  *
287  * Emit an hdp flush packet on the requested DMA ring.
288  */
289 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
290 {
291 	struct amdgpu_device *adev = ring->adev;
292 	u32 ref_and_mask = 0;
293 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
294 
295 	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
296 
297 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
298 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
299 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
300 	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
301 	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
302 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
303 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
304 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
305 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
306 }
307 
308 /**
309  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
310  *
311  * @ring: amdgpu ring pointer
312  * @addr: address
313  * @seq: sequence number
314  * @flags: fence related flags
315  *
316  * Add a DMA fence packet to the ring to write
317  * the fence seq number and DMA trap packet to generate
318  * an interrupt if needed.
319  */
320 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
321 				      unsigned flags)
322 {
323 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
324 	/* write the fence */
325 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
326 			  SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
327 	/* zero in first two bits */
328 	BUG_ON(addr & 0x3);
329 	amdgpu_ring_write(ring, lower_32_bits(addr));
330 	amdgpu_ring_write(ring, upper_32_bits(addr));
331 	amdgpu_ring_write(ring, lower_32_bits(seq));
332 
333 	/* optionally write high bits as well */
334 	if (write64bit) {
335 		addr += 4;
336 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
337 				  SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
338 		/* zero in first two bits */
339 		BUG_ON(addr & 0x3);
340 		amdgpu_ring_write(ring, lower_32_bits(addr));
341 		amdgpu_ring_write(ring, upper_32_bits(addr));
342 		amdgpu_ring_write(ring, upper_32_bits(seq));
343 	}
344 
345 	if ((flags & AMDGPU_FENCE_FLAG_INT)) {
346 		uint32_t ctx = ring->is_mes_queue ?
347 			(ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
348 		/* generate an interrupt */
349 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
350 		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
351 	}
352 }
353 
354 
355 /**
356  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
357  *
358  * @adev: amdgpu_device pointer
359  *
360  * Stop the gfx async dma ring buffers.
361  */
362 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
363 {
364 	u32 rb_cntl, ib_cntl;
365 	int i;
366 
367 	amdgpu_sdma_unset_buffer_funcs_helper(adev);
368 
369 	for (i = 0; i < adev->sdma.num_instances; i++) {
370 		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
371 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
372 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
373 		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
374 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
375 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
376 	}
377 }
378 
379 /**
380  * sdma_v5_2_rlc_stop - stop the compute async dma engines
381  *
382  * @adev: amdgpu_device pointer
383  *
384  * Stop the compute async dma queues.
385  */
386 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
387 {
388 	/* XXX todo */
389 }
390 
391 /**
392  * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
393  *
394  * @adev: amdgpu_device pointer
395  * @enable: enable/disable the DMA MEs context switch.
396  *
397  * Halt or unhalt the async dma engines context switch.
398  */
399 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
400 {
401 	u32 f32_cntl, phase_quantum = 0;
402 	int i;
403 
404 	if (amdgpu_sdma_phase_quantum) {
405 		unsigned value = amdgpu_sdma_phase_quantum;
406 		unsigned unit = 0;
407 
408 		while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
409 				SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
410 			value = (value + 1) >> 1;
411 			unit++;
412 		}
413 		if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
414 			    SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
415 			value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
416 				 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
417 			unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
418 				SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
419 			WARN_ONCE(1,
420 			"clamping sdma_phase_quantum to %uK clock cycles\n",
421 				  value << unit);
422 		}
423 		phase_quantum =
424 			value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
425 			unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
426 	}
427 
428 	for (i = 0; i < adev->sdma.num_instances; i++) {
429 		if (enable && amdgpu_sdma_phase_quantum) {
430 			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
431 			       phase_quantum);
432 			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
433 			       phase_quantum);
434 			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
435 			       phase_quantum);
436 		}
437 
438 		if (!amdgpu_sriov_vf(adev)) {
439 			f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
440 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
441 					AUTO_CTXSW_ENABLE, enable ? 1 : 0);
442 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
443 		}
444 	}
445 
446 }
447 
448 /**
449  * sdma_v5_2_enable - stop the async dma engines
450  *
451  * @adev: amdgpu_device pointer
452  * @enable: enable/disable the DMA MEs.
453  *
454  * Halt or unhalt the async dma engines.
455  */
456 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
457 {
458 	u32 f32_cntl;
459 	int i;
460 
461 	if (!enable) {
462 		sdma_v5_2_gfx_stop(adev);
463 		sdma_v5_2_rlc_stop(adev);
464 	}
465 
466 	if (!amdgpu_sriov_vf(adev)) {
467 		for (i = 0; i < adev->sdma.num_instances; i++) {
468 			f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
469 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
470 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
471 		}
472 	}
473 }
474 
475 /**
476  * sdma_v5_2_gfx_resume - setup and start the async dma engines
477  *
478  * @adev: amdgpu_device pointer
479  *
480  * Set up the gfx DMA ring buffers and enable them.
481  * Returns 0 for success, error for failure.
482  */
483 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
484 {
485 	struct amdgpu_ring *ring;
486 	u32 rb_cntl, ib_cntl;
487 	u32 rb_bufsz;
488 	u32 doorbell;
489 	u32 doorbell_offset;
490 	u32 temp;
491 	u32 wptr_poll_cntl;
492 	u64 wptr_gpu_addr;
493 	int i, r;
494 
495 	for (i = 0; i < adev->sdma.num_instances; i++) {
496 		ring = &adev->sdma.instance[i].ring;
497 
498 		if (!amdgpu_sriov_vf(adev))
499 			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
500 
501 		/* Set ring buffer size in dwords */
502 		rb_bufsz = order_base_2(ring->ring_size / 4);
503 		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
504 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
505 #ifdef __BIG_ENDIAN
506 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
507 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
508 					RPTR_WRITEBACK_SWAP_ENABLE, 1);
509 #endif
510 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
511 
512 		/* Initialize the ring buffer's read and write pointers */
513 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
514 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
515 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
516 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
517 
518 		/* setup the wptr shadow polling */
519 		wptr_gpu_addr = ring->wptr_gpu_addr;
520 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
521 		       lower_32_bits(wptr_gpu_addr));
522 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
523 		       upper_32_bits(wptr_gpu_addr));
524 		wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
525 							 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
526 		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
527 					       SDMA0_GFX_RB_WPTR_POLL_CNTL,
528 					       F32_POLL_ENABLE, 1);
529 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
530 		       wptr_poll_cntl);
531 
532 		/* set the wb address whether it's enabled or not */
533 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
534 		       upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
535 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
536 		       lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
537 
538 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
539 
540 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
541 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
542 
543 		ring->wptr = 0;
544 
545 		/* before programing wptr to a less value, need set minor_ptr_update first */
546 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
547 
548 		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
549 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
550 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
551 		}
552 
553 		doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
554 		doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
555 
556 		if (ring->use_doorbell) {
557 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
558 			doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
559 					OFFSET, ring->doorbell_index);
560 		} else {
561 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
562 		}
563 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
564 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
565 
566 		adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
567 						      ring->doorbell_index,
568 						      adev->doorbell_index.sdma_doorbell_range);
569 
570 		if (amdgpu_sriov_vf(adev))
571 			sdma_v5_2_ring_set_wptr(ring);
572 
573 		/* set minor_ptr_update to 0 after wptr programed */
574 
575 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
576 
577 		/* SRIOV VF has no control of any of registers below */
578 		if (!amdgpu_sriov_vf(adev)) {
579 			/* set utc l1 enable flag always to 1 */
580 			temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
581 			temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
582 
583 			/* enable MCBP */
584 			temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
585 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
586 
587 			/* Set up RESP_MODE to non-copy addresses */
588 			temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
589 			temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
590 			temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
591 			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
592 
593 			/* program default cache read and write policy */
594 			temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
595 			/* clean read policy and write policy bits */
596 			temp &= 0xFF0FFF;
597 			temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
598 				 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
599 				 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
600 			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
601 
602 			/* unhalt engine */
603 			temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
604 			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
605 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
606 		}
607 
608 		/* enable DMA RB */
609 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
610 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
611 
612 		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
613 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
614 #ifdef __BIG_ENDIAN
615 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
616 #endif
617 		/* enable DMA IBs */
618 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
619 
620 		ring->sched.ready = true;
621 
622 		if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
623 			sdma_v5_2_ctx_switch_enable(adev, true);
624 			sdma_v5_2_enable(adev, true);
625 		}
626 
627 		r = amdgpu_ring_test_ring(ring);
628 		if (r) {
629 			ring->sched.ready = false;
630 			return r;
631 		}
632 
633 		if (adev->mman.buffer_funcs_ring == ring)
634 			amdgpu_ttm_set_buffer_funcs_status(adev, true);
635 	}
636 
637 	return 0;
638 }
639 
640 /**
641  * sdma_v5_2_rlc_resume - setup and start the async dma engines
642  *
643  * @adev: amdgpu_device pointer
644  *
645  * Set up the compute DMA queues and enable them.
646  * Returns 0 for success, error for failure.
647  */
648 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
649 {
650 	return 0;
651 }
652 
653 /**
654  * sdma_v5_2_load_microcode - load the sDMA ME ucode
655  *
656  * @adev: amdgpu_device pointer
657  *
658  * Loads the sDMA0/1/2/3 ucode.
659  * Returns 0 for success, -EINVAL if the ucode is not available.
660  */
661 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
662 {
663 	const struct sdma_firmware_header_v1_0 *hdr;
664 	const __le32 *fw_data;
665 	u32 fw_size;
666 	int i, j;
667 
668 	/* halt the MEs */
669 	sdma_v5_2_enable(adev, false);
670 
671 	for (i = 0; i < adev->sdma.num_instances; i++) {
672 		if (!adev->sdma.instance[i].fw)
673 			return -EINVAL;
674 
675 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
676 		amdgpu_ucode_print_sdma_hdr(&hdr->header);
677 		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
678 
679 		fw_data = (const __le32 *)
680 			(adev->sdma.instance[i].fw->data +
681 				le32_to_cpu(hdr->header.ucode_array_offset_bytes));
682 
683 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
684 
685 		for (j = 0; j < fw_size; j++) {
686 			if (amdgpu_emu_mode == 1 && j % 500 == 0)
687 				msleep(1);
688 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
689 		}
690 
691 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
692 	}
693 
694 	return 0;
695 }
696 
697 static int sdma_v5_2_soft_reset(void *handle)
698 {
699 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
700 	u32 grbm_soft_reset;
701 	u32 tmp;
702 	int i;
703 
704 	for (i = 0; i < adev->sdma.num_instances; i++) {
705 		grbm_soft_reset = REG_SET_FIELD(0,
706 						GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
707 						1);
708 		grbm_soft_reset <<= i;
709 
710 		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
711 		tmp |= grbm_soft_reset;
712 		DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
713 		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
714 		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
715 
716 		udelay(50);
717 
718 		tmp &= ~grbm_soft_reset;
719 		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
720 		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
721 
722 		udelay(50);
723 	}
724 
725 	return 0;
726 }
727 
728 /**
729  * sdma_v5_2_start - setup and start the async dma engines
730  *
731  * @adev: amdgpu_device pointer
732  *
733  * Set up the DMA engines and enable them.
734  * Returns 0 for success, error for failure.
735  */
736 static int sdma_v5_2_start(struct amdgpu_device *adev)
737 {
738 	int r = 0;
739 
740 	if (amdgpu_sriov_vf(adev)) {
741 		sdma_v5_2_ctx_switch_enable(adev, false);
742 		sdma_v5_2_enable(adev, false);
743 
744 		/* set RB registers */
745 		r = sdma_v5_2_gfx_resume(adev);
746 		return r;
747 	}
748 
749 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
750 		r = sdma_v5_2_load_microcode(adev);
751 		if (r)
752 			return r;
753 
754 		/* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
755 		if (amdgpu_emu_mode == 1)
756 			msleep(1000);
757 	}
758 
759 	sdma_v5_2_soft_reset(adev);
760 	/* unhalt the MEs */
761 	sdma_v5_2_enable(adev, true);
762 	/* enable sdma ring preemption */
763 	sdma_v5_2_ctx_switch_enable(adev, true);
764 
765 	/* start the gfx rings and rlc compute queues */
766 	r = sdma_v5_2_gfx_resume(adev);
767 	if (r)
768 		return r;
769 	r = sdma_v5_2_rlc_resume(adev);
770 
771 	return r;
772 }
773 
774 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd,
775 			      struct amdgpu_mqd_prop *prop)
776 {
777 	struct v10_sdma_mqd *m = mqd;
778 	uint64_t wb_gpu_addr;
779 
780 	m->sdmax_rlcx_rb_cntl =
781 		order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
782 		1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
783 		6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
784 		1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
785 
786 	m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
787 	m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
788 
789 	m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
790 						  mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
791 
792 	wb_gpu_addr = prop->wptr_gpu_addr;
793 	m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
794 	m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
795 
796 	wb_gpu_addr = prop->rptr_gpu_addr;
797 	m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
798 	m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
799 
800 	m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
801 							mmSDMA0_GFX_IB_CNTL));
802 
803 	m->sdmax_rlcx_doorbell_offset =
804 		prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
805 
806 	m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
807 
808 	return 0;
809 }
810 
811 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev)
812 {
813 	adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
814 	adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init;
815 }
816 
817 /**
818  * sdma_v5_2_ring_test_ring - simple async dma engine test
819  *
820  * @ring: amdgpu_ring structure holding ring information
821  *
822  * Test the DMA engine by writing using it to write an
823  * value to memory.
824  * Returns 0 for success, error for failure.
825  */
826 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
827 {
828 	struct amdgpu_device *adev = ring->adev;
829 	unsigned i;
830 	unsigned index;
831 	int r;
832 	u32 tmp;
833 	u64 gpu_addr;
834 	volatile uint32_t *cpu_ptr = NULL;
835 
836 	tmp = 0xCAFEDEAD;
837 
838 	if (ring->is_mes_queue) {
839 		uint32_t offset = 0;
840 		offset = amdgpu_mes_ctx_get_offs(ring,
841 					 AMDGPU_MES_CTX_PADDING_OFFS);
842 		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
843 		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
844 		*cpu_ptr = tmp;
845 	} else {
846 		r = amdgpu_device_wb_get(adev, &index);
847 		if (r) {
848 			dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
849 			return r;
850 		}
851 
852 		gpu_addr = adev->wb.gpu_addr + (index * 4);
853 		adev->wb.wb[index] = cpu_to_le32(tmp);
854 	}
855 
856 	r = amdgpu_ring_alloc(ring, 20);
857 	if (r) {
858 		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
859 		amdgpu_device_wb_free(adev, index);
860 		return r;
861 	}
862 
863 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
864 			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
865 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
866 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
867 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
868 	amdgpu_ring_write(ring, 0xDEADBEEF);
869 	amdgpu_ring_commit(ring);
870 
871 	for (i = 0; i < adev->usec_timeout; i++) {
872 		if (ring->is_mes_queue)
873 			tmp = le32_to_cpu(*cpu_ptr);
874 		else
875 			tmp = le32_to_cpu(adev->wb.wb[index]);
876 		if (tmp == 0xDEADBEEF)
877 			break;
878 		if (amdgpu_emu_mode == 1)
879 			msleep(1);
880 		else
881 			udelay(1);
882 	}
883 
884 	if (i >= adev->usec_timeout)
885 		r = -ETIMEDOUT;
886 
887 	if (!ring->is_mes_queue)
888 		amdgpu_device_wb_free(adev, index);
889 
890 	return r;
891 }
892 
893 /**
894  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
895  *
896  * @ring: amdgpu_ring structure holding ring information
897  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
898  *
899  * Test a simple IB in the DMA ring.
900  * Returns 0 on success, error on failure.
901  */
902 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
903 {
904 	struct amdgpu_device *adev = ring->adev;
905 	struct amdgpu_ib ib;
906 	struct dma_fence *f = NULL;
907 	unsigned index;
908 	long r;
909 	u32 tmp = 0;
910 	u64 gpu_addr;
911 	volatile uint32_t *cpu_ptr = NULL;
912 
913 	tmp = 0xCAFEDEAD;
914 	memset(&ib, 0, sizeof(ib));
915 
916 	if (ring->is_mes_queue) {
917 		uint32_t offset = 0;
918 		offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
919 		ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
920 		ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
921 
922 		offset = amdgpu_mes_ctx_get_offs(ring,
923 					 AMDGPU_MES_CTX_PADDING_OFFS);
924 		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
925 		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
926 		*cpu_ptr = tmp;
927 	} else {
928 		r = amdgpu_device_wb_get(adev, &index);
929 		if (r) {
930 			dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
931 			return r;
932 		}
933 
934 		gpu_addr = adev->wb.gpu_addr + (index * 4);
935 		adev->wb.wb[index] = cpu_to_le32(tmp);
936 
937 		r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
938 		if (r) {
939 			DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
940 			goto err0;
941 		}
942 	}
943 
944 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
945 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
946 	ib.ptr[1] = lower_32_bits(gpu_addr);
947 	ib.ptr[2] = upper_32_bits(gpu_addr);
948 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
949 	ib.ptr[4] = 0xDEADBEEF;
950 	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
951 	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
952 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
953 	ib.length_dw = 8;
954 
955 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
956 	if (r)
957 		goto err1;
958 
959 	r = dma_fence_wait_timeout(f, false, timeout);
960 	if (r == 0) {
961 		DRM_ERROR("amdgpu: IB test timed out\n");
962 		r = -ETIMEDOUT;
963 		goto err1;
964 	} else if (r < 0) {
965 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
966 		goto err1;
967 	}
968 
969 	if (ring->is_mes_queue)
970 		tmp = le32_to_cpu(*cpu_ptr);
971 	else
972 		tmp = le32_to_cpu(adev->wb.wb[index]);
973 
974 	if (tmp == 0xDEADBEEF)
975 		r = 0;
976 	else
977 		r = -EINVAL;
978 
979 err1:
980 	amdgpu_ib_free(adev, &ib, NULL);
981 	dma_fence_put(f);
982 err0:
983 	if (!ring->is_mes_queue)
984 		amdgpu_device_wb_free(adev, index);
985 	return r;
986 }
987 
988 
989 /**
990  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
991  *
992  * @ib: indirect buffer to fill with commands
993  * @pe: addr of the page entry
994  * @src: src addr to copy from
995  * @count: number of page entries to update
996  *
997  * Update PTEs by copying them from the GART using sDMA.
998  */
999 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1000 				  uint64_t pe, uint64_t src,
1001 				  unsigned count)
1002 {
1003 	unsigned bytes = count * 8;
1004 
1005 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1006 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1007 	ib->ptr[ib->length_dw++] = bytes - 1;
1008 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1009 	ib->ptr[ib->length_dw++] = lower_32_bits(src);
1010 	ib->ptr[ib->length_dw++] = upper_32_bits(src);
1011 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1012 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1013 
1014 }
1015 
1016 /**
1017  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1018  *
1019  * @ib: indirect buffer to fill with commands
1020  * @pe: addr of the page entry
1021  * @value: dst addr to write into pe
1022  * @count: number of page entries to update
1023  * @incr: increase next addr by incr bytes
1024  *
1025  * Update PTEs by writing them manually using sDMA.
1026  */
1027 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1028 				   uint64_t value, unsigned count,
1029 				   uint32_t incr)
1030 {
1031 	unsigned ndw = count * 2;
1032 
1033 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1034 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1035 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1036 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1037 	ib->ptr[ib->length_dw++] = ndw - 1;
1038 	for (; ndw > 0; ndw -= 2) {
1039 		ib->ptr[ib->length_dw++] = lower_32_bits(value);
1040 		ib->ptr[ib->length_dw++] = upper_32_bits(value);
1041 		value += incr;
1042 	}
1043 }
1044 
1045 /**
1046  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1047  *
1048  * @ib: indirect buffer to fill with commands
1049  * @pe: addr of the page entry
1050  * @addr: dst addr to write into pe
1051  * @count: number of page entries to update
1052  * @incr: increase next addr by incr bytes
1053  * @flags: access flags
1054  *
1055  * Update the page tables using sDMA.
1056  */
1057 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1058 				     uint64_t pe,
1059 				     uint64_t addr, unsigned count,
1060 				     uint32_t incr, uint64_t flags)
1061 {
1062 	/* for physically contiguous pages (vram) */
1063 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1064 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1065 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1066 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1067 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1068 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1069 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1070 	ib->ptr[ib->length_dw++] = incr; /* increment size */
1071 	ib->ptr[ib->length_dw++] = 0;
1072 	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1073 }
1074 
1075 /**
1076  * sdma_v5_2_ring_pad_ib - pad the IB
1077  *
1078  * @ib: indirect buffer to fill with padding
1079  * @ring: amdgpu_ring structure holding ring information
1080  *
1081  * Pad the IB with NOPs to a boundary multiple of 8.
1082  */
1083 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1084 {
1085 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1086 	u32 pad_count;
1087 	int i;
1088 
1089 	pad_count = (-ib->length_dw) & 0x7;
1090 	for (i = 0; i < pad_count; i++)
1091 		if (sdma && sdma->burst_nop && (i == 0))
1092 			ib->ptr[ib->length_dw++] =
1093 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1094 				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1095 		else
1096 			ib->ptr[ib->length_dw++] =
1097 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1098 }
1099 
1100 
1101 /**
1102  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1103  *
1104  * @ring: amdgpu_ring pointer
1105  *
1106  * Make sure all previous operations are completed (CIK).
1107  */
1108 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1109 {
1110 	uint32_t seq = ring->fence_drv.sync_seq;
1111 	uint64_t addr = ring->fence_drv.gpu_addr;
1112 
1113 	/* wait for idle */
1114 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1115 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1116 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1117 			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1118 	amdgpu_ring_write(ring, addr & 0xfffffffc);
1119 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1120 	amdgpu_ring_write(ring, seq); /* reference */
1121 	amdgpu_ring_write(ring, 0xffffffff); /* mask */
1122 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1123 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1124 }
1125 
1126 
1127 /**
1128  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1129  *
1130  * @ring: amdgpu_ring pointer
1131  * @vmid: vmid number to use
1132  * @pd_addr: address
1133  *
1134  * Update the page table base and flush the VM TLB
1135  * using sDMA.
1136  */
1137 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1138 					 unsigned vmid, uint64_t pd_addr)
1139 {
1140 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1141 }
1142 
1143 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1144 				     uint32_t reg, uint32_t val)
1145 {
1146 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1147 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1148 	amdgpu_ring_write(ring, reg);
1149 	amdgpu_ring_write(ring, val);
1150 }
1151 
1152 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1153 					 uint32_t val, uint32_t mask)
1154 {
1155 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1156 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1157 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1158 	amdgpu_ring_write(ring, reg << 2);
1159 	amdgpu_ring_write(ring, 0);
1160 	amdgpu_ring_write(ring, val); /* reference */
1161 	amdgpu_ring_write(ring, mask); /* mask */
1162 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1163 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1164 }
1165 
1166 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1167 						   uint32_t reg0, uint32_t reg1,
1168 						   uint32_t ref, uint32_t mask)
1169 {
1170 	amdgpu_ring_emit_wreg(ring, reg0, ref);
1171 	/* wait for a cycle to reset vm_inv_eng*_ack */
1172 	amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1173 	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1174 }
1175 
1176 static int sdma_v5_2_early_init(void *handle)
1177 {
1178 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1179 
1180 	sdma_v5_2_set_ring_funcs(adev);
1181 	sdma_v5_2_set_buffer_funcs(adev);
1182 	sdma_v5_2_set_vm_pte_funcs(adev);
1183 	sdma_v5_2_set_irq_funcs(adev);
1184 	sdma_v5_2_set_mqd_funcs(adev);
1185 
1186 	return 0;
1187 }
1188 
1189 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1190 {
1191 	switch (seq_num) {
1192 	case 0:
1193 		return SOC15_IH_CLIENTID_SDMA0;
1194 	case 1:
1195 		return SOC15_IH_CLIENTID_SDMA1;
1196 	case 2:
1197 		return SOC15_IH_CLIENTID_SDMA2;
1198 	case 3:
1199 		return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1200 	default:
1201 		break;
1202 	}
1203 	return -EINVAL;
1204 }
1205 
1206 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1207 {
1208 	switch (seq_num) {
1209 	case 0:
1210 		return SDMA0_5_0__SRCID__SDMA_TRAP;
1211 	case 1:
1212 		return SDMA1_5_0__SRCID__SDMA_TRAP;
1213 	case 2:
1214 		return SDMA2_5_0__SRCID__SDMA_TRAP;
1215 	case 3:
1216 		return SDMA3_5_0__SRCID__SDMA_TRAP;
1217 	default:
1218 		break;
1219 	}
1220 	return -EINVAL;
1221 }
1222 
1223 static int sdma_v5_2_sw_init(void *handle)
1224 {
1225 	struct amdgpu_ring *ring;
1226 	int r, i;
1227 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1228 
1229 	/* SDMA trap event */
1230 	for (i = 0; i < adev->sdma.num_instances; i++) {
1231 		r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1232 				      sdma_v5_2_seq_to_trap_id(i),
1233 				      &adev->sdma.trap_irq);
1234 		if (r)
1235 			return r;
1236 	}
1237 
1238 	r = amdgpu_sdma_init_microcode(adev, 0, true);
1239 	if (r) {
1240 		DRM_ERROR("Failed to load sdma firmware!\n");
1241 		return r;
1242 	}
1243 
1244 	for (i = 0; i < adev->sdma.num_instances; i++) {
1245 		ring = &adev->sdma.instance[i].ring;
1246 		ring->ring_obj = NULL;
1247 		ring->use_doorbell = true;
1248 		ring->me = i;
1249 
1250 		DRM_INFO("use_doorbell being set to: [%s]\n",
1251 				ring->use_doorbell?"true":"false");
1252 
1253 		ring->doorbell_index =
1254 			(adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1255 
1256 		sprintf(ring->name, "sdma%d", i);
1257 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1258 				     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1259 				     AMDGPU_RING_PRIO_DEFAULT, NULL);
1260 		if (r)
1261 			return r;
1262 	}
1263 
1264 	return r;
1265 }
1266 
1267 static int sdma_v5_2_sw_fini(void *handle)
1268 {
1269 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1270 	int i;
1271 
1272 	for (i = 0; i < adev->sdma.num_instances; i++)
1273 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1274 
1275 	amdgpu_sdma_destroy_inst_ctx(adev, true);
1276 
1277 	return 0;
1278 }
1279 
1280 static int sdma_v5_2_hw_init(void *handle)
1281 {
1282 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1283 
1284 	return sdma_v5_2_start(adev);
1285 }
1286 
1287 static int sdma_v5_2_hw_fini(void *handle)
1288 {
1289 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1290 
1291 	if (amdgpu_sriov_vf(adev)) {
1292 		/* disable the scheduler for SDMA */
1293 		amdgpu_sdma_unset_buffer_funcs_helper(adev);
1294 		return 0;
1295 	}
1296 
1297 	sdma_v5_2_ctx_switch_enable(adev, false);
1298 	sdma_v5_2_enable(adev, false);
1299 
1300 	return 0;
1301 }
1302 
1303 static int sdma_v5_2_suspend(void *handle)
1304 {
1305 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1306 
1307 	return sdma_v5_2_hw_fini(adev);
1308 }
1309 
1310 static int sdma_v5_2_resume(void *handle)
1311 {
1312 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1313 
1314 	return sdma_v5_2_hw_init(adev);
1315 }
1316 
1317 static bool sdma_v5_2_is_idle(void *handle)
1318 {
1319 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1320 	u32 i;
1321 
1322 	for (i = 0; i < adev->sdma.num_instances; i++) {
1323 		u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1324 
1325 		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1326 			return false;
1327 	}
1328 
1329 	return true;
1330 }
1331 
1332 static int sdma_v5_2_wait_for_idle(void *handle)
1333 {
1334 	unsigned i;
1335 	u32 sdma0, sdma1, sdma2, sdma3;
1336 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1337 
1338 	for (i = 0; i < adev->usec_timeout; i++) {
1339 		sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1340 		sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1341 		sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1342 		sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1343 
1344 		if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1345 			return 0;
1346 		udelay(1);
1347 	}
1348 	return -ETIMEDOUT;
1349 }
1350 
1351 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1352 {
1353 	int i, r = 0;
1354 	struct amdgpu_device *adev = ring->adev;
1355 	u32 index = 0;
1356 	u64 sdma_gfx_preempt;
1357 
1358 	amdgpu_sdma_get_index_from_ring(ring, &index);
1359 	sdma_gfx_preempt =
1360 		sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1361 
1362 	/* assert preemption condition */
1363 	amdgpu_ring_set_preempt_cond_exec(ring, false);
1364 
1365 	/* emit the trailing fence */
1366 	ring->trail_seq += 1;
1367 	amdgpu_ring_alloc(ring, 10);
1368 	sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1369 				  ring->trail_seq, 0);
1370 	amdgpu_ring_commit(ring);
1371 
1372 	/* assert IB preemption */
1373 	WREG32(sdma_gfx_preempt, 1);
1374 
1375 	/* poll the trailing fence */
1376 	for (i = 0; i < adev->usec_timeout; i++) {
1377 		if (ring->trail_seq ==
1378 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1379 			break;
1380 		udelay(1);
1381 	}
1382 
1383 	if (i >= adev->usec_timeout) {
1384 		r = -EINVAL;
1385 		DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1386 	}
1387 
1388 	/* deassert IB preemption */
1389 	WREG32(sdma_gfx_preempt, 0);
1390 
1391 	/* deassert the preemption condition */
1392 	amdgpu_ring_set_preempt_cond_exec(ring, true);
1393 	return r;
1394 }
1395 
1396 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1397 					struct amdgpu_irq_src *source,
1398 					unsigned type,
1399 					enum amdgpu_interrupt_state state)
1400 {
1401 	u32 sdma_cntl;
1402 	u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1403 
1404 	if (!amdgpu_sriov_vf(adev)) {
1405 		sdma_cntl = RREG32(reg_offset);
1406 		sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1407 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1408 		WREG32(reg_offset, sdma_cntl);
1409 	}
1410 
1411 	return 0;
1412 }
1413 
1414 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1415 				      struct amdgpu_irq_src *source,
1416 				      struct amdgpu_iv_entry *entry)
1417 {
1418 	uint32_t mes_queue_id = entry->src_data[0];
1419 
1420 	DRM_DEBUG("IH: SDMA trap\n");
1421 
1422 	if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1423 		struct amdgpu_mes_queue *queue;
1424 
1425 		mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1426 
1427 		spin_lock(&adev->mes.queue_id_lock);
1428 		queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1429 		if (queue) {
1430 			DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1431 			amdgpu_fence_process(queue->ring);
1432 		}
1433 		spin_unlock(&adev->mes.queue_id_lock);
1434 		return 0;
1435 	}
1436 
1437 	switch (entry->client_id) {
1438 	case SOC15_IH_CLIENTID_SDMA0:
1439 		switch (entry->ring_id) {
1440 		case 0:
1441 			amdgpu_fence_process(&adev->sdma.instance[0].ring);
1442 			break;
1443 		case 1:
1444 			/* XXX compute */
1445 			break;
1446 		case 2:
1447 			/* XXX compute */
1448 			break;
1449 		case 3:
1450 			/* XXX page queue*/
1451 			break;
1452 		}
1453 		break;
1454 	case SOC15_IH_CLIENTID_SDMA1:
1455 		switch (entry->ring_id) {
1456 		case 0:
1457 			amdgpu_fence_process(&adev->sdma.instance[1].ring);
1458 			break;
1459 		case 1:
1460 			/* XXX compute */
1461 			break;
1462 		case 2:
1463 			/* XXX compute */
1464 			break;
1465 		case 3:
1466 			/* XXX page queue*/
1467 			break;
1468 		}
1469 		break;
1470 	case SOC15_IH_CLIENTID_SDMA2:
1471 		switch (entry->ring_id) {
1472 		case 0:
1473 			amdgpu_fence_process(&adev->sdma.instance[2].ring);
1474 			break;
1475 		case 1:
1476 			/* XXX compute */
1477 			break;
1478 		case 2:
1479 			/* XXX compute */
1480 			break;
1481 		case 3:
1482 			/* XXX page queue*/
1483 			break;
1484 		}
1485 		break;
1486 	case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1487 		switch (entry->ring_id) {
1488 		case 0:
1489 			amdgpu_fence_process(&adev->sdma.instance[3].ring);
1490 			break;
1491 		case 1:
1492 			/* XXX compute */
1493 			break;
1494 		case 2:
1495 			/* XXX compute */
1496 			break;
1497 		case 3:
1498 			/* XXX page queue*/
1499 			break;
1500 		}
1501 		break;
1502 	}
1503 	return 0;
1504 }
1505 
1506 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1507 					      struct amdgpu_irq_src *source,
1508 					      struct amdgpu_iv_entry *entry)
1509 {
1510 	return 0;
1511 }
1512 
1513 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1514 						       bool enable)
1515 {
1516 	uint32_t data, def;
1517 	int i;
1518 
1519 	for (i = 0; i < adev->sdma.num_instances; i++) {
1520 
1521 		if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1522 			adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1523 
1524 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1525 			/* Enable sdma clock gating */
1526 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1527 			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1528 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1529 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1530 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1531 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1532 				  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1533 			if (def != data)
1534 				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1535 		} else {
1536 			/* Disable sdma clock gating */
1537 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1538 			data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1539 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1540 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1541 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1542 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1543 				 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1544 			if (def != data)
1545 				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1546 		}
1547 	}
1548 }
1549 
1550 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1551 						      bool enable)
1552 {
1553 	uint32_t data, def;
1554 	int i;
1555 
1556 	for (i = 0; i < adev->sdma.num_instances; i++) {
1557 
1558 		if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1559 			adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1560 
1561 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1562 			/* Enable sdma mem light sleep */
1563 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1564 			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1565 			if (def != data)
1566 				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1567 
1568 		} else {
1569 			/* Disable sdma mem light sleep */
1570 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1571 			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1572 			if (def != data)
1573 				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1574 
1575 		}
1576 	}
1577 }
1578 
1579 static int sdma_v5_2_set_clockgating_state(void *handle,
1580 					   enum amd_clockgating_state state)
1581 {
1582 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1583 
1584 	if (amdgpu_sriov_vf(adev))
1585 		return 0;
1586 
1587 	switch (adev->ip_versions[SDMA0_HWIP][0]) {
1588 	case IP_VERSION(5, 2, 0):
1589 	case IP_VERSION(5, 2, 2):
1590 	case IP_VERSION(5, 2, 1):
1591 	case IP_VERSION(5, 2, 4):
1592 	case IP_VERSION(5, 2, 5):
1593 	case IP_VERSION(5, 2, 6):
1594 	case IP_VERSION(5, 2, 3):
1595 		sdma_v5_2_update_medium_grain_clock_gating(adev,
1596 				state == AMD_CG_STATE_GATE);
1597 		sdma_v5_2_update_medium_grain_light_sleep(adev,
1598 				state == AMD_CG_STATE_GATE);
1599 		break;
1600 	default:
1601 		break;
1602 	}
1603 
1604 	return 0;
1605 }
1606 
1607 static int sdma_v5_2_set_powergating_state(void *handle,
1608 					  enum amd_powergating_state state)
1609 {
1610 	return 0;
1611 }
1612 
1613 static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags)
1614 {
1615 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1616 	int data;
1617 
1618 	if (amdgpu_sriov_vf(adev))
1619 		*flags = 0;
1620 
1621 	/* AMD_CG_SUPPORT_SDMA_MGCG */
1622 	data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1623 	if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK))
1624 		*flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1625 
1626 	/* AMD_CG_SUPPORT_SDMA_LS */
1627 	data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1628 	if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1629 		*flags |= AMD_CG_SUPPORT_SDMA_LS;
1630 }
1631 
1632 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1633 	.name = "sdma_v5_2",
1634 	.early_init = sdma_v5_2_early_init,
1635 	.late_init = NULL,
1636 	.sw_init = sdma_v5_2_sw_init,
1637 	.sw_fini = sdma_v5_2_sw_fini,
1638 	.hw_init = sdma_v5_2_hw_init,
1639 	.hw_fini = sdma_v5_2_hw_fini,
1640 	.suspend = sdma_v5_2_suspend,
1641 	.resume = sdma_v5_2_resume,
1642 	.is_idle = sdma_v5_2_is_idle,
1643 	.wait_for_idle = sdma_v5_2_wait_for_idle,
1644 	.soft_reset = sdma_v5_2_soft_reset,
1645 	.set_clockgating_state = sdma_v5_2_set_clockgating_state,
1646 	.set_powergating_state = sdma_v5_2_set_powergating_state,
1647 	.get_clockgating_state = sdma_v5_2_get_clockgating_state,
1648 };
1649 
1650 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1651 	.type = AMDGPU_RING_TYPE_SDMA,
1652 	.align_mask = 0xf,
1653 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1654 	.support_64bit_ptrs = true,
1655 	.secure_submission_supported = true,
1656 	.vmhub = AMDGPU_GFXHUB_0,
1657 	.get_rptr = sdma_v5_2_ring_get_rptr,
1658 	.get_wptr = sdma_v5_2_ring_get_wptr,
1659 	.set_wptr = sdma_v5_2_ring_set_wptr,
1660 	.emit_frame_size =
1661 		5 + /* sdma_v5_2_ring_init_cond_exec */
1662 		6 + /* sdma_v5_2_ring_emit_hdp_flush */
1663 		3 + /* hdp_invalidate */
1664 		6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1665 		/* sdma_v5_2_ring_emit_vm_flush */
1666 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1667 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1668 		10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1669 	.emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1670 	.emit_ib = sdma_v5_2_ring_emit_ib,
1671 	.emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1672 	.emit_fence = sdma_v5_2_ring_emit_fence,
1673 	.emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1674 	.emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1675 	.emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1676 	.test_ring = sdma_v5_2_ring_test_ring,
1677 	.test_ib = sdma_v5_2_ring_test_ib,
1678 	.insert_nop = sdma_v5_2_ring_insert_nop,
1679 	.pad_ib = sdma_v5_2_ring_pad_ib,
1680 	.emit_wreg = sdma_v5_2_ring_emit_wreg,
1681 	.emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1682 	.emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1683 	.init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1684 	.patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1685 	.preempt_ib = sdma_v5_2_ring_preempt_ib,
1686 };
1687 
1688 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1689 {
1690 	int i;
1691 
1692 	for (i = 0; i < adev->sdma.num_instances; i++) {
1693 		adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1694 		adev->sdma.instance[i].ring.me = i;
1695 	}
1696 }
1697 
1698 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1699 	.set = sdma_v5_2_set_trap_irq_state,
1700 	.process = sdma_v5_2_process_trap_irq,
1701 };
1702 
1703 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1704 	.process = sdma_v5_2_process_illegal_inst_irq,
1705 };
1706 
1707 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1708 {
1709 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1710 					adev->sdma.num_instances;
1711 	adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1712 	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1713 }
1714 
1715 /**
1716  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1717  *
1718  * @ib: indirect buffer to copy to
1719  * @src_offset: src GPU address
1720  * @dst_offset: dst GPU address
1721  * @byte_count: number of bytes to xfer
1722  * @tmz: if a secure copy should be used
1723  *
1724  * Copy GPU buffers using the DMA engine.
1725  * Used by the amdgpu ttm implementation to move pages if
1726  * registered as the asic copy callback.
1727  */
1728 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1729 				       uint64_t src_offset,
1730 				       uint64_t dst_offset,
1731 				       uint32_t byte_count,
1732 				       bool tmz)
1733 {
1734 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1735 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1736 		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1737 	ib->ptr[ib->length_dw++] = byte_count - 1;
1738 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1739 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1740 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1741 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1742 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1743 }
1744 
1745 /**
1746  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1747  *
1748  * @ib: indirect buffer to fill
1749  * @src_data: value to write to buffer
1750  * @dst_offset: dst GPU address
1751  * @byte_count: number of bytes to xfer
1752  *
1753  * Fill GPU buffers using the DMA engine.
1754  */
1755 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1756 				       uint32_t src_data,
1757 				       uint64_t dst_offset,
1758 				       uint32_t byte_count)
1759 {
1760 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1761 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1762 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1763 	ib->ptr[ib->length_dw++] = src_data;
1764 	ib->ptr[ib->length_dw++] = byte_count - 1;
1765 }
1766 
1767 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1768 	.copy_max_bytes = 0x400000,
1769 	.copy_num_dw = 7,
1770 	.emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1771 
1772 	.fill_max_bytes = 0x400000,
1773 	.fill_num_dw = 5,
1774 	.emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1775 };
1776 
1777 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1778 {
1779 	if (adev->mman.buffer_funcs == NULL) {
1780 		adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1781 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1782 	}
1783 }
1784 
1785 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1786 	.copy_pte_num_dw = 7,
1787 	.copy_pte = sdma_v5_2_vm_copy_pte,
1788 	.write_pte = sdma_v5_2_vm_write_pte,
1789 	.set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1790 };
1791 
1792 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1793 {
1794 	unsigned i;
1795 
1796 	if (adev->vm_manager.vm_pte_funcs == NULL) {
1797 		adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1798 		for (i = 0; i < adev->sdma.num_instances; i++) {
1799 			adev->vm_manager.vm_pte_scheds[i] =
1800 				&adev->sdma.instance[i].ring.sched;
1801 		}
1802 		adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1803 	}
1804 }
1805 
1806 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1807 	.type = AMD_IP_BLOCK_TYPE_SDMA,
1808 	.major = 5,
1809 	.minor = 2,
1810 	.rev = 0,
1811 	.funcs = &sdma_v5_2_ip_funcs,
1812 };
1813