1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32 
33 #include "gc/gc_10_3_0_offset.h"
34 #include "gc/gc_10_3_0_sh_mask.h"
35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
39 
40 #include "soc15_common.h"
41 #include "soc15.h"
42 #include "navi10_sdma_pkt_open.h"
43 #include "nbio_v2_3.h"
44 #include "sdma_common.h"
45 #include "sdma_v5_2.h"
46 
47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
51 
52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
54 
55 #define SDMA1_REG_OFFSET 0x600
56 #define SDMA3_REG_OFFSET 0x400
57 #define SDMA0_HYP_DEC_REG_START 0x5880
58 #define SDMA0_HYP_DEC_REG_END 0x5893
59 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
60 
61 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
62 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
63 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
64 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
65 
66 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
67 {
68 	u32 base;
69 
70 	if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
71 	    internal_offset <= SDMA0_HYP_DEC_REG_END) {
72 		base = adev->reg_offset[GC_HWIP][0][1];
73 		if (instance != 0)
74 			internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
75 	} else {
76 		if (instance < 2) {
77 			base = adev->reg_offset[GC_HWIP][0][0];
78 			if (instance == 1)
79 				internal_offset += SDMA1_REG_OFFSET;
80 		} else {
81 			base = adev->reg_offset[GC_HWIP][0][2];
82 			if (instance == 3)
83 				internal_offset += SDMA3_REG_OFFSET;
84 		}
85 	}
86 
87 	return base + internal_offset;
88 }
89 
90 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
91 {
92 	int err = 0;
93 	const struct sdma_firmware_header_v1_0 *hdr;
94 
95 	err = amdgpu_ucode_validate(sdma_inst->fw);
96 	if (err)
97 		return err;
98 
99 	hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
100 	sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
101 	sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
102 
103 	if (sdma_inst->feature_version >= 20)
104 		sdma_inst->burst_nop = true;
105 
106 	return 0;
107 }
108 
109 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
110 {
111 	release_firmware(adev->sdma.instance[0].fw);
112 
113 	memset((void *)adev->sdma.instance, 0,
114 	       sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
115 }
116 
117 /**
118  * sdma_v5_2_init_microcode - load ucode images from disk
119  *
120  * @adev: amdgpu_device pointer
121  *
122  * Use the firmware interface to load the ucode images into
123  * the driver (not loaded into hw).
124  * Returns 0 on success, error on failure.
125  */
126 
127 // emulation only, won't work on real chip
128 // navi10 real chip need to use PSP to load firmware
129 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
130 {
131 	const char *chip_name;
132 	char fw_name[40];
133 	int err = 0, i;
134 	struct amdgpu_firmware_info *info = NULL;
135 	const struct common_firmware_header *header = NULL;
136 
137 	DRM_DEBUG("\n");
138 
139 	switch (adev->ip_versions[SDMA0_HWIP][0]) {
140 	case IP_VERSION(5, 2, 0):
141 		chip_name = "sienna_cichlid";
142 		break;
143 	case IP_VERSION(5, 2, 2):
144 		chip_name = "navy_flounder";
145 		break;
146 	case IP_VERSION(5, 2, 1):
147 		chip_name = "vangogh";
148 		break;
149 	case IP_VERSION(5, 2, 4):
150 		chip_name = "dimgrey_cavefish";
151 		break;
152 	case IP_VERSION(5, 2, 5):
153 		chip_name = "beige_goby";
154 		break;
155 	case IP_VERSION(5, 2, 3):
156 		chip_name = "yellow_carp";
157 		break;
158 	default:
159 		BUG();
160 	}
161 
162 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
163 
164 	err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
165 	if (err)
166 		goto out;
167 
168 	err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
169 	if (err)
170 		goto out;
171 
172 	for (i = 1; i < adev->sdma.num_instances; i++)
173 		memcpy((void *)&adev->sdma.instance[i],
174 		       (void *)&adev->sdma.instance[0],
175 		       sizeof(struct amdgpu_sdma_instance));
176 
177 	if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 0)))
178 		return 0;
179 
180 	DRM_DEBUG("psp_load == '%s'\n",
181 		  adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
182 
183 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
184 		for (i = 0; i < adev->sdma.num_instances; i++) {
185 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
186 			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
187 			info->fw = adev->sdma.instance[i].fw;
188 			header = (const struct common_firmware_header *)info->fw->data;
189 			adev->firmware.fw_size +=
190 				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
191 		}
192 	}
193 
194 out:
195 	if (err) {
196 		DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
197 		sdma_v5_2_destroy_inst_ctx(adev);
198 	}
199 	return err;
200 }
201 
202 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
203 {
204 	unsigned ret;
205 
206 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
207 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
208 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
209 	amdgpu_ring_write(ring, 1);
210 	ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
211 	amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
212 
213 	return ret;
214 }
215 
216 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
217 					   unsigned offset)
218 {
219 	unsigned cur;
220 
221 	BUG_ON(offset > ring->buf_mask);
222 	BUG_ON(ring->ring[offset] != 0x55aa55aa);
223 
224 	cur = (ring->wptr - 1) & ring->buf_mask;
225 	if (cur > offset)
226 		ring->ring[offset] = cur - offset;
227 	else
228 		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
229 }
230 
231 /**
232  * sdma_v5_2_ring_get_rptr - get the current read pointer
233  *
234  * @ring: amdgpu ring pointer
235  *
236  * Get the current rptr from the hardware (NAVI10+).
237  */
238 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
239 {
240 	u64 *rptr;
241 
242 	/* XXX check if swapping is necessary on BE */
243 	rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
244 
245 	DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
246 	return ((*rptr) >> 2);
247 }
248 
249 /**
250  * sdma_v5_2_ring_get_wptr - get the current write pointer
251  *
252  * @ring: amdgpu ring pointer
253  *
254  * Get the current wptr from the hardware (NAVI10+).
255  */
256 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
257 {
258 	struct amdgpu_device *adev = ring->adev;
259 	u64 wptr;
260 
261 	if (ring->use_doorbell) {
262 		/* XXX check if swapping is necessary on BE */
263 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
264 		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
265 	} else {
266 		wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
267 		wptr = wptr << 32;
268 		wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
269 		DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
270 	}
271 
272 	return wptr >> 2;
273 }
274 
275 /**
276  * sdma_v5_2_ring_set_wptr - commit the write pointer
277  *
278  * @ring: amdgpu ring pointer
279  *
280  * Write the wptr back to the hardware (NAVI10+).
281  */
282 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
283 {
284 	struct amdgpu_device *adev = ring->adev;
285 
286 	DRM_DEBUG("Setting write pointer\n");
287 	if (ring->use_doorbell) {
288 		DRM_DEBUG("Using doorbell -- "
289 				"wptr_offs == 0x%08x "
290 				"lower_32_bits(ring->wptr) << 2 == 0x%08x "
291 				"upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
292 				ring->wptr_offs,
293 				lower_32_bits(ring->wptr << 2),
294 				upper_32_bits(ring->wptr << 2));
295 		/* XXX check if swapping is necessary on BE */
296 		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
297 		adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
298 		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
299 				ring->doorbell_index, ring->wptr << 2);
300 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
301 	} else {
302 		DRM_DEBUG("Not using doorbell -- "
303 				"mmSDMA%i_GFX_RB_WPTR == 0x%08x "
304 				"mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
305 				ring->me,
306 				lower_32_bits(ring->wptr << 2),
307 				ring->me,
308 				upper_32_bits(ring->wptr << 2));
309 		WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
310 			lower_32_bits(ring->wptr << 2));
311 		WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
312 			upper_32_bits(ring->wptr << 2));
313 	}
314 }
315 
316 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
317 {
318 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
319 	int i;
320 
321 	for (i = 0; i < count; i++)
322 		if (sdma && sdma->burst_nop && (i == 0))
323 			amdgpu_ring_write(ring, ring->funcs->nop |
324 				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
325 		else
326 			amdgpu_ring_write(ring, ring->funcs->nop);
327 }
328 
329 /**
330  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
331  *
332  * @ring: amdgpu ring pointer
333  * @job: job to retrieve vmid from
334  * @ib: IB object to schedule
335  * @flags: unused
336  *
337  * Schedule an IB in the DMA ring.
338  */
339 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
340 				   struct amdgpu_job *job,
341 				   struct amdgpu_ib *ib,
342 				   uint32_t flags)
343 {
344 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
345 	uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
346 
347 	/* An IB packet must end on a 8 DW boundary--the next dword
348 	 * must be on a 8-dword boundary. Our IB packet below is 6
349 	 * dwords long, thus add x number of NOPs, such that, in
350 	 * modular arithmetic,
351 	 * wptr + 6 + x = 8k, k >= 0, which in C is,
352 	 * (wptr + 6 + x) % 8 = 0.
353 	 * The expression below, is a solution of x.
354 	 */
355 	sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
356 
357 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
358 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
359 	/* base must be 32 byte aligned */
360 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
361 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
362 	amdgpu_ring_write(ring, ib->length_dw);
363 	amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
364 	amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
365 }
366 
367 /**
368  * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
369  *
370  * @ring: amdgpu ring pointer
371  *
372  * flush the IB by graphics cache rinse.
373  */
374 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
375 {
376 	uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |
377 			    SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV |
378 			    SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
379 			    SDMA_GCR_GLI_INV(1);
380 
381 	/* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
382 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
383 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
384 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
385 			SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
386 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
387 			SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
388 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
389 			SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
390 }
391 
392 /**
393  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
394  *
395  * @ring: amdgpu ring pointer
396  *
397  * Emit an hdp flush packet on the requested DMA ring.
398  */
399 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
400 {
401 	struct amdgpu_device *adev = ring->adev;
402 	u32 ref_and_mask = 0;
403 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
404 
405 	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
406 
407 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
408 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
409 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
410 	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
411 	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
412 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
413 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
414 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
415 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
416 }
417 
418 /**
419  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
420  *
421  * @ring: amdgpu ring pointer
422  * @addr: address
423  * @seq: sequence number
424  * @flags: fence related flags
425  *
426  * Add a DMA fence packet to the ring to write
427  * the fence seq number and DMA trap packet to generate
428  * an interrupt if needed.
429  */
430 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
431 				      unsigned flags)
432 {
433 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
434 	/* write the fence */
435 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
436 			  SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
437 	/* zero in first two bits */
438 	BUG_ON(addr & 0x3);
439 	amdgpu_ring_write(ring, lower_32_bits(addr));
440 	amdgpu_ring_write(ring, upper_32_bits(addr));
441 	amdgpu_ring_write(ring, lower_32_bits(seq));
442 
443 	/* optionally write high bits as well */
444 	if (write64bit) {
445 		addr += 4;
446 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
447 				  SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
448 		/* zero in first two bits */
449 		BUG_ON(addr & 0x3);
450 		amdgpu_ring_write(ring, lower_32_bits(addr));
451 		amdgpu_ring_write(ring, upper_32_bits(addr));
452 		amdgpu_ring_write(ring, upper_32_bits(seq));
453 	}
454 
455 	if (flags & AMDGPU_FENCE_FLAG_INT) {
456 		/* generate an interrupt */
457 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
458 		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
459 	}
460 }
461 
462 
463 /**
464  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
465  *
466  * @adev: amdgpu_device pointer
467  *
468  * Stop the gfx async dma ring buffers.
469  */
470 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
471 {
472 	struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
473 	struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
474 	struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
475 	struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
476 	u32 rb_cntl, ib_cntl;
477 	int i;
478 
479 	if ((adev->mman.buffer_funcs_ring == sdma0) ||
480 	    (adev->mman.buffer_funcs_ring == sdma1) ||
481 	    (adev->mman.buffer_funcs_ring == sdma2) ||
482 	    (adev->mman.buffer_funcs_ring == sdma3))
483 		amdgpu_ttm_set_buffer_funcs_status(adev, false);
484 
485 	for (i = 0; i < adev->sdma.num_instances; i++) {
486 		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
487 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
488 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
489 		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
490 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
491 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
492 	}
493 }
494 
495 /**
496  * sdma_v5_2_rlc_stop - stop the compute async dma engines
497  *
498  * @adev: amdgpu_device pointer
499  *
500  * Stop the compute async dma queues.
501  */
502 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
503 {
504 	/* XXX todo */
505 }
506 
507 /**
508  * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
509  *
510  * @adev: amdgpu_device pointer
511  * @enable: enable/disable the DMA MEs context switch.
512  *
513  * Halt or unhalt the async dma engines context switch.
514  */
515 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
516 {
517 	u32 f32_cntl, phase_quantum = 0;
518 	int i;
519 
520 	if (amdgpu_sdma_phase_quantum) {
521 		unsigned value = amdgpu_sdma_phase_quantum;
522 		unsigned unit = 0;
523 
524 		while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
525 				SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
526 			value = (value + 1) >> 1;
527 			unit++;
528 		}
529 		if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
530 			    SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
531 			value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
532 				 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
533 			unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
534 				SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
535 			WARN_ONCE(1,
536 			"clamping sdma_phase_quantum to %uK clock cycles\n",
537 				  value << unit);
538 		}
539 		phase_quantum =
540 			value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
541 			unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
542 	}
543 
544 	for (i = 0; i < adev->sdma.num_instances; i++) {
545 		f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
546 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
547 				AUTO_CTXSW_ENABLE, enable ? 1 : 0);
548 		if (enable && amdgpu_sdma_phase_quantum) {
549 			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
550 			       phase_quantum);
551 			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
552 			       phase_quantum);
553 			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
554 			       phase_quantum);
555 		}
556 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
557 	}
558 
559 }
560 
561 /**
562  * sdma_v5_2_enable - stop the async dma engines
563  *
564  * @adev: amdgpu_device pointer
565  * @enable: enable/disable the DMA MEs.
566  *
567  * Halt or unhalt the async dma engines.
568  */
569 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
570 {
571 	u32 f32_cntl;
572 	int i;
573 
574 	if (!enable) {
575 		sdma_v5_2_gfx_stop(adev);
576 		sdma_v5_2_rlc_stop(adev);
577 	}
578 
579 	for (i = 0; i < adev->sdma.num_instances; i++) {
580 		f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
581 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
582 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
583 	}
584 }
585 
586 /**
587  * sdma_v5_2_gfx_resume - setup and start the async dma engines
588  *
589  * @adev: amdgpu_device pointer
590  *
591  * Set up the gfx DMA ring buffers and enable them.
592  * Returns 0 for success, error for failure.
593  */
594 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
595 {
596 	struct amdgpu_ring *ring;
597 	u32 rb_cntl, ib_cntl;
598 	u32 rb_bufsz;
599 	u32 wb_offset;
600 	u32 doorbell;
601 	u32 doorbell_offset;
602 	u32 temp;
603 	u32 wptr_poll_cntl;
604 	u64 wptr_gpu_addr;
605 	int i, r;
606 
607 	for (i = 0; i < adev->sdma.num_instances; i++) {
608 		ring = &adev->sdma.instance[i].ring;
609 		wb_offset = (ring->rptr_offs * 4);
610 
611 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
612 
613 		/* Set ring buffer size in dwords */
614 		rb_bufsz = order_base_2(ring->ring_size / 4);
615 		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
616 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
617 #ifdef __BIG_ENDIAN
618 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
619 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
620 					RPTR_WRITEBACK_SWAP_ENABLE, 1);
621 #endif
622 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
623 
624 		/* Initialize the ring buffer's read and write pointers */
625 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
626 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
627 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
628 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
629 
630 		/* setup the wptr shadow polling */
631 		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
632 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
633 		       lower_32_bits(wptr_gpu_addr));
634 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
635 		       upper_32_bits(wptr_gpu_addr));
636 		wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
637 							 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
638 		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
639 					       SDMA0_GFX_RB_WPTR_POLL_CNTL,
640 					       F32_POLL_ENABLE, 1);
641 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
642 		       wptr_poll_cntl);
643 
644 		/* set the wb address whether it's enabled or not */
645 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
646 		       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
647 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
648 		       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
649 
650 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
651 
652 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
653 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
654 
655 		ring->wptr = 0;
656 
657 		/* before programing wptr to a less value, need set minor_ptr_update first */
658 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
659 
660 		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
661 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
662 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
663 		}
664 
665 		doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
666 		doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
667 
668 		if (ring->use_doorbell) {
669 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
670 			doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
671 					OFFSET, ring->doorbell_index);
672 		} else {
673 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
674 		}
675 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
676 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
677 
678 		adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
679 						      ring->doorbell_index,
680 						      adev->doorbell_index.sdma_doorbell_range);
681 
682 		if (amdgpu_sriov_vf(adev))
683 			sdma_v5_2_ring_set_wptr(ring);
684 
685 		/* set minor_ptr_update to 0 after wptr programed */
686 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
687 
688 		/* set utc l1 enable flag always to 1 */
689 		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
690 		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
691 
692 		/* enable MCBP */
693 		temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
694 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
695 
696 		/* Set up RESP_MODE to non-copy addresses */
697 		temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
698 		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
699 		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
700 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
701 
702 		/* program default cache read and write policy */
703 		temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
704 		/* clean read policy and write policy bits */
705 		temp &= 0xFF0FFF;
706 		temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
707 			 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
708 			 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
709 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
710 
711 		if (!amdgpu_sriov_vf(adev)) {
712 			/* unhalt engine */
713 			temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
714 			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
715 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
716 		}
717 
718 		/* enable DMA RB */
719 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
720 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
721 
722 		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
723 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
724 #ifdef __BIG_ENDIAN
725 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
726 #endif
727 		/* enable DMA IBs */
728 		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
729 
730 		ring->sched.ready = true;
731 
732 		if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
733 			sdma_v5_2_ctx_switch_enable(adev, true);
734 			sdma_v5_2_enable(adev, true);
735 		}
736 
737 		r = amdgpu_ring_test_ring(ring);
738 		if (r) {
739 			ring->sched.ready = false;
740 			return r;
741 		}
742 
743 		if (adev->mman.buffer_funcs_ring == ring)
744 			amdgpu_ttm_set_buffer_funcs_status(adev, true);
745 	}
746 
747 	return 0;
748 }
749 
750 /**
751  * sdma_v5_2_rlc_resume - setup and start the async dma engines
752  *
753  * @adev: amdgpu_device pointer
754  *
755  * Set up the compute DMA queues and enable them.
756  * Returns 0 for success, error for failure.
757  */
758 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
759 {
760 	return 0;
761 }
762 
763 /**
764  * sdma_v5_2_load_microcode - load the sDMA ME ucode
765  *
766  * @adev: amdgpu_device pointer
767  *
768  * Loads the sDMA0/1/2/3 ucode.
769  * Returns 0 for success, -EINVAL if the ucode is not available.
770  */
771 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
772 {
773 	const struct sdma_firmware_header_v1_0 *hdr;
774 	const __le32 *fw_data;
775 	u32 fw_size;
776 	int i, j;
777 
778 	/* halt the MEs */
779 	sdma_v5_2_enable(adev, false);
780 
781 	for (i = 0; i < adev->sdma.num_instances; i++) {
782 		if (!adev->sdma.instance[i].fw)
783 			return -EINVAL;
784 
785 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
786 		amdgpu_ucode_print_sdma_hdr(&hdr->header);
787 		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
788 
789 		fw_data = (const __le32 *)
790 			(adev->sdma.instance[i].fw->data +
791 				le32_to_cpu(hdr->header.ucode_array_offset_bytes));
792 
793 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
794 
795 		for (j = 0; j < fw_size; j++) {
796 			if (amdgpu_emu_mode == 1 && j % 500 == 0)
797 				msleep(1);
798 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
799 		}
800 
801 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
802 	}
803 
804 	return 0;
805 }
806 
807 static int sdma_v5_2_soft_reset(void *handle)
808 {
809 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
810 	u32 grbm_soft_reset;
811 	u32 tmp;
812 	int i;
813 
814 	for (i = 0; i < adev->sdma.num_instances; i++) {
815 		grbm_soft_reset = REG_SET_FIELD(0,
816 						GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
817 						1);
818 		grbm_soft_reset <<= i;
819 
820 		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
821 		tmp |= grbm_soft_reset;
822 		DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
823 		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
824 		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
825 
826 		udelay(50);
827 
828 		tmp &= ~grbm_soft_reset;
829 		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
830 		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
831 
832 		udelay(50);
833 	}
834 
835 	return 0;
836 }
837 
838 /**
839  * sdma_v5_2_start - setup and start the async dma engines
840  *
841  * @adev: amdgpu_device pointer
842  *
843  * Set up the DMA engines and enable them.
844  * Returns 0 for success, error for failure.
845  */
846 static int sdma_v5_2_start(struct amdgpu_device *adev)
847 {
848 	int r = 0;
849 
850 	if (amdgpu_sriov_vf(adev)) {
851 		sdma_v5_2_ctx_switch_enable(adev, false);
852 		sdma_v5_2_enable(adev, false);
853 
854 		/* set RB registers */
855 		r = sdma_v5_2_gfx_resume(adev);
856 		return r;
857 	}
858 
859 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
860 		r = sdma_v5_2_load_microcode(adev);
861 		if (r)
862 			return r;
863 
864 		/* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
865 		if (amdgpu_emu_mode == 1)
866 			msleep(1000);
867 	}
868 
869 	/* TODO: check whether can submit a doorbell request to raise
870 	 * a doorbell fence to exit gfxoff.
871 	 */
872 	if (adev->in_s0ix)
873 		amdgpu_gfx_off_ctrl(adev, false);
874 
875 	sdma_v5_2_soft_reset(adev);
876 	/* unhalt the MEs */
877 	sdma_v5_2_enable(adev, true);
878 	/* enable sdma ring preemption */
879 	sdma_v5_2_ctx_switch_enable(adev, true);
880 
881 	/* start the gfx rings and rlc compute queues */
882 	r = sdma_v5_2_gfx_resume(adev);
883 	if (adev->in_s0ix)
884 		amdgpu_gfx_off_ctrl(adev, true);
885 	if (r)
886 		return r;
887 	r = sdma_v5_2_rlc_resume(adev);
888 
889 	return r;
890 }
891 
892 /**
893  * sdma_v5_2_ring_test_ring - simple async dma engine test
894  *
895  * @ring: amdgpu_ring structure holding ring information
896  *
897  * Test the DMA engine by writing using it to write an
898  * value to memory.
899  * Returns 0 for success, error for failure.
900  */
901 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
902 {
903 	struct amdgpu_device *adev = ring->adev;
904 	unsigned i;
905 	unsigned index;
906 	int r;
907 	u32 tmp;
908 	u64 gpu_addr;
909 
910 	r = amdgpu_device_wb_get(adev, &index);
911 	if (r) {
912 		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
913 		return r;
914 	}
915 
916 	gpu_addr = adev->wb.gpu_addr + (index * 4);
917 	tmp = 0xCAFEDEAD;
918 	adev->wb.wb[index] = cpu_to_le32(tmp);
919 
920 	r = amdgpu_ring_alloc(ring, 5);
921 	if (r) {
922 		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
923 		amdgpu_device_wb_free(adev, index);
924 		return r;
925 	}
926 
927 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
928 			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
929 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
930 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
931 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
932 	amdgpu_ring_write(ring, 0xDEADBEEF);
933 	amdgpu_ring_commit(ring);
934 
935 	for (i = 0; i < adev->usec_timeout; i++) {
936 		tmp = le32_to_cpu(adev->wb.wb[index]);
937 		if (tmp == 0xDEADBEEF)
938 			break;
939 		if (amdgpu_emu_mode == 1)
940 			msleep(1);
941 		else
942 			udelay(1);
943 	}
944 
945 	if (i >= adev->usec_timeout)
946 		r = -ETIMEDOUT;
947 
948 	amdgpu_device_wb_free(adev, index);
949 
950 	return r;
951 }
952 
953 /**
954  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
955  *
956  * @ring: amdgpu_ring structure holding ring information
957  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
958  *
959  * Test a simple IB in the DMA ring.
960  * Returns 0 on success, error on failure.
961  */
962 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
963 {
964 	struct amdgpu_device *adev = ring->adev;
965 	struct amdgpu_ib ib;
966 	struct dma_fence *f = NULL;
967 	unsigned index;
968 	long r;
969 	u32 tmp = 0;
970 	u64 gpu_addr;
971 
972 	r = amdgpu_device_wb_get(adev, &index);
973 	if (r) {
974 		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
975 		return r;
976 	}
977 
978 	gpu_addr = adev->wb.gpu_addr + (index * 4);
979 	tmp = 0xCAFEDEAD;
980 	adev->wb.wb[index] = cpu_to_le32(tmp);
981 	memset(&ib, 0, sizeof(ib));
982 	r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
983 	if (r) {
984 		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
985 		goto err0;
986 	}
987 
988 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
989 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
990 	ib.ptr[1] = lower_32_bits(gpu_addr);
991 	ib.ptr[2] = upper_32_bits(gpu_addr);
992 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
993 	ib.ptr[4] = 0xDEADBEEF;
994 	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
995 	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
996 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
997 	ib.length_dw = 8;
998 
999 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1000 	if (r)
1001 		goto err1;
1002 
1003 	r = dma_fence_wait_timeout(f, false, timeout);
1004 	if (r == 0) {
1005 		DRM_ERROR("amdgpu: IB test timed out\n");
1006 		r = -ETIMEDOUT;
1007 		goto err1;
1008 	} else if (r < 0) {
1009 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1010 		goto err1;
1011 	}
1012 	tmp = le32_to_cpu(adev->wb.wb[index]);
1013 	if (tmp == 0xDEADBEEF)
1014 		r = 0;
1015 	else
1016 		r = -EINVAL;
1017 
1018 err1:
1019 	amdgpu_ib_free(adev, &ib, NULL);
1020 	dma_fence_put(f);
1021 err0:
1022 	amdgpu_device_wb_free(adev, index);
1023 	return r;
1024 }
1025 
1026 
1027 /**
1028  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1029  *
1030  * @ib: indirect buffer to fill with commands
1031  * @pe: addr of the page entry
1032  * @src: src addr to copy from
1033  * @count: number of page entries to update
1034  *
1035  * Update PTEs by copying them from the GART using sDMA.
1036  */
1037 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1038 				  uint64_t pe, uint64_t src,
1039 				  unsigned count)
1040 {
1041 	unsigned bytes = count * 8;
1042 
1043 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1044 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1045 	ib->ptr[ib->length_dw++] = bytes - 1;
1046 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1047 	ib->ptr[ib->length_dw++] = lower_32_bits(src);
1048 	ib->ptr[ib->length_dw++] = upper_32_bits(src);
1049 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1050 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1051 
1052 }
1053 
1054 /**
1055  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1056  *
1057  * @ib: indirect buffer to fill with commands
1058  * @pe: addr of the page entry
1059  * @value: dst addr to write into pe
1060  * @count: number of page entries to update
1061  * @incr: increase next addr by incr bytes
1062  *
1063  * Update PTEs by writing them manually using sDMA.
1064  */
1065 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1066 				   uint64_t value, unsigned count,
1067 				   uint32_t incr)
1068 {
1069 	unsigned ndw = count * 2;
1070 
1071 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1072 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1073 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1074 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1075 	ib->ptr[ib->length_dw++] = ndw - 1;
1076 	for (; ndw > 0; ndw -= 2) {
1077 		ib->ptr[ib->length_dw++] = lower_32_bits(value);
1078 		ib->ptr[ib->length_dw++] = upper_32_bits(value);
1079 		value += incr;
1080 	}
1081 }
1082 
1083 /**
1084  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1085  *
1086  * @ib: indirect buffer to fill with commands
1087  * @pe: addr of the page entry
1088  * @addr: dst addr to write into pe
1089  * @count: number of page entries to update
1090  * @incr: increase next addr by incr bytes
1091  * @flags: access flags
1092  *
1093  * Update the page tables using sDMA.
1094  */
1095 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1096 				     uint64_t pe,
1097 				     uint64_t addr, unsigned count,
1098 				     uint32_t incr, uint64_t flags)
1099 {
1100 	/* for physically contiguous pages (vram) */
1101 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1102 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1103 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1104 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1105 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1106 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1107 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1108 	ib->ptr[ib->length_dw++] = incr; /* increment size */
1109 	ib->ptr[ib->length_dw++] = 0;
1110 	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1111 }
1112 
1113 /**
1114  * sdma_v5_2_ring_pad_ib - pad the IB
1115  *
1116  * @ib: indirect buffer to fill with padding
1117  * @ring: amdgpu_ring structure holding ring information
1118  *
1119  * Pad the IB with NOPs to a boundary multiple of 8.
1120  */
1121 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1122 {
1123 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1124 	u32 pad_count;
1125 	int i;
1126 
1127 	pad_count = (-ib->length_dw) & 0x7;
1128 	for (i = 0; i < pad_count; i++)
1129 		if (sdma && sdma->burst_nop && (i == 0))
1130 			ib->ptr[ib->length_dw++] =
1131 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1132 				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1133 		else
1134 			ib->ptr[ib->length_dw++] =
1135 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1136 }
1137 
1138 
1139 /**
1140  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1141  *
1142  * @ring: amdgpu_ring pointer
1143  *
1144  * Make sure all previous operations are completed (CIK).
1145  */
1146 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1147 {
1148 	uint32_t seq = ring->fence_drv.sync_seq;
1149 	uint64_t addr = ring->fence_drv.gpu_addr;
1150 
1151 	/* wait for idle */
1152 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1153 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1154 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1155 			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1156 	amdgpu_ring_write(ring, addr & 0xfffffffc);
1157 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1158 	amdgpu_ring_write(ring, seq); /* reference */
1159 	amdgpu_ring_write(ring, 0xffffffff); /* mask */
1160 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1161 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1162 }
1163 
1164 
1165 /**
1166  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1167  *
1168  * @ring: amdgpu_ring pointer
1169  * @vmid: vmid number to use
1170  * @pd_addr: address
1171  *
1172  * Update the page table base and flush the VM TLB
1173  * using sDMA.
1174  */
1175 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1176 					 unsigned vmid, uint64_t pd_addr)
1177 {
1178 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1179 }
1180 
1181 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1182 				     uint32_t reg, uint32_t val)
1183 {
1184 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1185 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1186 	amdgpu_ring_write(ring, reg);
1187 	amdgpu_ring_write(ring, val);
1188 }
1189 
1190 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1191 					 uint32_t val, uint32_t mask)
1192 {
1193 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1194 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1195 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1196 	amdgpu_ring_write(ring, reg << 2);
1197 	amdgpu_ring_write(ring, 0);
1198 	amdgpu_ring_write(ring, val); /* reference */
1199 	amdgpu_ring_write(ring, mask); /* mask */
1200 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1201 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1202 }
1203 
1204 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1205 						   uint32_t reg0, uint32_t reg1,
1206 						   uint32_t ref, uint32_t mask)
1207 {
1208 	amdgpu_ring_emit_wreg(ring, reg0, ref);
1209 	/* wait for a cycle to reset vm_inv_eng*_ack */
1210 	amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1211 	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1212 }
1213 
1214 static int sdma_v5_2_early_init(void *handle)
1215 {
1216 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1217 
1218 	sdma_v5_2_set_ring_funcs(adev);
1219 	sdma_v5_2_set_buffer_funcs(adev);
1220 	sdma_v5_2_set_vm_pte_funcs(adev);
1221 	sdma_v5_2_set_irq_funcs(adev);
1222 
1223 	return 0;
1224 }
1225 
1226 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1227 {
1228 	switch (seq_num) {
1229 	case 0:
1230 		return SOC15_IH_CLIENTID_SDMA0;
1231 	case 1:
1232 		return SOC15_IH_CLIENTID_SDMA1;
1233 	case 2:
1234 		return SOC15_IH_CLIENTID_SDMA2;
1235 	case 3:
1236 		return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1237 	default:
1238 		break;
1239 	}
1240 	return -EINVAL;
1241 }
1242 
1243 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1244 {
1245 	switch (seq_num) {
1246 	case 0:
1247 		return SDMA0_5_0__SRCID__SDMA_TRAP;
1248 	case 1:
1249 		return SDMA1_5_0__SRCID__SDMA_TRAP;
1250 	case 2:
1251 		return SDMA2_5_0__SRCID__SDMA_TRAP;
1252 	case 3:
1253 		return SDMA3_5_0__SRCID__SDMA_TRAP;
1254 	default:
1255 		break;
1256 	}
1257 	return -EINVAL;
1258 }
1259 
1260 static int sdma_v5_2_sw_init(void *handle)
1261 {
1262 	struct amdgpu_ring *ring;
1263 	int r, i;
1264 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265 
1266 	/* SDMA trap event */
1267 	for (i = 0; i < adev->sdma.num_instances; i++) {
1268 		r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1269 				      sdma_v5_2_seq_to_trap_id(i),
1270 				      &adev->sdma.trap_irq);
1271 		if (r)
1272 			return r;
1273 	}
1274 
1275 	r = sdma_v5_2_init_microcode(adev);
1276 	if (r) {
1277 		DRM_ERROR("Failed to load sdma firmware!\n");
1278 		return r;
1279 	}
1280 
1281 	for (i = 0; i < adev->sdma.num_instances; i++) {
1282 		ring = &adev->sdma.instance[i].ring;
1283 		ring->ring_obj = NULL;
1284 		ring->use_doorbell = true;
1285 		ring->me = i;
1286 
1287 		DRM_INFO("use_doorbell being set to: [%s]\n",
1288 				ring->use_doorbell?"true":"false");
1289 
1290 		ring->doorbell_index =
1291 			(adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1292 
1293 		sprintf(ring->name, "sdma%d", i);
1294 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1295 				     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1296 				     AMDGPU_RING_PRIO_DEFAULT, NULL);
1297 		if (r)
1298 			return r;
1299 	}
1300 
1301 	return r;
1302 }
1303 
1304 static int sdma_v5_2_sw_fini(void *handle)
1305 {
1306 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1307 	int i;
1308 
1309 	for (i = 0; i < adev->sdma.num_instances; i++)
1310 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1311 
1312 	sdma_v5_2_destroy_inst_ctx(adev);
1313 
1314 	return 0;
1315 }
1316 
1317 static int sdma_v5_2_hw_init(void *handle)
1318 {
1319 	int r;
1320 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321 
1322 	r = sdma_v5_2_start(adev);
1323 
1324 	return r;
1325 }
1326 
1327 static int sdma_v5_2_hw_fini(void *handle)
1328 {
1329 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1330 
1331 	if (amdgpu_sriov_vf(adev))
1332 		return 0;
1333 
1334 	sdma_v5_2_ctx_switch_enable(adev, false);
1335 	sdma_v5_2_enable(adev, false);
1336 
1337 	return 0;
1338 }
1339 
1340 static int sdma_v5_2_suspend(void *handle)
1341 {
1342 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1343 
1344 	return sdma_v5_2_hw_fini(adev);
1345 }
1346 
1347 static int sdma_v5_2_resume(void *handle)
1348 {
1349 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1350 
1351 	return sdma_v5_2_hw_init(adev);
1352 }
1353 
1354 static bool sdma_v5_2_is_idle(void *handle)
1355 {
1356 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1357 	u32 i;
1358 
1359 	for (i = 0; i < adev->sdma.num_instances; i++) {
1360 		u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1361 
1362 		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1363 			return false;
1364 	}
1365 
1366 	return true;
1367 }
1368 
1369 static int sdma_v5_2_wait_for_idle(void *handle)
1370 {
1371 	unsigned i;
1372 	u32 sdma0, sdma1, sdma2, sdma3;
1373 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1374 
1375 	for (i = 0; i < adev->usec_timeout; i++) {
1376 		sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1377 		sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1378 		sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1379 		sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1380 
1381 		if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1382 			return 0;
1383 		udelay(1);
1384 	}
1385 	return -ETIMEDOUT;
1386 }
1387 
1388 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1389 {
1390 	int i, r = 0;
1391 	struct amdgpu_device *adev = ring->adev;
1392 	u32 index = 0;
1393 	u64 sdma_gfx_preempt;
1394 
1395 	amdgpu_sdma_get_index_from_ring(ring, &index);
1396 	sdma_gfx_preempt =
1397 		sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1398 
1399 	/* assert preemption condition */
1400 	amdgpu_ring_set_preempt_cond_exec(ring, false);
1401 
1402 	/* emit the trailing fence */
1403 	ring->trail_seq += 1;
1404 	amdgpu_ring_alloc(ring, 10);
1405 	sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1406 				  ring->trail_seq, 0);
1407 	amdgpu_ring_commit(ring);
1408 
1409 	/* assert IB preemption */
1410 	WREG32(sdma_gfx_preempt, 1);
1411 
1412 	/* poll the trailing fence */
1413 	for (i = 0; i < adev->usec_timeout; i++) {
1414 		if (ring->trail_seq ==
1415 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1416 			break;
1417 		udelay(1);
1418 	}
1419 
1420 	if (i >= adev->usec_timeout) {
1421 		r = -EINVAL;
1422 		DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1423 	}
1424 
1425 	/* deassert IB preemption */
1426 	WREG32(sdma_gfx_preempt, 0);
1427 
1428 	/* deassert the preemption condition */
1429 	amdgpu_ring_set_preempt_cond_exec(ring, true);
1430 	return r;
1431 }
1432 
1433 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1434 					struct amdgpu_irq_src *source,
1435 					unsigned type,
1436 					enum amdgpu_interrupt_state state)
1437 {
1438 	u32 sdma_cntl;
1439 
1440 	u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1441 
1442 	sdma_cntl = RREG32(reg_offset);
1443 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1444 		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1445 	WREG32(reg_offset, sdma_cntl);
1446 
1447 	return 0;
1448 }
1449 
1450 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1451 				      struct amdgpu_irq_src *source,
1452 				      struct amdgpu_iv_entry *entry)
1453 {
1454 	DRM_DEBUG("IH: SDMA trap\n");
1455 	switch (entry->client_id) {
1456 	case SOC15_IH_CLIENTID_SDMA0:
1457 		switch (entry->ring_id) {
1458 		case 0:
1459 			amdgpu_fence_process(&adev->sdma.instance[0].ring);
1460 			break;
1461 		case 1:
1462 			/* XXX compute */
1463 			break;
1464 		case 2:
1465 			/* XXX compute */
1466 			break;
1467 		case 3:
1468 			/* XXX page queue*/
1469 			break;
1470 		}
1471 		break;
1472 	case SOC15_IH_CLIENTID_SDMA1:
1473 		switch (entry->ring_id) {
1474 		case 0:
1475 			amdgpu_fence_process(&adev->sdma.instance[1].ring);
1476 			break;
1477 		case 1:
1478 			/* XXX compute */
1479 			break;
1480 		case 2:
1481 			/* XXX compute */
1482 			break;
1483 		case 3:
1484 			/* XXX page queue*/
1485 			break;
1486 		}
1487 		break;
1488 	case SOC15_IH_CLIENTID_SDMA2:
1489 		switch (entry->ring_id) {
1490 		case 0:
1491 			amdgpu_fence_process(&adev->sdma.instance[2].ring);
1492 			break;
1493 		case 1:
1494 			/* XXX compute */
1495 			break;
1496 		case 2:
1497 			/* XXX compute */
1498 			break;
1499 		case 3:
1500 			/* XXX page queue*/
1501 			break;
1502 		}
1503 		break;
1504 	case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1505 		switch (entry->ring_id) {
1506 		case 0:
1507 			amdgpu_fence_process(&adev->sdma.instance[3].ring);
1508 			break;
1509 		case 1:
1510 			/* XXX compute */
1511 			break;
1512 		case 2:
1513 			/* XXX compute */
1514 			break;
1515 		case 3:
1516 			/* XXX page queue*/
1517 			break;
1518 		}
1519 		break;
1520 	}
1521 	return 0;
1522 }
1523 
1524 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1525 					      struct amdgpu_irq_src *source,
1526 					      struct amdgpu_iv_entry *entry)
1527 {
1528 	return 0;
1529 }
1530 
1531 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1532 						       bool enable)
1533 {
1534 	uint32_t data, def;
1535 	int i;
1536 
1537 	for (i = 0; i < adev->sdma.num_instances; i++) {
1538 
1539 		if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1540 			adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1541 
1542 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1543 			/* Enable sdma clock gating */
1544 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1545 			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1546 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1547 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1548 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1549 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1550 				  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1551 			if (def != data)
1552 				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1553 		} else {
1554 			/* Disable sdma clock gating */
1555 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1556 			data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1557 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1558 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1559 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1560 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1561 				 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1562 			if (def != data)
1563 				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1564 		}
1565 	}
1566 }
1567 
1568 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1569 						      bool enable)
1570 {
1571 	uint32_t data, def;
1572 	int i;
1573 
1574 	for (i = 0; i < adev->sdma.num_instances; i++) {
1575 
1576 		if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1577 			adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1578 
1579 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1580 			/* Enable sdma mem light sleep */
1581 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1582 			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1583 			if (def != data)
1584 				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1585 
1586 		} else {
1587 			/* Disable sdma mem light sleep */
1588 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1589 			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1590 			if (def != data)
1591 				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1592 
1593 		}
1594 	}
1595 }
1596 
1597 static int sdma_v5_2_set_clockgating_state(void *handle,
1598 					   enum amd_clockgating_state state)
1599 {
1600 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1601 
1602 	if (amdgpu_sriov_vf(adev))
1603 		return 0;
1604 
1605 	switch (adev->ip_versions[SDMA0_HWIP][0]) {
1606 	case IP_VERSION(5, 2, 0):
1607 	case IP_VERSION(5, 2, 2):
1608 	case IP_VERSION(5, 2, 1):
1609 	case IP_VERSION(5, 2, 4):
1610 	case IP_VERSION(5, 2, 5):
1611 	case IP_VERSION(5, 2, 3):
1612 		sdma_v5_2_update_medium_grain_clock_gating(adev,
1613 				state == AMD_CG_STATE_GATE);
1614 		sdma_v5_2_update_medium_grain_light_sleep(adev,
1615 				state == AMD_CG_STATE_GATE);
1616 		break;
1617 	default:
1618 		break;
1619 	}
1620 
1621 	return 0;
1622 }
1623 
1624 static int sdma_v5_2_set_powergating_state(void *handle,
1625 					  enum amd_powergating_state state)
1626 {
1627 	return 0;
1628 }
1629 
1630 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1631 {
1632 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1633 	int data;
1634 
1635 	if (amdgpu_sriov_vf(adev))
1636 		*flags = 0;
1637 
1638 	/* AMD_CG_SUPPORT_SDMA_LS */
1639 	data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1640 	if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1641 		*flags |= AMD_CG_SUPPORT_SDMA_LS;
1642 }
1643 
1644 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1645 	.name = "sdma_v5_2",
1646 	.early_init = sdma_v5_2_early_init,
1647 	.late_init = NULL,
1648 	.sw_init = sdma_v5_2_sw_init,
1649 	.sw_fini = sdma_v5_2_sw_fini,
1650 	.hw_init = sdma_v5_2_hw_init,
1651 	.hw_fini = sdma_v5_2_hw_fini,
1652 	.suspend = sdma_v5_2_suspend,
1653 	.resume = sdma_v5_2_resume,
1654 	.is_idle = sdma_v5_2_is_idle,
1655 	.wait_for_idle = sdma_v5_2_wait_for_idle,
1656 	.soft_reset = sdma_v5_2_soft_reset,
1657 	.set_clockgating_state = sdma_v5_2_set_clockgating_state,
1658 	.set_powergating_state = sdma_v5_2_set_powergating_state,
1659 	.get_clockgating_state = sdma_v5_2_get_clockgating_state,
1660 };
1661 
1662 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1663 	.type = AMDGPU_RING_TYPE_SDMA,
1664 	.align_mask = 0xf,
1665 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1666 	.support_64bit_ptrs = true,
1667 	.vmhub = AMDGPU_GFXHUB_0,
1668 	.get_rptr = sdma_v5_2_ring_get_rptr,
1669 	.get_wptr = sdma_v5_2_ring_get_wptr,
1670 	.set_wptr = sdma_v5_2_ring_set_wptr,
1671 	.emit_frame_size =
1672 		5 + /* sdma_v5_2_ring_init_cond_exec */
1673 		6 + /* sdma_v5_2_ring_emit_hdp_flush */
1674 		3 + /* hdp_invalidate */
1675 		6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1676 		/* sdma_v5_2_ring_emit_vm_flush */
1677 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1678 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1679 		10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1680 	.emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1681 	.emit_ib = sdma_v5_2_ring_emit_ib,
1682 	.emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1683 	.emit_fence = sdma_v5_2_ring_emit_fence,
1684 	.emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1685 	.emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1686 	.emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1687 	.test_ring = sdma_v5_2_ring_test_ring,
1688 	.test_ib = sdma_v5_2_ring_test_ib,
1689 	.insert_nop = sdma_v5_2_ring_insert_nop,
1690 	.pad_ib = sdma_v5_2_ring_pad_ib,
1691 	.emit_wreg = sdma_v5_2_ring_emit_wreg,
1692 	.emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1693 	.emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1694 	.init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1695 	.patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1696 	.preempt_ib = sdma_v5_2_ring_preempt_ib,
1697 };
1698 
1699 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1700 {
1701 	int i;
1702 
1703 	for (i = 0; i < adev->sdma.num_instances; i++) {
1704 		adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1705 		adev->sdma.instance[i].ring.me = i;
1706 	}
1707 }
1708 
1709 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1710 	.set = sdma_v5_2_set_trap_irq_state,
1711 	.process = sdma_v5_2_process_trap_irq,
1712 };
1713 
1714 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1715 	.process = sdma_v5_2_process_illegal_inst_irq,
1716 };
1717 
1718 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1719 {
1720 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1721 					adev->sdma.num_instances;
1722 	adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1723 	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1724 }
1725 
1726 /**
1727  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1728  *
1729  * @ib: indirect buffer to copy to
1730  * @src_offset: src GPU address
1731  * @dst_offset: dst GPU address
1732  * @byte_count: number of bytes to xfer
1733  * @tmz: if a secure copy should be used
1734  *
1735  * Copy GPU buffers using the DMA engine.
1736  * Used by the amdgpu ttm implementation to move pages if
1737  * registered as the asic copy callback.
1738  */
1739 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1740 				       uint64_t src_offset,
1741 				       uint64_t dst_offset,
1742 				       uint32_t byte_count,
1743 				       bool tmz)
1744 {
1745 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1746 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1747 		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1748 	ib->ptr[ib->length_dw++] = byte_count - 1;
1749 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1750 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1751 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1752 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1753 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1754 }
1755 
1756 /**
1757  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1758  *
1759  * @ib: indirect buffer to fill
1760  * @src_data: value to write to buffer
1761  * @dst_offset: dst GPU address
1762  * @byte_count: number of bytes to xfer
1763  *
1764  * Fill GPU buffers using the DMA engine.
1765  */
1766 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1767 				       uint32_t src_data,
1768 				       uint64_t dst_offset,
1769 				       uint32_t byte_count)
1770 {
1771 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1772 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1773 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1774 	ib->ptr[ib->length_dw++] = src_data;
1775 	ib->ptr[ib->length_dw++] = byte_count - 1;
1776 }
1777 
1778 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1779 	.copy_max_bytes = 0x400000,
1780 	.copy_num_dw = 7,
1781 	.emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1782 
1783 	.fill_max_bytes = 0x400000,
1784 	.fill_num_dw = 5,
1785 	.emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1786 };
1787 
1788 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1789 {
1790 	if (adev->mman.buffer_funcs == NULL) {
1791 		adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1792 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1793 	}
1794 }
1795 
1796 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1797 	.copy_pte_num_dw = 7,
1798 	.copy_pte = sdma_v5_2_vm_copy_pte,
1799 	.write_pte = sdma_v5_2_vm_write_pte,
1800 	.set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1801 };
1802 
1803 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1804 {
1805 	unsigned i;
1806 
1807 	if (adev->vm_manager.vm_pte_funcs == NULL) {
1808 		adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1809 		for (i = 0; i < adev->sdma.num_instances; i++) {
1810 			adev->vm_manager.vm_pte_scheds[i] =
1811 				&adev->sdma.instance[i].ring.sched;
1812 		}
1813 		adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1814 	}
1815 }
1816 
1817 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1818 	.type = AMD_IP_BLOCK_TYPE_SDMA,
1819 	.major = 5,
1820 	.minor = 2,
1821 	.rev = 0,
1822 	.funcs = &sdma_v5_2_ip_funcs,
1823 };
1824