1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32 
33 #include "gc/gc_10_3_0_offset.h"
34 #include "gc/gc_10_3_0_sh_mask.h"
35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
39 
40 #include "soc15_common.h"
41 #include "soc15.h"
42 #include "navi10_sdma_pkt_open.h"
43 #include "nbio_v2_3.h"
44 #include "sdma_common.h"
45 #include "sdma_v5_2.h"
46 
47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
50 
51 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
52 
53 #define SDMA1_REG_OFFSET 0x600
54 #define SDMA3_REG_OFFSET 0x400
55 #define SDMA0_HYP_DEC_REG_START 0x5880
56 #define SDMA0_HYP_DEC_REG_END 0x5893
57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
58 
59 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
60 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
61 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
62 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
63 
64 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
65 {
66 	u32 base;
67 
68 	if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
69 	    internal_offset <= SDMA0_HYP_DEC_REG_END) {
70 		base = adev->reg_offset[GC_HWIP][0][1];
71 		if (instance != 0)
72 			internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
73 	} else {
74 		if (instance < 2) {
75 			base = adev->reg_offset[GC_HWIP][0][0];
76 			if (instance == 1)
77 				internal_offset += SDMA1_REG_OFFSET;
78 		} else {
79 			base = adev->reg_offset[GC_HWIP][0][2];
80 			if (instance == 3)
81 				internal_offset += SDMA3_REG_OFFSET;
82 		}
83 	}
84 
85 	return base + internal_offset;
86 }
87 
88 static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
89 {
90 	switch (adev->asic_type) {
91 	case CHIP_SIENNA_CICHLID:
92 	case CHIP_NAVY_FLOUNDER:
93 	case CHIP_VANGOGH:
94 	case CHIP_DIMGREY_CAVEFISH:
95 		break;
96 	default:
97 		break;
98 	}
99 }
100 
101 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
102 {
103 	int err = 0;
104 	const struct sdma_firmware_header_v1_0 *hdr;
105 
106 	err = amdgpu_ucode_validate(sdma_inst->fw);
107 	if (err)
108 		return err;
109 
110 	hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
111 	sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
112 	sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
113 
114 	if (sdma_inst->feature_version >= 20)
115 		sdma_inst->burst_nop = true;
116 
117 	return 0;
118 }
119 
120 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
121 {
122 	release_firmware(adev->sdma.instance[0].fw);
123 
124 	memset((void *)adev->sdma.instance, 0,
125 	       sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
126 }
127 
128 /**
129  * sdma_v5_2_init_microcode - load ucode images from disk
130  *
131  * @adev: amdgpu_device pointer
132  *
133  * Use the firmware interface to load the ucode images into
134  * the driver (not loaded into hw).
135  * Returns 0 on success, error on failure.
136  */
137 
138 // emulation only, won't work on real chip
139 // navi10 real chip need to use PSP to load firmware
140 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
141 {
142 	const char *chip_name;
143 	char fw_name[40];
144 	int err = 0, i;
145 	struct amdgpu_firmware_info *info = NULL;
146 	const struct common_firmware_header *header = NULL;
147 
148 	if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID))
149 		return 0;
150 
151 	DRM_DEBUG("\n");
152 
153 	switch (adev->asic_type) {
154 	case CHIP_SIENNA_CICHLID:
155 		chip_name = "sienna_cichlid";
156 		break;
157 	case CHIP_NAVY_FLOUNDER:
158 		chip_name = "navy_flounder";
159 		break;
160 	case CHIP_VANGOGH:
161 		chip_name = "vangogh";
162 		break;
163 	case CHIP_DIMGREY_CAVEFISH:
164 		chip_name = "dimgrey_cavefish";
165 		break;
166 	default:
167 		BUG();
168 	}
169 
170 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
171 
172 	err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
173 	if (err)
174 		goto out;
175 
176 	err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
177 	if (err)
178 		goto out;
179 
180 	for (i = 1; i < adev->sdma.num_instances; i++)
181 		memcpy((void *)&adev->sdma.instance[i],
182 		       (void *)&adev->sdma.instance[0],
183 		       sizeof(struct amdgpu_sdma_instance));
184 
185 	DRM_DEBUG("psp_load == '%s'\n",
186 		  adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
187 
188 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
189 		for (i = 0; i < adev->sdma.num_instances; i++) {
190 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
191 			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
192 			info->fw = adev->sdma.instance[i].fw;
193 			header = (const struct common_firmware_header *)info->fw->data;
194 			adev->firmware.fw_size +=
195 				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
196 		}
197 	}
198 
199 out:
200 	if (err) {
201 		DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
202 		sdma_v5_2_destroy_inst_ctx(adev);
203 	}
204 	return err;
205 }
206 
207 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
208 {
209 	unsigned ret;
210 
211 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
212 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
213 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
214 	amdgpu_ring_write(ring, 1);
215 	ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
216 	amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
217 
218 	return ret;
219 }
220 
221 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
222 					   unsigned offset)
223 {
224 	unsigned cur;
225 
226 	BUG_ON(offset > ring->buf_mask);
227 	BUG_ON(ring->ring[offset] != 0x55aa55aa);
228 
229 	cur = (ring->wptr - 1) & ring->buf_mask;
230 	if (cur > offset)
231 		ring->ring[offset] = cur - offset;
232 	else
233 		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
234 }
235 
236 /**
237  * sdma_v5_2_ring_get_rptr - get the current read pointer
238  *
239  * @ring: amdgpu ring pointer
240  *
241  * Get the current rptr from the hardware (NAVI10+).
242  */
243 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
244 {
245 	u64 *rptr;
246 
247 	/* XXX check if swapping is necessary on BE */
248 	rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
249 
250 	DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
251 	return ((*rptr) >> 2);
252 }
253 
254 /**
255  * sdma_v5_2_ring_get_wptr - get the current write pointer
256  *
257  * @ring: amdgpu ring pointer
258  *
259  * Get the current wptr from the hardware (NAVI10+).
260  */
261 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
262 {
263 	struct amdgpu_device *adev = ring->adev;
264 	u64 wptr;
265 
266 	if (ring->use_doorbell) {
267 		/* XXX check if swapping is necessary on BE */
268 		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
269 		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
270 	} else {
271 		wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
272 		wptr = wptr << 32;
273 		wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
274 		DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
275 	}
276 
277 	return wptr >> 2;
278 }
279 
280 /**
281  * sdma_v5_2_ring_set_wptr - commit the write pointer
282  *
283  * @ring: amdgpu ring pointer
284  *
285  * Write the wptr back to the hardware (NAVI10+).
286  */
287 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
288 {
289 	struct amdgpu_device *adev = ring->adev;
290 
291 	DRM_DEBUG("Setting write pointer\n");
292 	if (ring->use_doorbell) {
293 		DRM_DEBUG("Using doorbell -- "
294 				"wptr_offs == 0x%08x "
295 				"lower_32_bits(ring->wptr) << 2 == 0x%08x "
296 				"upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
297 				ring->wptr_offs,
298 				lower_32_bits(ring->wptr << 2),
299 				upper_32_bits(ring->wptr << 2));
300 		/* XXX check if swapping is necessary on BE */
301 		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
302 		adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
303 		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
304 				ring->doorbell_index, ring->wptr << 2);
305 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
306 	} else {
307 		DRM_DEBUG("Not using doorbell -- "
308 				"mmSDMA%i_GFX_RB_WPTR == 0x%08x "
309 				"mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
310 				ring->me,
311 				lower_32_bits(ring->wptr << 2),
312 				ring->me,
313 				upper_32_bits(ring->wptr << 2));
314 		WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
315 			lower_32_bits(ring->wptr << 2));
316 		WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
317 			upper_32_bits(ring->wptr << 2));
318 	}
319 }
320 
321 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
322 {
323 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
324 	int i;
325 
326 	for (i = 0; i < count; i++)
327 		if (sdma && sdma->burst_nop && (i == 0))
328 			amdgpu_ring_write(ring, ring->funcs->nop |
329 				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
330 		else
331 			amdgpu_ring_write(ring, ring->funcs->nop);
332 }
333 
334 /**
335  * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
336  *
337  * @ring: amdgpu ring pointer
338  * @job: job to retrieve vmid from
339  * @ib: IB object to schedule
340  * @flags: unused
341  *
342  * Schedule an IB in the DMA ring.
343  */
344 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
345 				   struct amdgpu_job *job,
346 				   struct amdgpu_ib *ib,
347 				   uint32_t flags)
348 {
349 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
350 	uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
351 
352 	/* An IB packet must end on a 8 DW boundary--the next dword
353 	 * must be on a 8-dword boundary. Our IB packet below is 6
354 	 * dwords long, thus add x number of NOPs, such that, in
355 	 * modular arithmetic,
356 	 * wptr + 6 + x = 8k, k >= 0, which in C is,
357 	 * (wptr + 6 + x) % 8 = 0.
358 	 * The expression below, is a solution of x.
359 	 */
360 	sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
361 
362 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
363 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
364 	/* base must be 32 byte aligned */
365 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
366 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
367 	amdgpu_ring_write(ring, ib->length_dw);
368 	amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
369 	amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
370 }
371 
372 /**
373  * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
374  *
375  * @ring: amdgpu ring pointer
376  * @job: job to retrieve vmid from
377  * @ib: IB object to schedule
378  *
379  * flush the IB by graphics cache rinse.
380  */
381 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
382 {
383     uint32_t gcr_cntl =
384 		    SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
385 			SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
386 			SDMA_GCR_GLI_INV(1);
387 
388 	/* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
389 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
390 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
391 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
392 			SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
393 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
394 			SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
395 	amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
396 			SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
397 }
398 
399 /**
400  * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
401  *
402  * @ring: amdgpu ring pointer
403  *
404  * Emit an hdp flush packet on the requested DMA ring.
405  */
406 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
407 {
408 	struct amdgpu_device *adev = ring->adev;
409 	u32 ref_and_mask = 0;
410 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
411 
412 	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
413 
414 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
415 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
416 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
417 	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
418 	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
419 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
420 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
421 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
422 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
423 }
424 
425 /**
426  * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
427  *
428  * @ring: amdgpu ring pointer
429  * @addr: address
430  * @seq: sequence number
431  * @flags: fence related flags
432  *
433  * Add a DMA fence packet to the ring to write
434  * the fence seq number and DMA trap packet to generate
435  * an interrupt if needed.
436  */
437 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
438 				      unsigned flags)
439 {
440 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
441 	/* write the fence */
442 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
443 			  SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
444 	/* zero in first two bits */
445 	BUG_ON(addr & 0x3);
446 	amdgpu_ring_write(ring, lower_32_bits(addr));
447 	amdgpu_ring_write(ring, upper_32_bits(addr));
448 	amdgpu_ring_write(ring, lower_32_bits(seq));
449 
450 	/* optionally write high bits as well */
451 	if (write64bit) {
452 		addr += 4;
453 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
454 				  SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
455 		/* zero in first two bits */
456 		BUG_ON(addr & 0x3);
457 		amdgpu_ring_write(ring, lower_32_bits(addr));
458 		amdgpu_ring_write(ring, upper_32_bits(addr));
459 		amdgpu_ring_write(ring, upper_32_bits(seq));
460 	}
461 
462 	if (flags & AMDGPU_FENCE_FLAG_INT) {
463 		/* generate an interrupt */
464 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
465 		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
466 	}
467 }
468 
469 
470 /**
471  * sdma_v5_2_gfx_stop - stop the gfx async dma engines
472  *
473  * @adev: amdgpu_device pointer
474  *
475  * Stop the gfx async dma ring buffers.
476  */
477 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
478 {
479 	struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
480 	struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
481 	struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
482 	struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
483 	u32 rb_cntl, ib_cntl;
484 	int i;
485 
486 	if ((adev->mman.buffer_funcs_ring == sdma0) ||
487 	    (adev->mman.buffer_funcs_ring == sdma1) ||
488 	    (adev->mman.buffer_funcs_ring == sdma2) ||
489 	    (adev->mman.buffer_funcs_ring == sdma3))
490 		amdgpu_ttm_set_buffer_funcs_status(adev, false);
491 
492 	for (i = 0; i < adev->sdma.num_instances; i++) {
493 		rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
494 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
495 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
496 		ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
497 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
498 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
499 	}
500 
501 	sdma0->sched.ready = false;
502 	sdma1->sched.ready = false;
503 	sdma2->sched.ready = false;
504 	sdma3->sched.ready = false;
505 }
506 
507 /**
508  * sdma_v5_2_rlc_stop - stop the compute async dma engines
509  *
510  * @adev: amdgpu_device pointer
511  *
512  * Stop the compute async dma queues.
513  */
514 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
515 {
516 	/* XXX todo */
517 }
518 
519 /**
520  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
521  *
522  * @adev: amdgpu_device pointer
523  * @enable: enable/disable the DMA MEs context switch.
524  *
525  * Halt or unhalt the async dma engines context switch.
526  */
527 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
528 {
529 	u32 f32_cntl, phase_quantum = 0;
530 	int i;
531 
532 	if (amdgpu_sdma_phase_quantum) {
533 		unsigned value = amdgpu_sdma_phase_quantum;
534 		unsigned unit = 0;
535 
536 		while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
537 				SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
538 			value = (value + 1) >> 1;
539 			unit++;
540 		}
541 		if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
542 			    SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
543 			value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
544 				 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
545 			unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
546 				SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
547 			WARN_ONCE(1,
548 			"clamping sdma_phase_quantum to %uK clock cycles\n",
549 				  value << unit);
550 		}
551 		phase_quantum =
552 			value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
553 			unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
554 	}
555 
556 	for (i = 0; i < adev->sdma.num_instances; i++) {
557 		f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
558 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
559 				AUTO_CTXSW_ENABLE, enable ? 1 : 0);
560 		if (enable && amdgpu_sdma_phase_quantum) {
561 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
562 			       phase_quantum);
563 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
564 			       phase_quantum);
565 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
566 			       phase_quantum);
567 		}
568 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
569 	}
570 
571 }
572 
573 /**
574  * sdma_v5_2_enable - stop the async dma engines
575  *
576  * @adev: amdgpu_device pointer
577  * @enable: enable/disable the DMA MEs.
578  *
579  * Halt or unhalt the async dma engines.
580  */
581 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
582 {
583 	u32 f32_cntl;
584 	int i;
585 
586 	if (!enable) {
587 		sdma_v5_2_gfx_stop(adev);
588 		sdma_v5_2_rlc_stop(adev);
589 	}
590 
591 	for (i = 0; i < adev->sdma.num_instances; i++) {
592 		f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
593 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
594 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
595 	}
596 }
597 
598 /**
599  * sdma_v5_2_gfx_resume - setup and start the async dma engines
600  *
601  * @adev: amdgpu_device pointer
602  *
603  * Set up the gfx DMA ring buffers and enable them.
604  * Returns 0 for success, error for failure.
605  */
606 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
607 {
608 	struct amdgpu_ring *ring;
609 	u32 rb_cntl, ib_cntl;
610 	u32 rb_bufsz;
611 	u32 wb_offset;
612 	u32 doorbell;
613 	u32 doorbell_offset;
614 	u32 temp;
615 	u32 wptr_poll_cntl;
616 	u64 wptr_gpu_addr;
617 	int i, r;
618 
619 	for (i = 0; i < adev->sdma.num_instances; i++) {
620 		ring = &adev->sdma.instance[i].ring;
621 		wb_offset = (ring->rptr_offs * 4);
622 
623 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
624 
625 		/* Set ring buffer size in dwords */
626 		rb_bufsz = order_base_2(ring->ring_size / 4);
627 		rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
628 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
629 #ifdef __BIG_ENDIAN
630 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
631 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
632 					RPTR_WRITEBACK_SWAP_ENABLE, 1);
633 #endif
634 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
635 
636 		/* Initialize the ring buffer's read and write pointers */
637 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
638 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
639 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
640 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
641 
642 		/* setup the wptr shadow polling */
643 		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
644 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
645 		       lower_32_bits(wptr_gpu_addr));
646 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
647 		       upper_32_bits(wptr_gpu_addr));
648 		wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
649 							 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
650 		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
651 					       SDMA0_GFX_RB_WPTR_POLL_CNTL,
652 					       F32_POLL_ENABLE, 1);
653 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
654 		       wptr_poll_cntl);
655 
656 		/* set the wb address whether it's enabled or not */
657 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
658 		       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
659 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
660 		       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
661 
662 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
663 
664 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
665 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
666 
667 		ring->wptr = 0;
668 
669 		/* before programing wptr to a less value, need set minor_ptr_update first */
670 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
671 
672 		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
673 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
674 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
675 		}
676 
677 		doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
678 		doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
679 
680 		if (ring->use_doorbell) {
681 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
682 			doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
683 					OFFSET, ring->doorbell_index);
684 		} else {
685 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
686 		}
687 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
688 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
689 
690 		adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
691 						      ring->doorbell_index,
692 						      adev->doorbell_index.sdma_doorbell_range);
693 
694 		if (amdgpu_sriov_vf(adev))
695 			sdma_v5_2_ring_set_wptr(ring);
696 
697 		/* set minor_ptr_update to 0 after wptr programed */
698 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
699 
700 		/* set utc l1 enable flag always to 1 */
701 		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
702 		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
703 
704 		/* enable MCBP */
705 		temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
706 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
707 
708 		/* Set up RESP_MODE to non-copy addresses */
709 		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
710 		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
711 		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
712 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
713 
714 		/* program default cache read and write policy */
715 		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
716 		/* clean read policy and write policy bits */
717 		temp &= 0xFF0FFF;
718 		temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
719 			 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
720 			 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
721 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
722 
723 		if (!amdgpu_sriov_vf(adev)) {
724 			/* unhalt engine */
725 			temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
726 			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
727 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
728 		}
729 
730 		/* enable DMA RB */
731 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
732 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
733 
734 		ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
735 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
736 #ifdef __BIG_ENDIAN
737 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
738 #endif
739 		/* enable DMA IBs */
740 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
741 
742 		ring->sched.ready = true;
743 
744 		if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
745 			sdma_v5_2_ctx_switch_enable(adev, true);
746 			sdma_v5_2_enable(adev, true);
747 		}
748 
749 		r = amdgpu_ring_test_ring(ring);
750 		if (r) {
751 			ring->sched.ready = false;
752 			return r;
753 		}
754 
755 		if (adev->mman.buffer_funcs_ring == ring)
756 			amdgpu_ttm_set_buffer_funcs_status(adev, true);
757 	}
758 
759 	return 0;
760 }
761 
762 /**
763  * sdma_v5_2_rlc_resume - setup and start the async dma engines
764  *
765  * @adev: amdgpu_device pointer
766  *
767  * Set up the compute DMA queues and enable them.
768  * Returns 0 for success, error for failure.
769  */
770 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
771 {
772 	return 0;
773 }
774 
775 /**
776  * sdma_v5_2_load_microcode - load the sDMA ME ucode
777  *
778  * @adev: amdgpu_device pointer
779  *
780  * Loads the sDMA0/1/2/3 ucode.
781  * Returns 0 for success, -EINVAL if the ucode is not available.
782  */
783 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
784 {
785 	const struct sdma_firmware_header_v1_0 *hdr;
786 	const __le32 *fw_data;
787 	u32 fw_size;
788 	int i, j;
789 
790 	/* halt the MEs */
791 	sdma_v5_2_enable(adev, false);
792 
793 	for (i = 0; i < adev->sdma.num_instances; i++) {
794 		if (!adev->sdma.instance[i].fw)
795 			return -EINVAL;
796 
797 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
798 		amdgpu_ucode_print_sdma_hdr(&hdr->header);
799 		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
800 
801 		fw_data = (const __le32 *)
802 			(adev->sdma.instance[i].fw->data +
803 				le32_to_cpu(hdr->header.ucode_array_offset_bytes));
804 
805 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
806 
807 		for (j = 0; j < fw_size; j++) {
808 			if (amdgpu_emu_mode == 1 && j % 500 == 0)
809 				msleep(1);
810 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
811 		}
812 
813 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
814 	}
815 
816 	return 0;
817 }
818 
819 static int sdma_v5_2_soft_reset(void *handle)
820 {
821 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
822 	u32 grbm_soft_reset;
823 	u32 tmp;
824 	int i;
825 
826 	for (i = 0; i < adev->sdma.num_instances; i++) {
827 		grbm_soft_reset = REG_SET_FIELD(0,
828 						GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
829 						1);
830 		grbm_soft_reset <<= i;
831 
832 		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
833 		tmp |= grbm_soft_reset;
834 		DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
835 		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
836 		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
837 
838 		udelay(50);
839 
840 		tmp &= ~grbm_soft_reset;
841 		WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
842 		tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
843 
844 		udelay(50);
845 	}
846 
847 	return 0;
848 }
849 
850 /**
851  * sdma_v5_2_start - setup and start the async dma engines
852  *
853  * @adev: amdgpu_device pointer
854  *
855  * Set up the DMA engines and enable them.
856  * Returns 0 for success, error for failure.
857  */
858 static int sdma_v5_2_start(struct amdgpu_device *adev)
859 {
860 	int r = 0;
861 
862 	if (amdgpu_sriov_vf(adev)) {
863 		sdma_v5_2_ctx_switch_enable(adev, false);
864 		sdma_v5_2_enable(adev, false);
865 
866 		/* set RB registers */
867 		r = sdma_v5_2_gfx_resume(adev);
868 		return r;
869 	}
870 
871 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
872 		r = sdma_v5_2_load_microcode(adev);
873 		if (r)
874 			return r;
875 
876 		/* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
877 		if (amdgpu_emu_mode == 1)
878 			msleep(1000);
879 	}
880 
881 	sdma_v5_2_soft_reset(adev);
882 	/* unhalt the MEs */
883 	sdma_v5_2_enable(adev, true);
884 	/* enable sdma ring preemption */
885 	sdma_v5_2_ctx_switch_enable(adev, true);
886 
887 	/* start the gfx rings and rlc compute queues */
888 	r = sdma_v5_2_gfx_resume(adev);
889 	if (r)
890 		return r;
891 	r = sdma_v5_2_rlc_resume(adev);
892 
893 	return r;
894 }
895 
896 /**
897  * sdma_v5_2_ring_test_ring - simple async dma engine test
898  *
899  * @ring: amdgpu_ring structure holding ring information
900  *
901  * Test the DMA engine by writing using it to write an
902  * value to memory.
903  * Returns 0 for success, error for failure.
904  */
905 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
906 {
907 	struct amdgpu_device *adev = ring->adev;
908 	unsigned i;
909 	unsigned index;
910 	int r;
911 	u32 tmp;
912 	u64 gpu_addr;
913 
914 	r = amdgpu_device_wb_get(adev, &index);
915 	if (r) {
916 		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
917 		return r;
918 	}
919 
920 	gpu_addr = adev->wb.gpu_addr + (index * 4);
921 	tmp = 0xCAFEDEAD;
922 	adev->wb.wb[index] = cpu_to_le32(tmp);
923 
924 	r = amdgpu_ring_alloc(ring, 5);
925 	if (r) {
926 		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
927 		amdgpu_device_wb_free(adev, index);
928 		return r;
929 	}
930 
931 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
932 			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
933 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
934 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
935 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
936 	amdgpu_ring_write(ring, 0xDEADBEEF);
937 	amdgpu_ring_commit(ring);
938 
939 	for (i = 0; i < adev->usec_timeout; i++) {
940 		tmp = le32_to_cpu(adev->wb.wb[index]);
941 		if (tmp == 0xDEADBEEF)
942 			break;
943 		if (amdgpu_emu_mode == 1)
944 			msleep(1);
945 		else
946 			udelay(1);
947 	}
948 
949 	if (i >= adev->usec_timeout)
950 		r = -ETIMEDOUT;
951 
952 	amdgpu_device_wb_free(adev, index);
953 
954 	return r;
955 }
956 
957 /**
958  * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
959  *
960  * @ring: amdgpu_ring structure holding ring information
961  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
962  *
963  * Test a simple IB in the DMA ring.
964  * Returns 0 on success, error on failure.
965  */
966 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
967 {
968 	struct amdgpu_device *adev = ring->adev;
969 	struct amdgpu_ib ib;
970 	struct dma_fence *f = NULL;
971 	unsigned index;
972 	long r;
973 	u32 tmp = 0;
974 	u64 gpu_addr;
975 
976 	r = amdgpu_device_wb_get(adev, &index);
977 	if (r) {
978 		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
979 		return r;
980 	}
981 
982 	gpu_addr = adev->wb.gpu_addr + (index * 4);
983 	tmp = 0xCAFEDEAD;
984 	adev->wb.wb[index] = cpu_to_le32(tmp);
985 	memset(&ib, 0, sizeof(ib));
986 	r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
987 	if (r) {
988 		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
989 		goto err0;
990 	}
991 
992 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
993 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
994 	ib.ptr[1] = lower_32_bits(gpu_addr);
995 	ib.ptr[2] = upper_32_bits(gpu_addr);
996 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
997 	ib.ptr[4] = 0xDEADBEEF;
998 	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
999 	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1000 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1001 	ib.length_dw = 8;
1002 
1003 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1004 	if (r)
1005 		goto err1;
1006 
1007 	r = dma_fence_wait_timeout(f, false, timeout);
1008 	if (r == 0) {
1009 		DRM_ERROR("amdgpu: IB test timed out\n");
1010 		r = -ETIMEDOUT;
1011 		goto err1;
1012 	} else if (r < 0) {
1013 		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1014 		goto err1;
1015 	}
1016 	tmp = le32_to_cpu(adev->wb.wb[index]);
1017 	if (tmp == 0xDEADBEEF)
1018 		r = 0;
1019 	else
1020 		r = -EINVAL;
1021 
1022 err1:
1023 	amdgpu_ib_free(adev, &ib, NULL);
1024 	dma_fence_put(f);
1025 err0:
1026 	amdgpu_device_wb_free(adev, index);
1027 	return r;
1028 }
1029 
1030 
1031 /**
1032  * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1033  *
1034  * @ib: indirect buffer to fill with commands
1035  * @pe: addr of the page entry
1036  * @src: src addr to copy from
1037  * @count: number of page entries to update
1038  *
1039  * Update PTEs by copying them from the GART using sDMA.
1040  */
1041 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1042 				  uint64_t pe, uint64_t src,
1043 				  unsigned count)
1044 {
1045 	unsigned bytes = count * 8;
1046 
1047 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1048 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1049 	ib->ptr[ib->length_dw++] = bytes - 1;
1050 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1051 	ib->ptr[ib->length_dw++] = lower_32_bits(src);
1052 	ib->ptr[ib->length_dw++] = upper_32_bits(src);
1053 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1054 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1055 
1056 }
1057 
1058 /**
1059  * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1060  *
1061  * @ib: indirect buffer to fill with commands
1062  * @pe: addr of the page entry
1063  * @value: dst addr to write into pe
1064  * @count: number of page entries to update
1065  * @incr: increase next addr by incr bytes
1066  *
1067  * Update PTEs by writing them manually using sDMA.
1068  */
1069 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1070 				   uint64_t value, unsigned count,
1071 				   uint32_t incr)
1072 {
1073 	unsigned ndw = count * 2;
1074 
1075 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1076 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1077 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1078 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1079 	ib->ptr[ib->length_dw++] = ndw - 1;
1080 	for (; ndw > 0; ndw -= 2) {
1081 		ib->ptr[ib->length_dw++] = lower_32_bits(value);
1082 		ib->ptr[ib->length_dw++] = upper_32_bits(value);
1083 		value += incr;
1084 	}
1085 }
1086 
1087 /**
1088  * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1089  *
1090  * @ib: indirect buffer to fill with commands
1091  * @pe: addr of the page entry
1092  * @addr: dst addr to write into pe
1093  * @count: number of page entries to update
1094  * @incr: increase next addr by incr bytes
1095  * @flags: access flags
1096  *
1097  * Update the page tables using sDMA.
1098  */
1099 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1100 				     uint64_t pe,
1101 				     uint64_t addr, unsigned count,
1102 				     uint32_t incr, uint64_t flags)
1103 {
1104 	/* for physically contiguous pages (vram) */
1105 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1106 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1107 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1108 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1109 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1110 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1111 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1112 	ib->ptr[ib->length_dw++] = incr; /* increment size */
1113 	ib->ptr[ib->length_dw++] = 0;
1114 	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1115 }
1116 
1117 /**
1118  * sdma_v5_2_ring_pad_ib - pad the IB
1119  *
1120  * @ib: indirect buffer to fill with padding
1121  * @ring: amdgpu_ring structure holding ring information
1122  *
1123  * Pad the IB with NOPs to a boundary multiple of 8.
1124  */
1125 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1126 {
1127 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1128 	u32 pad_count;
1129 	int i;
1130 
1131 	pad_count = (-ib->length_dw) & 0x7;
1132 	for (i = 0; i < pad_count; i++)
1133 		if (sdma && sdma->burst_nop && (i == 0))
1134 			ib->ptr[ib->length_dw++] =
1135 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1136 				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1137 		else
1138 			ib->ptr[ib->length_dw++] =
1139 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1140 }
1141 
1142 
1143 /**
1144  * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1145  *
1146  * @ring: amdgpu_ring pointer
1147  *
1148  * Make sure all previous operations are completed (CIK).
1149  */
1150 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1151 {
1152 	uint32_t seq = ring->fence_drv.sync_seq;
1153 	uint64_t addr = ring->fence_drv.gpu_addr;
1154 
1155 	/* wait for idle */
1156 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1157 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1158 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1159 			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1160 	amdgpu_ring_write(ring, addr & 0xfffffffc);
1161 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1162 	amdgpu_ring_write(ring, seq); /* reference */
1163 	amdgpu_ring_write(ring, 0xffffffff); /* mask */
1164 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1165 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1166 }
1167 
1168 
1169 /**
1170  * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1171  *
1172  * @ring: amdgpu_ring pointer
1173  * @vmid: vmid number to use
1174  * @pd_addr: address
1175  *
1176  * Update the page table base and flush the VM TLB
1177  * using sDMA.
1178  */
1179 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1180 					 unsigned vmid, uint64_t pd_addr)
1181 {
1182 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1183 }
1184 
1185 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1186 				     uint32_t reg, uint32_t val)
1187 {
1188 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1189 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1190 	amdgpu_ring_write(ring, reg);
1191 	amdgpu_ring_write(ring, val);
1192 }
1193 
1194 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1195 					 uint32_t val, uint32_t mask)
1196 {
1197 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1198 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1199 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1200 	amdgpu_ring_write(ring, reg << 2);
1201 	amdgpu_ring_write(ring, 0);
1202 	amdgpu_ring_write(ring, val); /* reference */
1203 	amdgpu_ring_write(ring, mask); /* mask */
1204 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1205 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1206 }
1207 
1208 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1209 						   uint32_t reg0, uint32_t reg1,
1210 						   uint32_t ref, uint32_t mask)
1211 {
1212 	amdgpu_ring_emit_wreg(ring, reg0, ref);
1213 	/* wait for a cycle to reset vm_inv_eng*_ack */
1214 	amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1215 	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1216 }
1217 
1218 static int sdma_v5_2_early_init(void *handle)
1219 {
1220 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1221 
1222 	switch (adev->asic_type) {
1223 	case CHIP_SIENNA_CICHLID:
1224 		adev->sdma.num_instances = 4;
1225 		break;
1226 	case CHIP_NAVY_FLOUNDER:
1227 	case CHIP_DIMGREY_CAVEFISH:
1228 		adev->sdma.num_instances = 2;
1229 		break;
1230 	case CHIP_VANGOGH:
1231 		adev->sdma.num_instances = 1;
1232 		break;
1233 	default:
1234 		break;
1235 	}
1236 
1237 	sdma_v5_2_set_ring_funcs(adev);
1238 	sdma_v5_2_set_buffer_funcs(adev);
1239 	sdma_v5_2_set_vm_pte_funcs(adev);
1240 	sdma_v5_2_set_irq_funcs(adev);
1241 
1242 	return 0;
1243 }
1244 
1245 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1246 {
1247 	switch (seq_num) {
1248 	case 0:
1249 		return SOC15_IH_CLIENTID_SDMA0;
1250 	case 1:
1251 		return SOC15_IH_CLIENTID_SDMA1;
1252 	case 2:
1253 		return SOC15_IH_CLIENTID_SDMA2;
1254 	case 3:
1255 		return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1256 	default:
1257 		break;
1258 	}
1259 	return -EINVAL;
1260 }
1261 
1262 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1263 {
1264 	switch (seq_num) {
1265 	case 0:
1266 		return SDMA0_5_0__SRCID__SDMA_TRAP;
1267 	case 1:
1268 		return SDMA1_5_0__SRCID__SDMA_TRAP;
1269 	case 2:
1270 		return SDMA2_5_0__SRCID__SDMA_TRAP;
1271 	case 3:
1272 		return SDMA3_5_0__SRCID__SDMA_TRAP;
1273 	default:
1274 		break;
1275 	}
1276 	return -EINVAL;
1277 }
1278 
1279 static int sdma_v5_2_sw_init(void *handle)
1280 {
1281 	struct amdgpu_ring *ring;
1282 	int r, i;
1283 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1284 
1285 	/* SDMA trap event */
1286 	for (i = 0; i < adev->sdma.num_instances; i++) {
1287 		r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1288 				      sdma_v5_2_seq_to_trap_id(i),
1289 				      &adev->sdma.trap_irq);
1290 		if (r)
1291 			return r;
1292 	}
1293 
1294 	r = sdma_v5_2_init_microcode(adev);
1295 	if (r) {
1296 		DRM_ERROR("Failed to load sdma firmware!\n");
1297 		return r;
1298 	}
1299 
1300 	for (i = 0; i < adev->sdma.num_instances; i++) {
1301 		ring = &adev->sdma.instance[i].ring;
1302 		ring->ring_obj = NULL;
1303 		ring->use_doorbell = true;
1304 		ring->me = i;
1305 
1306 		DRM_INFO("use_doorbell being set to: [%s]\n",
1307 				ring->use_doorbell?"true":"false");
1308 
1309 		ring->doorbell_index =
1310 			(adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1311 
1312 		sprintf(ring->name, "sdma%d", i);
1313 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1314 				     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1315 				     AMDGPU_RING_PRIO_DEFAULT, NULL);
1316 		if (r)
1317 			return r;
1318 	}
1319 
1320 	return r;
1321 }
1322 
1323 static int sdma_v5_2_sw_fini(void *handle)
1324 {
1325 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1326 	int i;
1327 
1328 	for (i = 0; i < adev->sdma.num_instances; i++)
1329 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1330 
1331 	sdma_v5_2_destroy_inst_ctx(adev);
1332 
1333 	return 0;
1334 }
1335 
1336 static int sdma_v5_2_hw_init(void *handle)
1337 {
1338 	int r;
1339 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1340 
1341 	sdma_v5_2_init_golden_registers(adev);
1342 
1343 	r = sdma_v5_2_start(adev);
1344 
1345 	return r;
1346 }
1347 
1348 static int sdma_v5_2_hw_fini(void *handle)
1349 {
1350 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1351 
1352 	if (amdgpu_sriov_vf(adev))
1353 		return 0;
1354 
1355 	sdma_v5_2_ctx_switch_enable(adev, false);
1356 	sdma_v5_2_enable(adev, false);
1357 
1358 	return 0;
1359 }
1360 
1361 static int sdma_v5_2_suspend(void *handle)
1362 {
1363 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1364 
1365 	return sdma_v5_2_hw_fini(adev);
1366 }
1367 
1368 static int sdma_v5_2_resume(void *handle)
1369 {
1370 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1371 
1372 	return sdma_v5_2_hw_init(adev);
1373 }
1374 
1375 static bool sdma_v5_2_is_idle(void *handle)
1376 {
1377 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1378 	u32 i;
1379 
1380 	for (i = 0; i < adev->sdma.num_instances; i++) {
1381 		u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1382 
1383 		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1384 			return false;
1385 	}
1386 
1387 	return true;
1388 }
1389 
1390 static int sdma_v5_2_wait_for_idle(void *handle)
1391 {
1392 	unsigned i;
1393 	u32 sdma0, sdma1, sdma2, sdma3;
1394 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1395 
1396 	for (i = 0; i < adev->usec_timeout; i++) {
1397 		sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1398 		sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1399 		sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1400 		sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1401 
1402 		if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1403 			return 0;
1404 		udelay(1);
1405 	}
1406 	return -ETIMEDOUT;
1407 }
1408 
1409 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1410 {
1411 	int i, r = 0;
1412 	struct amdgpu_device *adev = ring->adev;
1413 	u32 index = 0;
1414 	u64 sdma_gfx_preempt;
1415 
1416 	amdgpu_sdma_get_index_from_ring(ring, &index);
1417 	sdma_gfx_preempt =
1418 		sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1419 
1420 	/* assert preemption condition */
1421 	amdgpu_ring_set_preempt_cond_exec(ring, false);
1422 
1423 	/* emit the trailing fence */
1424 	ring->trail_seq += 1;
1425 	amdgpu_ring_alloc(ring, 10);
1426 	sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1427 				  ring->trail_seq, 0);
1428 	amdgpu_ring_commit(ring);
1429 
1430 	/* assert IB preemption */
1431 	WREG32(sdma_gfx_preempt, 1);
1432 
1433 	/* poll the trailing fence */
1434 	for (i = 0; i < adev->usec_timeout; i++) {
1435 		if (ring->trail_seq ==
1436 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1437 			break;
1438 		udelay(1);
1439 	}
1440 
1441 	if (i >= adev->usec_timeout) {
1442 		r = -EINVAL;
1443 		DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1444 	}
1445 
1446 	/* deassert IB preemption */
1447 	WREG32(sdma_gfx_preempt, 0);
1448 
1449 	/* deassert the preemption condition */
1450 	amdgpu_ring_set_preempt_cond_exec(ring, true);
1451 	return r;
1452 }
1453 
1454 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1455 					struct amdgpu_irq_src *source,
1456 					unsigned type,
1457 					enum amdgpu_interrupt_state state)
1458 {
1459 	u32 sdma_cntl;
1460 
1461 	u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1462 
1463 	sdma_cntl = RREG32(reg_offset);
1464 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1465 		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1466 	WREG32(reg_offset, sdma_cntl);
1467 
1468 	return 0;
1469 }
1470 
1471 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1472 				      struct amdgpu_irq_src *source,
1473 				      struct amdgpu_iv_entry *entry)
1474 {
1475 	DRM_DEBUG("IH: SDMA trap\n");
1476 	switch (entry->client_id) {
1477 	case SOC15_IH_CLIENTID_SDMA0:
1478 		switch (entry->ring_id) {
1479 		case 0:
1480 			amdgpu_fence_process(&adev->sdma.instance[0].ring);
1481 			break;
1482 		case 1:
1483 			/* XXX compute */
1484 			break;
1485 		case 2:
1486 			/* XXX compute */
1487 			break;
1488 		case 3:
1489 			/* XXX page queue*/
1490 			break;
1491 		}
1492 		break;
1493 	case SOC15_IH_CLIENTID_SDMA1:
1494 		switch (entry->ring_id) {
1495 		case 0:
1496 			amdgpu_fence_process(&adev->sdma.instance[1].ring);
1497 			break;
1498 		case 1:
1499 			/* XXX compute */
1500 			break;
1501 		case 2:
1502 			/* XXX compute */
1503 			break;
1504 		case 3:
1505 			/* XXX page queue*/
1506 			break;
1507 		}
1508 		break;
1509 	case SOC15_IH_CLIENTID_SDMA2:
1510 		switch (entry->ring_id) {
1511 		case 0:
1512 			amdgpu_fence_process(&adev->sdma.instance[2].ring);
1513 			break;
1514 		case 1:
1515 			/* XXX compute */
1516 			break;
1517 		case 2:
1518 			/* XXX compute */
1519 			break;
1520 		case 3:
1521 			/* XXX page queue*/
1522 			break;
1523 		}
1524 		break;
1525 	case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1526 		switch (entry->ring_id) {
1527 		case 0:
1528 			amdgpu_fence_process(&adev->sdma.instance[3].ring);
1529 			break;
1530 		case 1:
1531 			/* XXX compute */
1532 			break;
1533 		case 2:
1534 			/* XXX compute */
1535 			break;
1536 		case 3:
1537 			/* XXX page queue*/
1538 			break;
1539 		}
1540 		break;
1541 	}
1542 	return 0;
1543 }
1544 
1545 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1546 					      struct amdgpu_irq_src *source,
1547 					      struct amdgpu_iv_entry *entry)
1548 {
1549 	return 0;
1550 }
1551 
1552 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1553 						       bool enable)
1554 {
1555 	uint32_t data, def;
1556 	int i;
1557 
1558 	for (i = 0; i < adev->sdma.num_instances; i++) {
1559 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1560 			/* Enable sdma clock gating */
1561 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1562 			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1563 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1564 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1565 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1566 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1567 				  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1568 			if (def != data)
1569 				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1570 		} else {
1571 			/* Disable sdma clock gating */
1572 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1573 			data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1574 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1575 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1576 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1577 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1578 				 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1579 			if (def != data)
1580 				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1581 		}
1582 	}
1583 }
1584 
1585 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1586 						      bool enable)
1587 {
1588 	uint32_t data, def;
1589 	int i;
1590 
1591 	for (i = 0; i < adev->sdma.num_instances; i++) {
1592 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1593 			/* Enable sdma mem light sleep */
1594 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1595 			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1596 			if (def != data)
1597 				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1598 
1599 		} else {
1600 			/* Disable sdma mem light sleep */
1601 			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1602 			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1603 			if (def != data)
1604 				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1605 
1606 		}
1607 	}
1608 }
1609 
1610 static int sdma_v5_2_set_clockgating_state(void *handle,
1611 					   enum amd_clockgating_state state)
1612 {
1613 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1614 
1615 	if (amdgpu_sriov_vf(adev))
1616 		return 0;
1617 
1618 	switch (adev->asic_type) {
1619 	case CHIP_SIENNA_CICHLID:
1620 	case CHIP_NAVY_FLOUNDER:
1621 	case CHIP_VANGOGH:
1622 	case CHIP_DIMGREY_CAVEFISH:
1623 		sdma_v5_2_update_medium_grain_clock_gating(adev,
1624 				state == AMD_CG_STATE_GATE);
1625 		sdma_v5_2_update_medium_grain_light_sleep(adev,
1626 				state == AMD_CG_STATE_GATE);
1627 		break;
1628 	default:
1629 		break;
1630 	}
1631 
1632 	return 0;
1633 }
1634 
1635 static int sdma_v5_2_set_powergating_state(void *handle,
1636 					  enum amd_powergating_state state)
1637 {
1638 	return 0;
1639 }
1640 
1641 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1642 {
1643 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1644 	int data;
1645 
1646 	if (amdgpu_sriov_vf(adev))
1647 		*flags = 0;
1648 
1649 	/* AMD_CG_SUPPORT_SDMA_LS */
1650 	data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1651 	if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1652 		*flags |= AMD_CG_SUPPORT_SDMA_LS;
1653 }
1654 
1655 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1656 	.name = "sdma_v5_2",
1657 	.early_init = sdma_v5_2_early_init,
1658 	.late_init = NULL,
1659 	.sw_init = sdma_v5_2_sw_init,
1660 	.sw_fini = sdma_v5_2_sw_fini,
1661 	.hw_init = sdma_v5_2_hw_init,
1662 	.hw_fini = sdma_v5_2_hw_fini,
1663 	.suspend = sdma_v5_2_suspend,
1664 	.resume = sdma_v5_2_resume,
1665 	.is_idle = sdma_v5_2_is_idle,
1666 	.wait_for_idle = sdma_v5_2_wait_for_idle,
1667 	.soft_reset = sdma_v5_2_soft_reset,
1668 	.set_clockgating_state = sdma_v5_2_set_clockgating_state,
1669 	.set_powergating_state = sdma_v5_2_set_powergating_state,
1670 	.get_clockgating_state = sdma_v5_2_get_clockgating_state,
1671 };
1672 
1673 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1674 	.type = AMDGPU_RING_TYPE_SDMA,
1675 	.align_mask = 0xf,
1676 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1677 	.support_64bit_ptrs = true,
1678 	.vmhub = AMDGPU_GFXHUB_0,
1679 	.get_rptr = sdma_v5_2_ring_get_rptr,
1680 	.get_wptr = sdma_v5_2_ring_get_wptr,
1681 	.set_wptr = sdma_v5_2_ring_set_wptr,
1682 	.emit_frame_size =
1683 		5 + /* sdma_v5_2_ring_init_cond_exec */
1684 		6 + /* sdma_v5_2_ring_emit_hdp_flush */
1685 		3 + /* hdp_invalidate */
1686 		6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1687 		/* sdma_v5_2_ring_emit_vm_flush */
1688 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1689 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1690 		10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1691 	.emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1692 	.emit_ib = sdma_v5_2_ring_emit_ib,
1693 	.emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1694 	.emit_fence = sdma_v5_2_ring_emit_fence,
1695 	.emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1696 	.emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1697 	.emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1698 	.test_ring = sdma_v5_2_ring_test_ring,
1699 	.test_ib = sdma_v5_2_ring_test_ib,
1700 	.insert_nop = sdma_v5_2_ring_insert_nop,
1701 	.pad_ib = sdma_v5_2_ring_pad_ib,
1702 	.emit_wreg = sdma_v5_2_ring_emit_wreg,
1703 	.emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1704 	.emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1705 	.init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1706 	.patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1707 	.preempt_ib = sdma_v5_2_ring_preempt_ib,
1708 };
1709 
1710 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1711 {
1712 	int i;
1713 
1714 	for (i = 0; i < adev->sdma.num_instances; i++) {
1715 		adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1716 		adev->sdma.instance[i].ring.me = i;
1717 	}
1718 }
1719 
1720 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1721 	.set = sdma_v5_2_set_trap_irq_state,
1722 	.process = sdma_v5_2_process_trap_irq,
1723 };
1724 
1725 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1726 	.process = sdma_v5_2_process_illegal_inst_irq,
1727 };
1728 
1729 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1730 {
1731 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1732 					adev->sdma.num_instances;
1733 	adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1734 	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1735 }
1736 
1737 /**
1738  * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1739  *
1740  * @ib: indirect buffer to copy to
1741  * @src_offset: src GPU address
1742  * @dst_offset: dst GPU address
1743  * @byte_count: number of bytes to xfer
1744  * @tmz: if a secure copy should be used
1745  *
1746  * Copy GPU buffers using the DMA engine.
1747  * Used by the amdgpu ttm implementation to move pages if
1748  * registered as the asic copy callback.
1749  */
1750 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1751 				       uint64_t src_offset,
1752 				       uint64_t dst_offset,
1753 				       uint32_t byte_count,
1754 				       bool tmz)
1755 {
1756 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1757 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1758 		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1759 	ib->ptr[ib->length_dw++] = byte_count - 1;
1760 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1761 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1762 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1763 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1764 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1765 }
1766 
1767 /**
1768  * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1769  *
1770  * @ib: indirect buffer to fill
1771  * @src_data: value to write to buffer
1772  * @dst_offset: dst GPU address
1773  * @byte_count: number of bytes to xfer
1774  *
1775  * Fill GPU buffers using the DMA engine.
1776  */
1777 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1778 				       uint32_t src_data,
1779 				       uint64_t dst_offset,
1780 				       uint32_t byte_count)
1781 {
1782 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1783 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1784 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1785 	ib->ptr[ib->length_dw++] = src_data;
1786 	ib->ptr[ib->length_dw++] = byte_count - 1;
1787 }
1788 
1789 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1790 	.copy_max_bytes = 0x400000,
1791 	.copy_num_dw = 7,
1792 	.emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1793 
1794 	.fill_max_bytes = 0x400000,
1795 	.fill_num_dw = 5,
1796 	.emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1797 };
1798 
1799 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1800 {
1801 	if (adev->mman.buffer_funcs == NULL) {
1802 		adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1803 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1804 	}
1805 }
1806 
1807 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1808 	.copy_pte_num_dw = 7,
1809 	.copy_pte = sdma_v5_2_vm_copy_pte,
1810 	.write_pte = sdma_v5_2_vm_write_pte,
1811 	.set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1812 };
1813 
1814 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1815 {
1816 	unsigned i;
1817 
1818 	if (adev->vm_manager.vm_pte_funcs == NULL) {
1819 		adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1820 		for (i = 0; i < adev->sdma.num_instances; i++) {
1821 			adev->vm_manager.vm_pte_scheds[i] =
1822 				&adev->sdma.instance[i].ring.sched;
1823 		}
1824 		adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1825 	}
1826 }
1827 
1828 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1829 	.type = AMD_IP_BLOCK_TYPE_SDMA,
1830 	.major = 5,
1831 	.minor = 2,
1832 	.rev = 0,
1833 	.funcs = &sdma_v5_2_ip_funcs,
1834 };
1835