1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_3_0_offset.h" 34 #include "gc/gc_10_3_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" 38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "navi10_sdma_pkt_open.h" 43 #include "nbio_v2_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v5_2.h" 46 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 49 50 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); 51 52 #define SDMA1_REG_OFFSET 0x600 53 #define SDMA3_REG_OFFSET 0x400 54 #define SDMA0_HYP_DEC_REG_START 0x5880 55 #define SDMA0_HYP_DEC_REG_END 0x5893 56 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 57 58 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 59 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 60 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 61 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 62 63 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 64 { 65 u32 base; 66 67 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 68 internal_offset <= SDMA0_HYP_DEC_REG_END) { 69 base = adev->reg_offset[GC_HWIP][0][1]; 70 if (instance != 0) 71 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 72 } else { 73 if (instance < 2) { 74 base = adev->reg_offset[GC_HWIP][0][0]; 75 if (instance == 1) 76 internal_offset += SDMA1_REG_OFFSET; 77 } else { 78 base = adev->reg_offset[GC_HWIP][0][2]; 79 if (instance == 3) 80 internal_offset += SDMA3_REG_OFFSET; 81 } 82 } 83 84 return base + internal_offset; 85 } 86 87 static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev) 88 { 89 switch (adev->asic_type) { 90 case CHIP_SIENNA_CICHLID: 91 case CHIP_NAVY_FLOUNDER: 92 case CHIP_VANGOGH: 93 break; 94 default: 95 break; 96 } 97 } 98 99 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 100 { 101 int err = 0; 102 const struct sdma_firmware_header_v1_0 *hdr; 103 104 err = amdgpu_ucode_validate(sdma_inst->fw); 105 if (err) 106 return err; 107 108 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 109 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 110 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 111 112 if (sdma_inst->feature_version >= 20) 113 sdma_inst->burst_nop = true; 114 115 return 0; 116 } 117 118 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev) 119 { 120 int i; 121 122 for (i = 0; i < adev->sdma.num_instances; i++) { 123 release_firmware(adev->sdma.instance[i].fw); 124 adev->sdma.instance[i].fw = NULL; 125 126 if (adev->asic_type == CHIP_SIENNA_CICHLID) 127 break; 128 } 129 130 memset((void*)adev->sdma.instance, 0, 131 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 132 } 133 134 /** 135 * sdma_v5_2_init_microcode - load ucode images from disk 136 * 137 * @adev: amdgpu_device pointer 138 * 139 * Use the firmware interface to load the ucode images into 140 * the driver (not loaded into hw). 141 * Returns 0 on success, error on failure. 142 */ 143 144 // emulation only, won't work on real chip 145 // navi10 real chip need to use PSP to load firmware 146 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) 147 { 148 const char *chip_name; 149 char fw_name[40]; 150 int err = 0, i; 151 struct amdgpu_firmware_info *info = NULL; 152 const struct common_firmware_header *header = NULL; 153 154 if (amdgpu_sriov_vf(adev)) 155 return 0; 156 157 DRM_DEBUG("\n"); 158 159 switch (adev->asic_type) { 160 case CHIP_SIENNA_CICHLID: 161 chip_name = "sienna_cichlid"; 162 break; 163 case CHIP_NAVY_FLOUNDER: 164 chip_name = "navy_flounder"; 165 break; 166 case CHIP_VANGOGH: 167 chip_name = "vangogh"; 168 break; 169 default: 170 BUG(); 171 } 172 173 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 174 175 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 176 if (err) 177 goto out; 178 179 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]); 180 if (err) 181 goto out; 182 183 for (i = 1; i < adev->sdma.num_instances; i++) { 184 if (adev->asic_type == CHIP_SIENNA_CICHLID || 185 adev->asic_type == CHIP_NAVY_FLOUNDER) { 186 memcpy((void*)&adev->sdma.instance[i], 187 (void*)&adev->sdma.instance[0], 188 sizeof(struct amdgpu_sdma_instance)); 189 } else { 190 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i); 191 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 192 if (err) 193 goto out; 194 195 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]); 196 if (err) 197 goto out; 198 } 199 } 200 201 DRM_DEBUG("psp_load == '%s'\n", 202 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 203 204 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 205 for (i = 0; i < adev->sdma.num_instances; i++) { 206 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 207 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 208 info->fw = adev->sdma.instance[i].fw; 209 header = (const struct common_firmware_header *)info->fw->data; 210 adev->firmware.fw_size += 211 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 212 } 213 } 214 215 out: 216 if (err) { 217 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name); 218 sdma_v5_2_destroy_inst_ctx(adev); 219 } 220 return err; 221 } 222 223 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) 224 { 225 unsigned ret; 226 227 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 228 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 229 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 230 amdgpu_ring_write(ring, 1); 231 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 232 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 233 234 return ret; 235 } 236 237 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring, 238 unsigned offset) 239 { 240 unsigned cur; 241 242 BUG_ON(offset > ring->buf_mask); 243 BUG_ON(ring->ring[offset] != 0x55aa55aa); 244 245 cur = (ring->wptr - 1) & ring->buf_mask; 246 if (cur > offset) 247 ring->ring[offset] = cur - offset; 248 else 249 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 250 } 251 252 /** 253 * sdma_v5_2_ring_get_rptr - get the current read pointer 254 * 255 * @ring: amdgpu ring pointer 256 * 257 * Get the current rptr from the hardware (NAVI10+). 258 */ 259 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) 260 { 261 u64 *rptr; 262 263 /* XXX check if swapping is necessary on BE */ 264 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 265 266 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 267 return ((*rptr) >> 2); 268 } 269 270 /** 271 * sdma_v5_2_ring_get_wptr - get the current write pointer 272 * 273 * @ring: amdgpu ring pointer 274 * 275 * Get the current wptr from the hardware (NAVI10+). 276 */ 277 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) 278 { 279 struct amdgpu_device *adev = ring->adev; 280 u64 wptr; 281 282 if (ring->use_doorbell) { 283 /* XXX check if swapping is necessary on BE */ 284 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 285 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 286 } else { 287 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 288 wptr = wptr << 32; 289 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 290 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 291 } 292 293 return wptr >> 2; 294 } 295 296 /** 297 * sdma_v5_2_ring_set_wptr - commit the write pointer 298 * 299 * @ring: amdgpu ring pointer 300 * 301 * Write the wptr back to the hardware (NAVI10+). 302 */ 303 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) 304 { 305 struct amdgpu_device *adev = ring->adev; 306 307 DRM_DEBUG("Setting write pointer\n"); 308 if (ring->use_doorbell) { 309 DRM_DEBUG("Using doorbell -- " 310 "wptr_offs == 0x%08x " 311 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 312 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 313 ring->wptr_offs, 314 lower_32_bits(ring->wptr << 2), 315 upper_32_bits(ring->wptr << 2)); 316 /* XXX check if swapping is necessary on BE */ 317 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 318 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 319 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 320 ring->doorbell_index, ring->wptr << 2); 321 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 322 } else { 323 DRM_DEBUG("Not using doorbell -- " 324 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 325 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 326 ring->me, 327 lower_32_bits(ring->wptr << 2), 328 ring->me, 329 upper_32_bits(ring->wptr << 2)); 330 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 331 lower_32_bits(ring->wptr << 2)); 332 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 333 upper_32_bits(ring->wptr << 2)); 334 } 335 } 336 337 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 338 { 339 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 340 int i; 341 342 for (i = 0; i < count; i++) 343 if (sdma && sdma->burst_nop && (i == 0)) 344 amdgpu_ring_write(ring, ring->funcs->nop | 345 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 346 else 347 amdgpu_ring_write(ring, ring->funcs->nop); 348 } 349 350 /** 351 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine 352 * 353 * @ring: amdgpu ring pointer 354 * @ib: IB object to schedule 355 * 356 * Schedule an IB in the DMA ring. 357 */ 358 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, 359 struct amdgpu_job *job, 360 struct amdgpu_ib *ib, 361 uint32_t flags) 362 { 363 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 364 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 365 366 /* An IB packet must end on a 8 DW boundary--the next dword 367 * must be on a 8-dword boundary. Our IB packet below is 6 368 * dwords long, thus add x number of NOPs, such that, in 369 * modular arithmetic, 370 * wptr + 6 + x = 8k, k >= 0, which in C is, 371 * (wptr + 6 + x) % 8 = 0. 372 * The expression below, is a solution of x. 373 */ 374 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 375 376 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 377 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 378 /* base must be 32 byte aligned */ 379 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 380 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 381 amdgpu_ring_write(ring, ib->length_dw); 382 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 383 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 384 } 385 386 /** 387 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 388 * 389 * @ring: amdgpu ring pointer 390 * 391 * Emit an hdp flush packet on the requested DMA ring. 392 */ 393 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 394 { 395 struct amdgpu_device *adev = ring->adev; 396 u32 ref_and_mask = 0; 397 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 398 399 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 400 401 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 402 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 403 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 404 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 405 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 406 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 407 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 408 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 409 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 410 } 411 412 /** 413 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring 414 * 415 * @ring: amdgpu ring pointer 416 * @fence: amdgpu fence object 417 * 418 * Add a DMA fence packet to the ring to write 419 * the fence seq number and DMA trap packet to generate 420 * an interrupt if needed. 421 */ 422 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 423 unsigned flags) 424 { 425 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 426 /* write the fence */ 427 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 428 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 429 /* zero in first two bits */ 430 BUG_ON(addr & 0x3); 431 amdgpu_ring_write(ring, lower_32_bits(addr)); 432 amdgpu_ring_write(ring, upper_32_bits(addr)); 433 amdgpu_ring_write(ring, lower_32_bits(seq)); 434 435 /* optionally write high bits as well */ 436 if (write64bit) { 437 addr += 4; 438 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 439 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 440 /* zero in first two bits */ 441 BUG_ON(addr & 0x3); 442 amdgpu_ring_write(ring, lower_32_bits(addr)); 443 amdgpu_ring_write(ring, upper_32_bits(addr)); 444 amdgpu_ring_write(ring, upper_32_bits(seq)); 445 } 446 447 if (flags & AMDGPU_FENCE_FLAG_INT) { 448 /* generate an interrupt */ 449 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 450 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 451 } 452 } 453 454 455 /** 456 * sdma_v5_2_gfx_stop - stop the gfx async dma engines 457 * 458 * @adev: amdgpu_device pointer 459 * 460 * Stop the gfx async dma ring buffers. 461 */ 462 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) 463 { 464 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 465 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 466 struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring; 467 struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring; 468 u32 rb_cntl, ib_cntl; 469 int i; 470 471 if ((adev->mman.buffer_funcs_ring == sdma0) || 472 (adev->mman.buffer_funcs_ring == sdma1) || 473 (adev->mman.buffer_funcs_ring == sdma2) || 474 (adev->mman.buffer_funcs_ring == sdma3)) 475 amdgpu_ttm_set_buffer_funcs_status(adev, false); 476 477 for (i = 0; i < adev->sdma.num_instances; i++) { 478 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 479 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 480 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 481 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 482 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 483 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 484 } 485 486 sdma0->sched.ready = false; 487 sdma1->sched.ready = false; 488 sdma2->sched.ready = false; 489 sdma3->sched.ready = false; 490 } 491 492 /** 493 * sdma_v5_2_rlc_stop - stop the compute async dma engines 494 * 495 * @adev: amdgpu_device pointer 496 * 497 * Stop the compute async dma queues. 498 */ 499 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) 500 { 501 /* XXX todo */ 502 } 503 504 /** 505 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 506 * 507 * @adev: amdgpu_device pointer 508 * @enable: enable/disable the DMA MEs context switch. 509 * 510 * Halt or unhalt the async dma engines context switch. 511 */ 512 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 513 { 514 u32 f32_cntl, phase_quantum = 0; 515 int i; 516 517 if (amdgpu_sdma_phase_quantum) { 518 unsigned value = amdgpu_sdma_phase_quantum; 519 unsigned unit = 0; 520 521 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 522 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 523 value = (value + 1) >> 1; 524 unit++; 525 } 526 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 527 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 528 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 529 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 530 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 531 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 532 WARN_ONCE(1, 533 "clamping sdma_phase_quantum to %uK clock cycles\n", 534 value << unit); 535 } 536 phase_quantum = 537 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 538 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 539 } 540 541 for (i = 0; i < adev->sdma.num_instances; i++) { 542 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 543 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 544 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 545 if (enable && amdgpu_sdma_phase_quantum) { 546 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 547 phase_quantum); 548 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 549 phase_quantum); 550 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 551 phase_quantum); 552 } 553 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 554 } 555 556 } 557 558 /** 559 * sdma_v5_2_enable - stop the async dma engines 560 * 561 * @adev: amdgpu_device pointer 562 * @enable: enable/disable the DMA MEs. 563 * 564 * Halt or unhalt the async dma engines. 565 */ 566 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) 567 { 568 u32 f32_cntl; 569 int i; 570 571 if (!enable) { 572 sdma_v5_2_gfx_stop(adev); 573 sdma_v5_2_rlc_stop(adev); 574 } 575 576 for (i = 0; i < adev->sdma.num_instances; i++) { 577 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 578 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 579 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 580 } 581 } 582 583 /** 584 * sdma_v5_2_gfx_resume - setup and start the async dma engines 585 * 586 * @adev: amdgpu_device pointer 587 * 588 * Set up the gfx DMA ring buffers and enable them. 589 * Returns 0 for success, error for failure. 590 */ 591 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 592 { 593 struct amdgpu_ring *ring; 594 u32 rb_cntl, ib_cntl; 595 u32 rb_bufsz; 596 u32 wb_offset; 597 u32 doorbell; 598 u32 doorbell_offset; 599 u32 temp; 600 u32 wptr_poll_cntl; 601 u64 wptr_gpu_addr; 602 int i, r; 603 604 for (i = 0; i < adev->sdma.num_instances; i++) { 605 ring = &adev->sdma.instance[i].ring; 606 wb_offset = (ring->rptr_offs * 4); 607 608 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 609 610 /* Set ring buffer size in dwords */ 611 rb_bufsz = order_base_2(ring->ring_size / 4); 612 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 613 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 614 #ifdef __BIG_ENDIAN 615 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 616 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 617 RPTR_WRITEBACK_SWAP_ENABLE, 1); 618 #endif 619 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 620 621 /* Initialize the ring buffer's read and write pointers */ 622 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 623 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 624 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 625 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 626 627 /* setup the wptr shadow polling */ 628 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 629 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 630 lower_32_bits(wptr_gpu_addr)); 631 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 632 upper_32_bits(wptr_gpu_addr)); 633 wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, 634 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 635 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 636 SDMA0_GFX_RB_WPTR_POLL_CNTL, 637 F32_POLL_ENABLE, 1); 638 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 639 wptr_poll_cntl); 640 641 /* set the wb address whether it's enabled or not */ 642 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 643 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 644 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 645 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 646 647 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 648 649 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 650 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 651 652 ring->wptr = 0; 653 654 /* before programing wptr to a less value, need set minor_ptr_update first */ 655 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 656 657 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 658 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 659 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 660 } 661 662 doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 663 doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 664 665 if (ring->use_doorbell) { 666 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 667 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 668 OFFSET, ring->doorbell_index); 669 } else { 670 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 671 } 672 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 673 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 674 675 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 676 ring->doorbell_index, 677 adev->doorbell_index.sdma_doorbell_range); 678 679 if (amdgpu_sriov_vf(adev)) 680 sdma_v5_2_ring_set_wptr(ring); 681 682 /* set minor_ptr_update to 0 after wptr programed */ 683 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 684 685 /* set utc l1 enable flag always to 1 */ 686 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 687 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 688 689 /* enable MCBP */ 690 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 691 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 692 693 /* Set up RESP_MODE to non-copy addresses */ 694 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 695 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 696 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 697 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 698 699 /* program default cache read and write policy */ 700 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 701 /* clean read policy and write policy bits */ 702 temp &= 0xFF0FFF; 703 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 704 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 705 0x01000000); 706 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 707 708 if (!amdgpu_sriov_vf(adev)) { 709 /* unhalt engine */ 710 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 711 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 712 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 713 } 714 715 /* enable DMA RB */ 716 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 717 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 718 719 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 720 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 721 #ifdef __BIG_ENDIAN 722 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 723 #endif 724 /* enable DMA IBs */ 725 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 726 727 ring->sched.ready = true; 728 729 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 730 sdma_v5_2_ctx_switch_enable(adev, true); 731 sdma_v5_2_enable(adev, true); 732 } 733 734 r = amdgpu_ring_test_ring(ring); 735 if (r) { 736 ring->sched.ready = false; 737 return r; 738 } 739 740 if (adev->mman.buffer_funcs_ring == ring) 741 amdgpu_ttm_set_buffer_funcs_status(adev, true); 742 } 743 744 return 0; 745 } 746 747 /** 748 * sdma_v5_2_rlc_resume - setup and start the async dma engines 749 * 750 * @adev: amdgpu_device pointer 751 * 752 * Set up the compute DMA queues and enable them. 753 * Returns 0 for success, error for failure. 754 */ 755 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) 756 { 757 return 0; 758 } 759 760 /** 761 * sdma_v5_2_load_microcode - load the sDMA ME ucode 762 * 763 * @adev: amdgpu_device pointer 764 * 765 * Loads the sDMA0/1/2/3 ucode. 766 * Returns 0 for success, -EINVAL if the ucode is not available. 767 */ 768 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) 769 { 770 const struct sdma_firmware_header_v1_0 *hdr; 771 const __le32 *fw_data; 772 u32 fw_size; 773 int i, j; 774 775 /* halt the MEs */ 776 sdma_v5_2_enable(adev, false); 777 778 for (i = 0; i < adev->sdma.num_instances; i++) { 779 if (!adev->sdma.instance[i].fw) 780 return -EINVAL; 781 782 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 783 amdgpu_ucode_print_sdma_hdr(&hdr->header); 784 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 785 786 fw_data = (const __le32 *) 787 (adev->sdma.instance[i].fw->data + 788 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 789 790 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 791 792 for (j = 0; j < fw_size; j++) { 793 if (amdgpu_emu_mode == 1 && j % 500 == 0) 794 msleep(1); 795 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 796 } 797 798 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 799 } 800 801 return 0; 802 } 803 804 /** 805 * sdma_v5_2_start - setup and start the async dma engines 806 * 807 * @adev: amdgpu_device pointer 808 * 809 * Set up the DMA engines and enable them. 810 * Returns 0 for success, error for failure. 811 */ 812 static int sdma_v5_2_start(struct amdgpu_device *adev) 813 { 814 int r = 0; 815 816 if (amdgpu_sriov_vf(adev)) { 817 sdma_v5_2_ctx_switch_enable(adev, false); 818 sdma_v5_2_enable(adev, false); 819 820 /* set RB registers */ 821 r = sdma_v5_2_gfx_resume(adev); 822 return r; 823 } 824 825 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 826 r = sdma_v5_2_load_microcode(adev); 827 if (r) 828 return r; 829 830 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 831 if (amdgpu_emu_mode == 1) 832 msleep(1000); 833 } 834 835 /* unhalt the MEs */ 836 sdma_v5_2_enable(adev, true); 837 /* enable sdma ring preemption */ 838 sdma_v5_2_ctx_switch_enable(adev, true); 839 840 /* start the gfx rings and rlc compute queues */ 841 r = sdma_v5_2_gfx_resume(adev); 842 if (r) 843 return r; 844 r = sdma_v5_2_rlc_resume(adev); 845 846 return r; 847 } 848 849 /** 850 * sdma_v5_2_ring_test_ring - simple async dma engine test 851 * 852 * @ring: amdgpu_ring structure holding ring information 853 * 854 * Test the DMA engine by writing using it to write an 855 * value to memory. 856 * Returns 0 for success, error for failure. 857 */ 858 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) 859 { 860 struct amdgpu_device *adev = ring->adev; 861 unsigned i; 862 unsigned index; 863 int r; 864 u32 tmp; 865 u64 gpu_addr; 866 867 r = amdgpu_device_wb_get(adev, &index); 868 if (r) { 869 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 870 return r; 871 } 872 873 gpu_addr = adev->wb.gpu_addr + (index * 4); 874 tmp = 0xCAFEDEAD; 875 adev->wb.wb[index] = cpu_to_le32(tmp); 876 877 r = amdgpu_ring_alloc(ring, 5); 878 if (r) { 879 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 880 amdgpu_device_wb_free(adev, index); 881 return r; 882 } 883 884 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 885 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 886 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 887 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 888 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 889 amdgpu_ring_write(ring, 0xDEADBEEF); 890 amdgpu_ring_commit(ring); 891 892 for (i = 0; i < adev->usec_timeout; i++) { 893 tmp = le32_to_cpu(adev->wb.wb[index]); 894 if (tmp == 0xDEADBEEF) 895 break; 896 if (amdgpu_emu_mode == 1) 897 msleep(1); 898 else 899 udelay(1); 900 } 901 902 if (i >= adev->usec_timeout) 903 r = -ETIMEDOUT; 904 905 amdgpu_device_wb_free(adev, index); 906 907 return r; 908 } 909 910 /** 911 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine 912 * 913 * @ring: amdgpu_ring structure holding ring information 914 * 915 * Test a simple IB in the DMA ring. 916 * Returns 0 on success, error on failure. 917 */ 918 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 919 { 920 struct amdgpu_device *adev = ring->adev; 921 struct amdgpu_ib ib; 922 struct dma_fence *f = NULL; 923 unsigned index; 924 long r; 925 u32 tmp = 0; 926 u64 gpu_addr; 927 928 r = amdgpu_device_wb_get(adev, &index); 929 if (r) { 930 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 931 return r; 932 } 933 934 gpu_addr = adev->wb.gpu_addr + (index * 4); 935 tmp = 0xCAFEDEAD; 936 adev->wb.wb[index] = cpu_to_le32(tmp); 937 memset(&ib, 0, sizeof(ib)); 938 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 939 if (r) { 940 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 941 goto err0; 942 } 943 944 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 945 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 946 ib.ptr[1] = lower_32_bits(gpu_addr); 947 ib.ptr[2] = upper_32_bits(gpu_addr); 948 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 949 ib.ptr[4] = 0xDEADBEEF; 950 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 951 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 952 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 953 ib.length_dw = 8; 954 955 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 956 if (r) 957 goto err1; 958 959 r = dma_fence_wait_timeout(f, false, timeout); 960 if (r == 0) { 961 DRM_ERROR("amdgpu: IB test timed out\n"); 962 r = -ETIMEDOUT; 963 goto err1; 964 } else if (r < 0) { 965 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 966 goto err1; 967 } 968 tmp = le32_to_cpu(adev->wb.wb[index]); 969 if (tmp == 0xDEADBEEF) 970 r = 0; 971 else 972 r = -EINVAL; 973 974 err1: 975 amdgpu_ib_free(adev, &ib, NULL); 976 dma_fence_put(f); 977 err0: 978 amdgpu_device_wb_free(adev, index); 979 return r; 980 } 981 982 983 /** 984 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART 985 * 986 * @ib: indirect buffer to fill with commands 987 * @pe: addr of the page entry 988 * @src: src addr to copy from 989 * @count: number of page entries to update 990 * 991 * Update PTEs by copying them from the GART using sDMA. 992 */ 993 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, 994 uint64_t pe, uint64_t src, 995 unsigned count) 996 { 997 unsigned bytes = count * 8; 998 999 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1000 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1001 ib->ptr[ib->length_dw++] = bytes - 1; 1002 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1003 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1004 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1005 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1006 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1007 1008 } 1009 1010 /** 1011 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually 1012 * 1013 * @ib: indirect buffer to fill with commands 1014 * @pe: addr of the page entry 1015 * @addr: dst addr to write into pe 1016 * @count: number of page entries to update 1017 * @incr: increase next addr by incr bytes 1018 * @flags: access flags 1019 * 1020 * Update PTEs by writing them manually using sDMA. 1021 */ 1022 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1023 uint64_t value, unsigned count, 1024 uint32_t incr) 1025 { 1026 unsigned ndw = count * 2; 1027 1028 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1029 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1030 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1031 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1032 ib->ptr[ib->length_dw++] = ndw - 1; 1033 for (; ndw > 0; ndw -= 2) { 1034 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1035 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1036 value += incr; 1037 } 1038 } 1039 1040 /** 1041 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA 1042 * 1043 * @ib: indirect buffer to fill with commands 1044 * @pe: addr of the page entry 1045 * @addr: dst addr to write into pe 1046 * @count: number of page entries to update 1047 * @incr: increase next addr by incr bytes 1048 * @flags: access flags 1049 * 1050 * Update the page tables using sDMA. 1051 */ 1052 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1053 uint64_t pe, 1054 uint64_t addr, unsigned count, 1055 uint32_t incr, uint64_t flags) 1056 { 1057 /* for physically contiguous pages (vram) */ 1058 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1059 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1060 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1061 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1062 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1063 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1064 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1065 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1066 ib->ptr[ib->length_dw++] = 0; 1067 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1068 } 1069 1070 /** 1071 * sdma_v5_2_ring_pad_ib - pad the IB 1072 * 1073 * @ib: indirect buffer to fill with padding 1074 * 1075 * Pad the IB with NOPs to a boundary multiple of 8. 1076 */ 1077 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1078 { 1079 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1080 u32 pad_count; 1081 int i; 1082 1083 pad_count = (-ib->length_dw) & 0x7; 1084 for (i = 0; i < pad_count; i++) 1085 if (sdma && sdma->burst_nop && (i == 0)) 1086 ib->ptr[ib->length_dw++] = 1087 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1088 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1089 else 1090 ib->ptr[ib->length_dw++] = 1091 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1092 } 1093 1094 1095 /** 1096 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline 1097 * 1098 * @ring: amdgpu_ring pointer 1099 * 1100 * Make sure all previous operations are completed (CIK). 1101 */ 1102 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1103 { 1104 uint32_t seq = ring->fence_drv.sync_seq; 1105 uint64_t addr = ring->fence_drv.gpu_addr; 1106 1107 /* wait for idle */ 1108 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1109 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1110 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1111 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1112 amdgpu_ring_write(ring, addr & 0xfffffffc); 1113 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1114 amdgpu_ring_write(ring, seq); /* reference */ 1115 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1116 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1117 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1118 } 1119 1120 1121 /** 1122 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA 1123 * 1124 * @ring: amdgpu_ring pointer 1125 * @vm: amdgpu_vm pointer 1126 * 1127 * Update the page table base and flush the VM TLB 1128 * using sDMA. 1129 */ 1130 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1131 unsigned vmid, uint64_t pd_addr) 1132 { 1133 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1134 } 1135 1136 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, 1137 uint32_t reg, uint32_t val) 1138 { 1139 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1140 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1141 amdgpu_ring_write(ring, reg); 1142 amdgpu_ring_write(ring, val); 1143 } 1144 1145 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1146 uint32_t val, uint32_t mask) 1147 { 1148 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1149 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1150 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1151 amdgpu_ring_write(ring, reg << 2); 1152 amdgpu_ring_write(ring, 0); 1153 amdgpu_ring_write(ring, val); /* reference */ 1154 amdgpu_ring_write(ring, mask); /* mask */ 1155 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1156 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1157 } 1158 1159 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1160 uint32_t reg0, uint32_t reg1, 1161 uint32_t ref, uint32_t mask) 1162 { 1163 amdgpu_ring_emit_wreg(ring, reg0, ref); 1164 /* wait for a cycle to reset vm_inv_eng*_ack */ 1165 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1166 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1167 } 1168 1169 static int sdma_v5_2_early_init(void *handle) 1170 { 1171 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1172 1173 switch (adev->asic_type) { 1174 case CHIP_SIENNA_CICHLID: 1175 adev->sdma.num_instances = 4; 1176 break; 1177 case CHIP_NAVY_FLOUNDER: 1178 adev->sdma.num_instances = 2; 1179 break; 1180 case CHIP_VANGOGH: 1181 adev->sdma.num_instances = 1; 1182 break; 1183 default: 1184 break; 1185 } 1186 1187 sdma_v5_2_set_ring_funcs(adev); 1188 sdma_v5_2_set_buffer_funcs(adev); 1189 sdma_v5_2_set_vm_pte_funcs(adev); 1190 sdma_v5_2_set_irq_funcs(adev); 1191 1192 return 0; 1193 } 1194 1195 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) 1196 { 1197 switch (seq_num) { 1198 case 0: 1199 return SOC15_IH_CLIENTID_SDMA0; 1200 case 1: 1201 return SOC15_IH_CLIENTID_SDMA1; 1202 case 2: 1203 return SOC15_IH_CLIENTID_SDMA2; 1204 case 3: 1205 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; 1206 default: 1207 break; 1208 } 1209 return -EINVAL; 1210 } 1211 1212 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) 1213 { 1214 switch (seq_num) { 1215 case 0: 1216 return SDMA0_5_0__SRCID__SDMA_TRAP; 1217 case 1: 1218 return SDMA1_5_0__SRCID__SDMA_TRAP; 1219 case 2: 1220 return SDMA2_5_0__SRCID__SDMA_TRAP; 1221 case 3: 1222 return SDMA3_5_0__SRCID__SDMA_TRAP; 1223 default: 1224 break; 1225 } 1226 return -EINVAL; 1227 } 1228 1229 static int sdma_v5_2_sw_init(void *handle) 1230 { 1231 struct amdgpu_ring *ring; 1232 int r, i; 1233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1234 1235 /* SDMA trap event */ 1236 for (i = 0; i < adev->sdma.num_instances; i++) { 1237 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), 1238 sdma_v5_2_seq_to_trap_id(i), 1239 &adev->sdma.trap_irq); 1240 if (r) 1241 return r; 1242 } 1243 1244 r = sdma_v5_2_init_microcode(adev); 1245 if (r) { 1246 DRM_ERROR("Failed to load sdma firmware!\n"); 1247 return r; 1248 } 1249 1250 for (i = 0; i < adev->sdma.num_instances; i++) { 1251 ring = &adev->sdma.instance[i].ring; 1252 ring->ring_obj = NULL; 1253 ring->use_doorbell = true; 1254 ring->me = i; 1255 1256 DRM_INFO("use_doorbell being set to: [%s]\n", 1257 ring->use_doorbell?"true":"false"); 1258 1259 ring->doorbell_index = 1260 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1261 1262 sprintf(ring->name, "sdma%d", i); 1263 r = amdgpu_ring_init(adev, ring, 1024, 1264 &adev->sdma.trap_irq, 1265 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1266 AMDGPU_RING_PRIO_DEFAULT); 1267 if (r) 1268 return r; 1269 } 1270 1271 return r; 1272 } 1273 1274 static int sdma_v5_2_sw_fini(void *handle) 1275 { 1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1277 int i; 1278 1279 for (i = 0; i < adev->sdma.num_instances; i++) 1280 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1281 1282 sdma_v5_2_destroy_inst_ctx(adev); 1283 1284 return 0; 1285 } 1286 1287 static int sdma_v5_2_hw_init(void *handle) 1288 { 1289 int r; 1290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1291 1292 sdma_v5_2_init_golden_registers(adev); 1293 1294 r = sdma_v5_2_start(adev); 1295 1296 return r; 1297 } 1298 1299 static int sdma_v5_2_hw_fini(void *handle) 1300 { 1301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1302 1303 if (amdgpu_sriov_vf(adev)) 1304 return 0; 1305 1306 sdma_v5_2_ctx_switch_enable(adev, false); 1307 sdma_v5_2_enable(adev, false); 1308 1309 return 0; 1310 } 1311 1312 static int sdma_v5_2_suspend(void *handle) 1313 { 1314 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1315 1316 return sdma_v5_2_hw_fini(adev); 1317 } 1318 1319 static int sdma_v5_2_resume(void *handle) 1320 { 1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1322 1323 return sdma_v5_2_hw_init(adev); 1324 } 1325 1326 static bool sdma_v5_2_is_idle(void *handle) 1327 { 1328 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1329 u32 i; 1330 1331 for (i = 0; i < adev->sdma.num_instances; i++) { 1332 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1333 1334 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1335 return false; 1336 } 1337 1338 return true; 1339 } 1340 1341 static int sdma_v5_2_wait_for_idle(void *handle) 1342 { 1343 unsigned i; 1344 u32 sdma0, sdma1, sdma2, sdma3; 1345 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1346 1347 for (i = 0; i < adev->usec_timeout; i++) { 1348 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1349 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1350 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); 1351 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); 1352 1353 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK) 1354 return 0; 1355 udelay(1); 1356 } 1357 return -ETIMEDOUT; 1358 } 1359 1360 static int sdma_v5_2_soft_reset(void *handle) 1361 { 1362 /* todo */ 1363 1364 return 0; 1365 } 1366 1367 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) 1368 { 1369 int i, r = 0; 1370 struct amdgpu_device *adev = ring->adev; 1371 u32 index = 0; 1372 u64 sdma_gfx_preempt; 1373 1374 amdgpu_sdma_get_index_from_ring(ring, &index); 1375 sdma_gfx_preempt = 1376 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT); 1377 1378 /* assert preemption condition */ 1379 amdgpu_ring_set_preempt_cond_exec(ring, false); 1380 1381 /* emit the trailing fence */ 1382 ring->trail_seq += 1; 1383 amdgpu_ring_alloc(ring, 10); 1384 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1385 ring->trail_seq, 0); 1386 amdgpu_ring_commit(ring); 1387 1388 /* assert IB preemption */ 1389 WREG32(sdma_gfx_preempt, 1); 1390 1391 /* poll the trailing fence */ 1392 for (i = 0; i < adev->usec_timeout; i++) { 1393 if (ring->trail_seq == 1394 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1395 break; 1396 udelay(1); 1397 } 1398 1399 if (i >= adev->usec_timeout) { 1400 r = -EINVAL; 1401 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1402 } 1403 1404 /* deassert IB preemption */ 1405 WREG32(sdma_gfx_preempt, 0); 1406 1407 /* deassert the preemption condition */ 1408 amdgpu_ring_set_preempt_cond_exec(ring, true); 1409 return r; 1410 } 1411 1412 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, 1413 struct amdgpu_irq_src *source, 1414 unsigned type, 1415 enum amdgpu_interrupt_state state) 1416 { 1417 u32 sdma_cntl; 1418 1419 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); 1420 1421 sdma_cntl = RREG32(reg_offset); 1422 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1423 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1424 WREG32(reg_offset, sdma_cntl); 1425 1426 return 0; 1427 } 1428 1429 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, 1430 struct amdgpu_irq_src *source, 1431 struct amdgpu_iv_entry *entry) 1432 { 1433 DRM_DEBUG("IH: SDMA trap\n"); 1434 switch (entry->client_id) { 1435 case SOC15_IH_CLIENTID_SDMA0: 1436 switch (entry->ring_id) { 1437 case 0: 1438 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1439 break; 1440 case 1: 1441 /* XXX compute */ 1442 break; 1443 case 2: 1444 /* XXX compute */ 1445 break; 1446 case 3: 1447 /* XXX page queue*/ 1448 break; 1449 } 1450 break; 1451 case SOC15_IH_CLIENTID_SDMA1: 1452 switch (entry->ring_id) { 1453 case 0: 1454 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1455 break; 1456 case 1: 1457 /* XXX compute */ 1458 break; 1459 case 2: 1460 /* XXX compute */ 1461 break; 1462 case 3: 1463 /* XXX page queue*/ 1464 break; 1465 } 1466 break; 1467 case SOC15_IH_CLIENTID_SDMA2: 1468 switch (entry->ring_id) { 1469 case 0: 1470 amdgpu_fence_process(&adev->sdma.instance[2].ring); 1471 break; 1472 case 1: 1473 /* XXX compute */ 1474 break; 1475 case 2: 1476 /* XXX compute */ 1477 break; 1478 case 3: 1479 /* XXX page queue*/ 1480 break; 1481 } 1482 break; 1483 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: 1484 switch (entry->ring_id) { 1485 case 0: 1486 amdgpu_fence_process(&adev->sdma.instance[3].ring); 1487 break; 1488 case 1: 1489 /* XXX compute */ 1490 break; 1491 case 2: 1492 /* XXX compute */ 1493 break; 1494 case 3: 1495 /* XXX page queue*/ 1496 break; 1497 } 1498 break; 1499 } 1500 return 0; 1501 } 1502 1503 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1504 struct amdgpu_irq_src *source, 1505 struct amdgpu_iv_entry *entry) 1506 { 1507 return 0; 1508 } 1509 1510 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1511 bool enable) 1512 { 1513 uint32_t data, def; 1514 int i; 1515 1516 for (i = 0; i < adev->sdma.num_instances; i++) { 1517 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1518 /* Enable sdma clock gating */ 1519 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1520 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1521 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1522 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1523 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1524 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1525 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1526 if (def != data) 1527 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1528 } else { 1529 /* Disable sdma clock gating */ 1530 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1531 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1532 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1533 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1534 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1535 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1536 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1537 if (def != data) 1538 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1539 } 1540 } 1541 } 1542 1543 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1544 bool enable) 1545 { 1546 uint32_t data, def; 1547 int i; 1548 1549 for (i = 0; i < adev->sdma.num_instances; i++) { 1550 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1551 /* Enable sdma mem light sleep */ 1552 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1553 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1554 if (def != data) 1555 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1556 1557 } else { 1558 /* Disable sdma mem light sleep */ 1559 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1560 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1561 if (def != data) 1562 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1563 1564 } 1565 } 1566 } 1567 1568 static int sdma_v5_2_set_clockgating_state(void *handle, 1569 enum amd_clockgating_state state) 1570 { 1571 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1572 1573 if (amdgpu_sriov_vf(adev)) 1574 return 0; 1575 1576 switch (adev->asic_type) { 1577 case CHIP_SIENNA_CICHLID: 1578 case CHIP_NAVY_FLOUNDER: 1579 case CHIP_VANGOGH: 1580 sdma_v5_2_update_medium_grain_clock_gating(adev, 1581 state == AMD_CG_STATE_GATE ? true : false); 1582 sdma_v5_2_update_medium_grain_light_sleep(adev, 1583 state == AMD_CG_STATE_GATE ? true : false); 1584 break; 1585 default: 1586 break; 1587 } 1588 1589 return 0; 1590 } 1591 1592 static int sdma_v5_2_set_powergating_state(void *handle, 1593 enum amd_powergating_state state) 1594 { 1595 return 0; 1596 } 1597 1598 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags) 1599 { 1600 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1601 int data; 1602 1603 if (amdgpu_sriov_vf(adev)) 1604 *flags = 0; 1605 1606 /* AMD_CG_SUPPORT_SDMA_LS */ 1607 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1608 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1609 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1610 } 1611 1612 const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1613 .name = "sdma_v5_2", 1614 .early_init = sdma_v5_2_early_init, 1615 .late_init = NULL, 1616 .sw_init = sdma_v5_2_sw_init, 1617 .sw_fini = sdma_v5_2_sw_fini, 1618 .hw_init = sdma_v5_2_hw_init, 1619 .hw_fini = sdma_v5_2_hw_fini, 1620 .suspend = sdma_v5_2_suspend, 1621 .resume = sdma_v5_2_resume, 1622 .is_idle = sdma_v5_2_is_idle, 1623 .wait_for_idle = sdma_v5_2_wait_for_idle, 1624 .soft_reset = sdma_v5_2_soft_reset, 1625 .set_clockgating_state = sdma_v5_2_set_clockgating_state, 1626 .set_powergating_state = sdma_v5_2_set_powergating_state, 1627 .get_clockgating_state = sdma_v5_2_get_clockgating_state, 1628 }; 1629 1630 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 1631 .type = AMDGPU_RING_TYPE_SDMA, 1632 .align_mask = 0xf, 1633 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1634 .support_64bit_ptrs = true, 1635 .vmhub = AMDGPU_GFXHUB_0, 1636 .get_rptr = sdma_v5_2_ring_get_rptr, 1637 .get_wptr = sdma_v5_2_ring_get_wptr, 1638 .set_wptr = sdma_v5_2_ring_set_wptr, 1639 .emit_frame_size = 1640 5 + /* sdma_v5_2_ring_init_cond_exec */ 1641 6 + /* sdma_v5_2_ring_emit_hdp_flush */ 1642 3 + /* hdp_invalidate */ 1643 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ 1644 /* sdma_v5_2_ring_emit_vm_flush */ 1645 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1646 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1647 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ 1648 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ 1649 .emit_ib = sdma_v5_2_ring_emit_ib, 1650 .emit_fence = sdma_v5_2_ring_emit_fence, 1651 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, 1652 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, 1653 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, 1654 .test_ring = sdma_v5_2_ring_test_ring, 1655 .test_ib = sdma_v5_2_ring_test_ib, 1656 .insert_nop = sdma_v5_2_ring_insert_nop, 1657 .pad_ib = sdma_v5_2_ring_pad_ib, 1658 .emit_wreg = sdma_v5_2_ring_emit_wreg, 1659 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, 1660 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, 1661 .init_cond_exec = sdma_v5_2_ring_init_cond_exec, 1662 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec, 1663 .preempt_ib = sdma_v5_2_ring_preempt_ib, 1664 }; 1665 1666 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) 1667 { 1668 int i; 1669 1670 for (i = 0; i < adev->sdma.num_instances; i++) { 1671 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; 1672 adev->sdma.instance[i].ring.me = i; 1673 } 1674 } 1675 1676 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { 1677 .set = sdma_v5_2_set_trap_irq_state, 1678 .process = sdma_v5_2_process_trap_irq, 1679 }; 1680 1681 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { 1682 .process = sdma_v5_2_process_illegal_inst_irq, 1683 }; 1684 1685 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) 1686 { 1687 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1688 adev->sdma.num_instances; 1689 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; 1690 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; 1691 } 1692 1693 /** 1694 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine 1695 * 1696 * @ring: amdgpu_ring structure holding ring information 1697 * @src_offset: src GPU address 1698 * @dst_offset: dst GPU address 1699 * @byte_count: number of bytes to xfer 1700 * 1701 * Copy GPU buffers using the DMA engine. 1702 * Used by the amdgpu ttm implementation to move pages if 1703 * registered as the asic copy callback. 1704 */ 1705 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, 1706 uint64_t src_offset, 1707 uint64_t dst_offset, 1708 uint32_t byte_count, 1709 bool tmz) 1710 { 1711 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1712 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1713 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1714 ib->ptr[ib->length_dw++] = byte_count - 1; 1715 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1716 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1717 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1718 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1719 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1720 } 1721 1722 /** 1723 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine 1724 * 1725 * @ring: amdgpu_ring structure holding ring information 1726 * @src_data: value to write to buffer 1727 * @dst_offset: dst GPU address 1728 * @byte_count: number of bytes to xfer 1729 * 1730 * Fill GPU buffers using the DMA engine. 1731 */ 1732 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, 1733 uint32_t src_data, 1734 uint64_t dst_offset, 1735 uint32_t byte_count) 1736 { 1737 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1738 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1739 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1740 ib->ptr[ib->length_dw++] = src_data; 1741 ib->ptr[ib->length_dw++] = byte_count - 1; 1742 } 1743 1744 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { 1745 .copy_max_bytes = 0x400000, 1746 .copy_num_dw = 7, 1747 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, 1748 1749 .fill_max_bytes = 0x400000, 1750 .fill_num_dw = 5, 1751 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, 1752 }; 1753 1754 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) 1755 { 1756 if (adev->mman.buffer_funcs == NULL) { 1757 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 1758 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1759 } 1760 } 1761 1762 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 1763 .copy_pte_num_dw = 7, 1764 .copy_pte = sdma_v5_2_vm_copy_pte, 1765 .write_pte = sdma_v5_2_vm_write_pte, 1766 .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 1767 }; 1768 1769 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 1770 { 1771 unsigned i; 1772 1773 if (adev->vm_manager.vm_pte_funcs == NULL) { 1774 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 1775 for (i = 0; i < adev->sdma.num_instances; i++) { 1776 adev->vm_manager.vm_pte_scheds[i] = 1777 &adev->sdma.instance[i].ring.sched; 1778 } 1779 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1780 } 1781 } 1782 1783 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { 1784 .type = AMD_IP_BLOCK_TYPE_SDMA, 1785 .major = 5, 1786 .minor = 2, 1787 .rev = 0, 1788 .funcs = &sdma_v5_2_ip_funcs, 1789 }; 1790