1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_3_0_offset.h" 34 #include "gc/gc_10_3_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h" 38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h" 39 40 #include "soc15_common.h" 41 #include "soc15.h" 42 #include "navi10_sdma_pkt_open.h" 43 #include "nbio_v2_3.h" 44 #include "sdma_common.h" 45 #include "sdma_v5_2.h" 46 47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin"); 48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin"); 50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin"); 51 52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin"); 54 55 #define SDMA1_REG_OFFSET 0x600 56 #define SDMA3_REG_OFFSET 0x400 57 #define SDMA0_HYP_DEC_REG_START 0x5880 58 #define SDMA0_HYP_DEC_REG_END 0x5893 59 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 60 61 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); 62 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); 63 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); 64 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); 65 66 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 67 { 68 u32 base; 69 70 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 71 internal_offset <= SDMA0_HYP_DEC_REG_END) { 72 base = adev->reg_offset[GC_HWIP][0][1]; 73 if (instance != 0) 74 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance; 75 } else { 76 if (instance < 2) { 77 base = adev->reg_offset[GC_HWIP][0][0]; 78 if (instance == 1) 79 internal_offset += SDMA1_REG_OFFSET; 80 } else { 81 base = adev->reg_offset[GC_HWIP][0][2]; 82 if (instance == 3) 83 internal_offset += SDMA3_REG_OFFSET; 84 } 85 } 86 87 return base + internal_offset; 88 } 89 90 static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst) 91 { 92 int err = 0; 93 const struct sdma_firmware_header_v1_0 *hdr; 94 95 err = amdgpu_ucode_validate(sdma_inst->fw); 96 if (err) 97 return err; 98 99 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data; 100 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version); 101 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version); 102 103 if (sdma_inst->feature_version >= 20) 104 sdma_inst->burst_nop = true; 105 106 return 0; 107 } 108 109 static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev) 110 { 111 release_firmware(adev->sdma.instance[0].fw); 112 113 memset((void *)adev->sdma.instance, 0, 114 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES); 115 } 116 117 /** 118 * sdma_v5_2_init_microcode - load ucode images from disk 119 * 120 * @adev: amdgpu_device pointer 121 * 122 * Use the firmware interface to load the ucode images into 123 * the driver (not loaded into hw). 124 * Returns 0 on success, error on failure. 125 */ 126 127 // emulation only, won't work on real chip 128 // navi10 real chip need to use PSP to load firmware 129 static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) 130 { 131 const char *chip_name; 132 char fw_name[40]; 133 int err = 0, i; 134 struct amdgpu_firmware_info *info = NULL; 135 const struct common_firmware_header *header = NULL; 136 137 DRM_DEBUG("\n"); 138 139 switch (adev->asic_type) { 140 case CHIP_SIENNA_CICHLID: 141 chip_name = "sienna_cichlid"; 142 break; 143 case CHIP_NAVY_FLOUNDER: 144 chip_name = "navy_flounder"; 145 break; 146 case CHIP_VANGOGH: 147 chip_name = "vangogh"; 148 break; 149 case CHIP_DIMGREY_CAVEFISH: 150 chip_name = "dimgrey_cavefish"; 151 break; 152 case CHIP_BEIGE_GOBY: 153 chip_name = "beige_goby"; 154 break; 155 case CHIP_YELLOW_CARP: 156 chip_name = "yellow_carp"; 157 break; 158 default: 159 BUG(); 160 } 161 162 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 163 164 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev); 165 if (err) 166 goto out; 167 168 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]); 169 if (err) 170 goto out; 171 172 for (i = 1; i < adev->sdma.num_instances; i++) 173 memcpy((void *)&adev->sdma.instance[i], 174 (void *)&adev->sdma.instance[0], 175 sizeof(struct amdgpu_sdma_instance)); 176 177 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID)) 178 return 0; 179 180 DRM_DEBUG("psp_load == '%s'\n", 181 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 182 183 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 184 for (i = 0; i < adev->sdma.num_instances; i++) { 185 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 186 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 187 info->fw = adev->sdma.instance[i].fw; 188 header = (const struct common_firmware_header *)info->fw->data; 189 adev->firmware.fw_size += 190 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 191 } 192 } 193 194 out: 195 if (err) { 196 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name); 197 sdma_v5_2_destroy_inst_ctx(adev); 198 } 199 return err; 200 } 201 202 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring) 203 { 204 unsigned ret; 205 206 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 207 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 208 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 209 amdgpu_ring_write(ring, 1); 210 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 211 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 212 213 return ret; 214 } 215 216 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring, 217 unsigned offset) 218 { 219 unsigned cur; 220 221 BUG_ON(offset > ring->buf_mask); 222 BUG_ON(ring->ring[offset] != 0x55aa55aa); 223 224 cur = (ring->wptr - 1) & ring->buf_mask; 225 if (cur > offset) 226 ring->ring[offset] = cur - offset; 227 else 228 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 229 } 230 231 /** 232 * sdma_v5_2_ring_get_rptr - get the current read pointer 233 * 234 * @ring: amdgpu ring pointer 235 * 236 * Get the current rptr from the hardware (NAVI10+). 237 */ 238 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring) 239 { 240 u64 *rptr; 241 242 /* XXX check if swapping is necessary on BE */ 243 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 244 245 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 246 return ((*rptr) >> 2); 247 } 248 249 /** 250 * sdma_v5_2_ring_get_wptr - get the current write pointer 251 * 252 * @ring: amdgpu ring pointer 253 * 254 * Get the current wptr from the hardware (NAVI10+). 255 */ 256 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring) 257 { 258 struct amdgpu_device *adev = ring->adev; 259 u64 wptr; 260 261 if (ring->use_doorbell) { 262 /* XXX check if swapping is necessary on BE */ 263 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 264 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 265 } else { 266 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 267 wptr = wptr << 32; 268 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 269 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 270 } 271 272 return wptr >> 2; 273 } 274 275 /** 276 * sdma_v5_2_ring_set_wptr - commit the write pointer 277 * 278 * @ring: amdgpu ring pointer 279 * 280 * Write the wptr back to the hardware (NAVI10+). 281 */ 282 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) 283 { 284 struct amdgpu_device *adev = ring->adev; 285 286 DRM_DEBUG("Setting write pointer\n"); 287 if (ring->use_doorbell) { 288 DRM_DEBUG("Using doorbell -- " 289 "wptr_offs == 0x%08x " 290 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 291 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 292 ring->wptr_offs, 293 lower_32_bits(ring->wptr << 2), 294 upper_32_bits(ring->wptr << 2)); 295 /* XXX check if swapping is necessary on BE */ 296 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 297 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 298 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 299 ring->doorbell_index, ring->wptr << 2); 300 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 301 } else { 302 DRM_DEBUG("Not using doorbell -- " 303 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 304 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 305 ring->me, 306 lower_32_bits(ring->wptr << 2), 307 ring->me, 308 upper_32_bits(ring->wptr << 2)); 309 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 310 lower_32_bits(ring->wptr << 2)); 311 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 312 upper_32_bits(ring->wptr << 2)); 313 } 314 } 315 316 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 317 { 318 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 319 int i; 320 321 for (i = 0; i < count; i++) 322 if (sdma && sdma->burst_nop && (i == 0)) 323 amdgpu_ring_write(ring, ring->funcs->nop | 324 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 325 else 326 amdgpu_ring_write(ring, ring->funcs->nop); 327 } 328 329 /** 330 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine 331 * 332 * @ring: amdgpu ring pointer 333 * @job: job to retrieve vmid from 334 * @ib: IB object to schedule 335 * @flags: unused 336 * 337 * Schedule an IB in the DMA ring. 338 */ 339 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring, 340 struct amdgpu_job *job, 341 struct amdgpu_ib *ib, 342 uint32_t flags) 343 { 344 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 345 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 346 347 /* An IB packet must end on a 8 DW boundary--the next dword 348 * must be on a 8-dword boundary. Our IB packet below is 6 349 * dwords long, thus add x number of NOPs, such that, in 350 * modular arithmetic, 351 * wptr + 6 + x = 8k, k >= 0, which in C is, 352 * (wptr + 6 + x) % 8 = 0. 353 * The expression below, is a solution of x. 354 */ 355 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 356 357 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 358 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 359 /* base must be 32 byte aligned */ 360 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 361 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 362 amdgpu_ring_write(ring, ib->length_dw); 363 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 364 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 365 } 366 367 /** 368 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse 369 * 370 * @ring: amdgpu ring pointer 371 * @job: job to retrieve vmid from 372 * @ib: IB object to schedule 373 * 374 * flush the IB by graphics cache rinse. 375 */ 376 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring) 377 { 378 uint32_t gcr_cntl = 379 SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 380 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 381 SDMA_GCR_GLI_INV(1); 382 383 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 384 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 385 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 386 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 387 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 388 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 389 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 390 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 391 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 392 } 393 394 /** 395 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 396 * 397 * @ring: amdgpu ring pointer 398 * 399 * Emit an hdp flush packet on the requested DMA ring. 400 */ 401 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 402 { 403 struct amdgpu_device *adev = ring->adev; 404 u32 ref_and_mask = 0; 405 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 406 407 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; 408 409 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 410 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 411 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 412 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 413 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 414 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 415 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 416 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 417 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 418 } 419 420 /** 421 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring 422 * 423 * @ring: amdgpu ring pointer 424 * @addr: address 425 * @seq: sequence number 426 * @flags: fence related flags 427 * 428 * Add a DMA fence packet to the ring to write 429 * the fence seq number and DMA trap packet to generate 430 * an interrupt if needed. 431 */ 432 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 433 unsigned flags) 434 { 435 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 436 /* write the fence */ 437 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 438 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 439 /* zero in first two bits */ 440 BUG_ON(addr & 0x3); 441 amdgpu_ring_write(ring, lower_32_bits(addr)); 442 amdgpu_ring_write(ring, upper_32_bits(addr)); 443 amdgpu_ring_write(ring, lower_32_bits(seq)); 444 445 /* optionally write high bits as well */ 446 if (write64bit) { 447 addr += 4; 448 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 449 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 450 /* zero in first two bits */ 451 BUG_ON(addr & 0x3); 452 amdgpu_ring_write(ring, lower_32_bits(addr)); 453 amdgpu_ring_write(ring, upper_32_bits(addr)); 454 amdgpu_ring_write(ring, upper_32_bits(seq)); 455 } 456 457 if (flags & AMDGPU_FENCE_FLAG_INT) { 458 /* generate an interrupt */ 459 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 460 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 461 } 462 } 463 464 465 /** 466 * sdma_v5_2_gfx_stop - stop the gfx async dma engines 467 * 468 * @adev: amdgpu_device pointer 469 * 470 * Stop the gfx async dma ring buffers. 471 */ 472 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev) 473 { 474 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 475 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 476 struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring; 477 struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring; 478 u32 rb_cntl, ib_cntl; 479 int i; 480 481 if ((adev->mman.buffer_funcs_ring == sdma0) || 482 (adev->mman.buffer_funcs_ring == sdma1) || 483 (adev->mman.buffer_funcs_ring == sdma2) || 484 (adev->mman.buffer_funcs_ring == sdma3)) 485 amdgpu_ttm_set_buffer_funcs_status(adev, false); 486 487 for (i = 0; i < adev->sdma.num_instances; i++) { 488 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 489 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 490 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 491 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 492 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 493 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 494 } 495 } 496 497 /** 498 * sdma_v5_2_rlc_stop - stop the compute async dma engines 499 * 500 * @adev: amdgpu_device pointer 501 * 502 * Stop the compute async dma queues. 503 */ 504 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) 505 { 506 /* XXX todo */ 507 } 508 509 /** 510 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch 511 * 512 * @adev: amdgpu_device pointer 513 * @enable: enable/disable the DMA MEs context switch. 514 * 515 * Halt or unhalt the async dma engines context switch. 516 */ 517 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 518 { 519 u32 f32_cntl, phase_quantum = 0; 520 int i; 521 522 if (amdgpu_sdma_phase_quantum) { 523 unsigned value = amdgpu_sdma_phase_quantum; 524 unsigned unit = 0; 525 526 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 527 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 528 value = (value + 1) >> 1; 529 unit++; 530 } 531 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 532 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 533 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 534 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 535 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 536 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 537 WARN_ONCE(1, 538 "clamping sdma_phase_quantum to %uK clock cycles\n", 539 value << unit); 540 } 541 phase_quantum = 542 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 543 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 544 } 545 546 for (i = 0; i < adev->sdma.num_instances; i++) { 547 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 548 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 549 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 550 if (enable && amdgpu_sdma_phase_quantum) { 551 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 552 phase_quantum); 553 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 554 phase_quantum); 555 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 556 phase_quantum); 557 } 558 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 559 } 560 561 } 562 563 /** 564 * sdma_v5_2_enable - stop the async dma engines 565 * 566 * @adev: amdgpu_device pointer 567 * @enable: enable/disable the DMA MEs. 568 * 569 * Halt or unhalt the async dma engines. 570 */ 571 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) 572 { 573 u32 f32_cntl; 574 int i; 575 576 if (!enable) { 577 sdma_v5_2_gfx_stop(adev); 578 sdma_v5_2_rlc_stop(adev); 579 } 580 581 for (i = 0; i < adev->sdma.num_instances; i++) { 582 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 583 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 584 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 585 } 586 } 587 588 /** 589 * sdma_v5_2_gfx_resume - setup and start the async dma engines 590 * 591 * @adev: amdgpu_device pointer 592 * 593 * Set up the gfx DMA ring buffers and enable them. 594 * Returns 0 for success, error for failure. 595 */ 596 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) 597 { 598 struct amdgpu_ring *ring; 599 u32 rb_cntl, ib_cntl; 600 u32 rb_bufsz; 601 u32 wb_offset; 602 u32 doorbell; 603 u32 doorbell_offset; 604 u32 temp; 605 u32 wptr_poll_cntl; 606 u64 wptr_gpu_addr; 607 int i, r; 608 609 for (i = 0; i < adev->sdma.num_instances; i++) { 610 ring = &adev->sdma.instance[i].ring; 611 wb_offset = (ring->rptr_offs * 4); 612 613 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 614 615 /* Set ring buffer size in dwords */ 616 rb_bufsz = order_base_2(ring->ring_size / 4); 617 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 618 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 619 #ifdef __BIG_ENDIAN 620 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 621 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 622 RPTR_WRITEBACK_SWAP_ENABLE, 1); 623 #endif 624 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 625 626 /* Initialize the ring buffer's read and write pointers */ 627 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 628 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 629 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 630 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 631 632 /* setup the wptr shadow polling */ 633 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 634 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 635 lower_32_bits(wptr_gpu_addr)); 636 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 637 upper_32_bits(wptr_gpu_addr)); 638 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, 639 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 640 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 641 SDMA0_GFX_RB_WPTR_POLL_CNTL, 642 F32_POLL_ENABLE, 1); 643 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 644 wptr_poll_cntl); 645 646 /* set the wb address whether it's enabled or not */ 647 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 648 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 649 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 650 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 651 652 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 653 654 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 655 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 656 657 ring->wptr = 0; 658 659 /* before programing wptr to a less value, need set minor_ptr_update first */ 660 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 661 662 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 663 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 664 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 665 } 666 667 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 668 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 669 670 if (ring->use_doorbell) { 671 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 672 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 673 OFFSET, ring->doorbell_index); 674 } else { 675 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 676 } 677 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 678 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 679 680 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 681 ring->doorbell_index, 682 adev->doorbell_index.sdma_doorbell_range); 683 684 if (amdgpu_sriov_vf(adev)) 685 sdma_v5_2_ring_set_wptr(ring); 686 687 /* set minor_ptr_update to 0 after wptr programed */ 688 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 689 690 /* set utc l1 enable flag always to 1 */ 691 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); 692 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 693 694 /* enable MCBP */ 695 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 696 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 697 698 /* Set up RESP_MODE to non-copy addresses */ 699 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 700 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 701 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 702 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 703 704 /* program default cache read and write policy */ 705 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 706 /* clean read policy and write policy bits */ 707 temp &= 0xFF0FFF; 708 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | 709 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | 710 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); 711 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 712 713 if (!amdgpu_sriov_vf(adev)) { 714 /* unhalt engine */ 715 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 716 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 717 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 718 } 719 720 /* enable DMA RB */ 721 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 722 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 723 724 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 725 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 726 #ifdef __BIG_ENDIAN 727 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 728 #endif 729 /* enable DMA IBs */ 730 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 731 732 ring->sched.ready = true; 733 734 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 735 sdma_v5_2_ctx_switch_enable(adev, true); 736 sdma_v5_2_enable(adev, true); 737 } 738 739 r = amdgpu_ring_test_ring(ring); 740 if (r) { 741 ring->sched.ready = false; 742 return r; 743 } 744 745 if (adev->mman.buffer_funcs_ring == ring) 746 amdgpu_ttm_set_buffer_funcs_status(adev, true); 747 } 748 749 return 0; 750 } 751 752 /** 753 * sdma_v5_2_rlc_resume - setup and start the async dma engines 754 * 755 * @adev: amdgpu_device pointer 756 * 757 * Set up the compute DMA queues and enable them. 758 * Returns 0 for success, error for failure. 759 */ 760 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) 761 { 762 return 0; 763 } 764 765 /** 766 * sdma_v5_2_load_microcode - load the sDMA ME ucode 767 * 768 * @adev: amdgpu_device pointer 769 * 770 * Loads the sDMA0/1/2/3 ucode. 771 * Returns 0 for success, -EINVAL if the ucode is not available. 772 */ 773 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) 774 { 775 const struct sdma_firmware_header_v1_0 *hdr; 776 const __le32 *fw_data; 777 u32 fw_size; 778 int i, j; 779 780 /* halt the MEs */ 781 sdma_v5_2_enable(adev, false); 782 783 for (i = 0; i < adev->sdma.num_instances; i++) { 784 if (!adev->sdma.instance[i].fw) 785 return -EINVAL; 786 787 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 788 amdgpu_ucode_print_sdma_hdr(&hdr->header); 789 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 790 791 fw_data = (const __le32 *) 792 (adev->sdma.instance[i].fw->data + 793 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 794 795 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 796 797 for (j = 0; j < fw_size; j++) { 798 if (amdgpu_emu_mode == 1 && j % 500 == 0) 799 msleep(1); 800 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 801 } 802 803 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 804 } 805 806 return 0; 807 } 808 809 static int sdma_v5_2_soft_reset(void *handle) 810 { 811 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 812 u32 grbm_soft_reset; 813 u32 tmp; 814 int i; 815 816 for (i = 0; i < adev->sdma.num_instances; i++) { 817 grbm_soft_reset = REG_SET_FIELD(0, 818 GRBM_SOFT_RESET, SOFT_RESET_SDMA0, 819 1); 820 grbm_soft_reset <<= i; 821 822 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 823 tmp |= grbm_soft_reset; 824 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp); 825 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 826 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 827 828 udelay(50); 829 830 tmp &= ~grbm_soft_reset; 831 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 832 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 833 834 udelay(50); 835 } 836 837 return 0; 838 } 839 840 /** 841 * sdma_v5_2_start - setup and start the async dma engines 842 * 843 * @adev: amdgpu_device pointer 844 * 845 * Set up the DMA engines and enable them. 846 * Returns 0 for success, error for failure. 847 */ 848 static int sdma_v5_2_start(struct amdgpu_device *adev) 849 { 850 int r = 0; 851 852 if (amdgpu_sriov_vf(adev)) { 853 sdma_v5_2_ctx_switch_enable(adev, false); 854 sdma_v5_2_enable(adev, false); 855 856 /* set RB registers */ 857 r = sdma_v5_2_gfx_resume(adev); 858 return r; 859 } 860 861 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 862 r = sdma_v5_2_load_microcode(adev); 863 if (r) 864 return r; 865 866 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 867 if (amdgpu_emu_mode == 1) 868 msleep(1000); 869 } 870 871 sdma_v5_2_soft_reset(adev); 872 /* unhalt the MEs */ 873 sdma_v5_2_enable(adev, true); 874 /* enable sdma ring preemption */ 875 sdma_v5_2_ctx_switch_enable(adev, true); 876 877 /* start the gfx rings and rlc compute queues */ 878 r = sdma_v5_2_gfx_resume(adev); 879 if (r) 880 return r; 881 r = sdma_v5_2_rlc_resume(adev); 882 883 return r; 884 } 885 886 /** 887 * sdma_v5_2_ring_test_ring - simple async dma engine test 888 * 889 * @ring: amdgpu_ring structure holding ring information 890 * 891 * Test the DMA engine by writing using it to write an 892 * value to memory. 893 * Returns 0 for success, error for failure. 894 */ 895 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) 896 { 897 struct amdgpu_device *adev = ring->adev; 898 unsigned i; 899 unsigned index; 900 int r; 901 u32 tmp; 902 u64 gpu_addr; 903 904 r = amdgpu_device_wb_get(adev, &index); 905 if (r) { 906 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 907 return r; 908 } 909 910 gpu_addr = adev->wb.gpu_addr + (index * 4); 911 tmp = 0xCAFEDEAD; 912 adev->wb.wb[index] = cpu_to_le32(tmp); 913 914 r = amdgpu_ring_alloc(ring, 5); 915 if (r) { 916 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 917 amdgpu_device_wb_free(adev, index); 918 return r; 919 } 920 921 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 922 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 923 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 924 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 925 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 926 amdgpu_ring_write(ring, 0xDEADBEEF); 927 amdgpu_ring_commit(ring); 928 929 for (i = 0; i < adev->usec_timeout; i++) { 930 tmp = le32_to_cpu(adev->wb.wb[index]); 931 if (tmp == 0xDEADBEEF) 932 break; 933 if (amdgpu_emu_mode == 1) 934 msleep(1); 935 else 936 udelay(1); 937 } 938 939 if (i >= adev->usec_timeout) 940 r = -ETIMEDOUT; 941 942 amdgpu_device_wb_free(adev, index); 943 944 return r; 945 } 946 947 /** 948 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine 949 * 950 * @ring: amdgpu_ring structure holding ring information 951 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 952 * 953 * Test a simple IB in the DMA ring. 954 * Returns 0 on success, error on failure. 955 */ 956 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) 957 { 958 struct amdgpu_device *adev = ring->adev; 959 struct amdgpu_ib ib; 960 struct dma_fence *f = NULL; 961 unsigned index; 962 long r; 963 u32 tmp = 0; 964 u64 gpu_addr; 965 966 r = amdgpu_device_wb_get(adev, &index); 967 if (r) { 968 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 969 return r; 970 } 971 972 gpu_addr = adev->wb.gpu_addr + (index * 4); 973 tmp = 0xCAFEDEAD; 974 adev->wb.wb[index] = cpu_to_le32(tmp); 975 memset(&ib, 0, sizeof(ib)); 976 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); 977 if (r) { 978 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 979 goto err0; 980 } 981 982 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 983 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 984 ib.ptr[1] = lower_32_bits(gpu_addr); 985 ib.ptr[2] = upper_32_bits(gpu_addr); 986 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 987 ib.ptr[4] = 0xDEADBEEF; 988 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 989 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 990 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 991 ib.length_dw = 8; 992 993 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 994 if (r) 995 goto err1; 996 997 r = dma_fence_wait_timeout(f, false, timeout); 998 if (r == 0) { 999 DRM_ERROR("amdgpu: IB test timed out\n"); 1000 r = -ETIMEDOUT; 1001 goto err1; 1002 } else if (r < 0) { 1003 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1004 goto err1; 1005 } 1006 tmp = le32_to_cpu(adev->wb.wb[index]); 1007 if (tmp == 0xDEADBEEF) 1008 r = 0; 1009 else 1010 r = -EINVAL; 1011 1012 err1: 1013 amdgpu_ib_free(adev, &ib, NULL); 1014 dma_fence_put(f); 1015 err0: 1016 amdgpu_device_wb_free(adev, index); 1017 return r; 1018 } 1019 1020 1021 /** 1022 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART 1023 * 1024 * @ib: indirect buffer to fill with commands 1025 * @pe: addr of the page entry 1026 * @src: src addr to copy from 1027 * @count: number of page entries to update 1028 * 1029 * Update PTEs by copying them from the GART using sDMA. 1030 */ 1031 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib, 1032 uint64_t pe, uint64_t src, 1033 unsigned count) 1034 { 1035 unsigned bytes = count * 8; 1036 1037 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1038 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1039 ib->ptr[ib->length_dw++] = bytes - 1; 1040 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1041 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1042 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1043 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1044 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1045 1046 } 1047 1048 /** 1049 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually 1050 * 1051 * @ib: indirect buffer to fill with commands 1052 * @pe: addr of the page entry 1053 * @value: dst addr to write into pe 1054 * @count: number of page entries to update 1055 * @incr: increase next addr by incr bytes 1056 * 1057 * Update PTEs by writing them manually using sDMA. 1058 */ 1059 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1060 uint64_t value, unsigned count, 1061 uint32_t incr) 1062 { 1063 unsigned ndw = count * 2; 1064 1065 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1066 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1067 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1068 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1069 ib->ptr[ib->length_dw++] = ndw - 1; 1070 for (; ndw > 0; ndw -= 2) { 1071 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1072 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1073 value += incr; 1074 } 1075 } 1076 1077 /** 1078 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA 1079 * 1080 * @ib: indirect buffer to fill with commands 1081 * @pe: addr of the page entry 1082 * @addr: dst addr to write into pe 1083 * @count: number of page entries to update 1084 * @incr: increase next addr by incr bytes 1085 * @flags: access flags 1086 * 1087 * Update the page tables using sDMA. 1088 */ 1089 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib, 1090 uint64_t pe, 1091 uint64_t addr, unsigned count, 1092 uint32_t incr, uint64_t flags) 1093 { 1094 /* for physically contiguous pages (vram) */ 1095 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1096 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1097 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1098 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1099 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1100 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1101 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1102 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1103 ib->ptr[ib->length_dw++] = 0; 1104 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1105 } 1106 1107 /** 1108 * sdma_v5_2_ring_pad_ib - pad the IB 1109 * 1110 * @ib: indirect buffer to fill with padding 1111 * @ring: amdgpu_ring structure holding ring information 1112 * 1113 * Pad the IB with NOPs to a boundary multiple of 8. 1114 */ 1115 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1116 { 1117 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1118 u32 pad_count; 1119 int i; 1120 1121 pad_count = (-ib->length_dw) & 0x7; 1122 for (i = 0; i < pad_count; i++) 1123 if (sdma && sdma->burst_nop && (i == 0)) 1124 ib->ptr[ib->length_dw++] = 1125 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1126 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1127 else 1128 ib->ptr[ib->length_dw++] = 1129 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1130 } 1131 1132 1133 /** 1134 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline 1135 * 1136 * @ring: amdgpu_ring pointer 1137 * 1138 * Make sure all previous operations are completed (CIK). 1139 */ 1140 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1141 { 1142 uint32_t seq = ring->fence_drv.sync_seq; 1143 uint64_t addr = ring->fence_drv.gpu_addr; 1144 1145 /* wait for idle */ 1146 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1147 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1148 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1149 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1150 amdgpu_ring_write(ring, addr & 0xfffffffc); 1151 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1152 amdgpu_ring_write(ring, seq); /* reference */ 1153 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1154 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1155 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1156 } 1157 1158 1159 /** 1160 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA 1161 * 1162 * @ring: amdgpu_ring pointer 1163 * @vmid: vmid number to use 1164 * @pd_addr: address 1165 * 1166 * Update the page table base and flush the VM TLB 1167 * using sDMA. 1168 */ 1169 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, 1170 unsigned vmid, uint64_t pd_addr) 1171 { 1172 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1173 } 1174 1175 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, 1176 uint32_t reg, uint32_t val) 1177 { 1178 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1179 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1180 amdgpu_ring_write(ring, reg); 1181 amdgpu_ring_write(ring, val); 1182 } 1183 1184 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1185 uint32_t val, uint32_t mask) 1186 { 1187 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1188 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1189 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1190 amdgpu_ring_write(ring, reg << 2); 1191 amdgpu_ring_write(ring, 0); 1192 amdgpu_ring_write(ring, val); /* reference */ 1193 amdgpu_ring_write(ring, mask); /* mask */ 1194 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1195 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1196 } 1197 1198 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1199 uint32_t reg0, uint32_t reg1, 1200 uint32_t ref, uint32_t mask) 1201 { 1202 amdgpu_ring_emit_wreg(ring, reg0, ref); 1203 /* wait for a cycle to reset vm_inv_eng*_ack */ 1204 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1205 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1206 } 1207 1208 static int sdma_v5_2_early_init(void *handle) 1209 { 1210 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1211 1212 switch (adev->asic_type) { 1213 case CHIP_SIENNA_CICHLID: 1214 adev->sdma.num_instances = 4; 1215 break; 1216 case CHIP_NAVY_FLOUNDER: 1217 case CHIP_DIMGREY_CAVEFISH: 1218 adev->sdma.num_instances = 2; 1219 break; 1220 case CHIP_VANGOGH: 1221 case CHIP_BEIGE_GOBY: 1222 case CHIP_YELLOW_CARP: 1223 adev->sdma.num_instances = 1; 1224 break; 1225 default: 1226 break; 1227 } 1228 1229 sdma_v5_2_set_ring_funcs(adev); 1230 sdma_v5_2_set_buffer_funcs(adev); 1231 sdma_v5_2_set_vm_pte_funcs(adev); 1232 sdma_v5_2_set_irq_funcs(adev); 1233 1234 return 0; 1235 } 1236 1237 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num) 1238 { 1239 switch (seq_num) { 1240 case 0: 1241 return SOC15_IH_CLIENTID_SDMA0; 1242 case 1: 1243 return SOC15_IH_CLIENTID_SDMA1; 1244 case 2: 1245 return SOC15_IH_CLIENTID_SDMA2; 1246 case 3: 1247 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid; 1248 default: 1249 break; 1250 } 1251 return -EINVAL; 1252 } 1253 1254 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) 1255 { 1256 switch (seq_num) { 1257 case 0: 1258 return SDMA0_5_0__SRCID__SDMA_TRAP; 1259 case 1: 1260 return SDMA1_5_0__SRCID__SDMA_TRAP; 1261 case 2: 1262 return SDMA2_5_0__SRCID__SDMA_TRAP; 1263 case 3: 1264 return SDMA3_5_0__SRCID__SDMA_TRAP; 1265 default: 1266 break; 1267 } 1268 return -EINVAL; 1269 } 1270 1271 static int sdma_v5_2_sw_init(void *handle) 1272 { 1273 struct amdgpu_ring *ring; 1274 int r, i; 1275 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1276 1277 /* SDMA trap event */ 1278 for (i = 0; i < adev->sdma.num_instances; i++) { 1279 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i), 1280 sdma_v5_2_seq_to_trap_id(i), 1281 &adev->sdma.trap_irq); 1282 if (r) 1283 return r; 1284 } 1285 1286 r = sdma_v5_2_init_microcode(adev); 1287 if (r) { 1288 DRM_ERROR("Failed to load sdma firmware!\n"); 1289 return r; 1290 } 1291 1292 for (i = 0; i < adev->sdma.num_instances; i++) { 1293 ring = &adev->sdma.instance[i].ring; 1294 ring->ring_obj = NULL; 1295 ring->use_doorbell = true; 1296 ring->me = i; 1297 1298 DRM_INFO("use_doorbell being set to: [%s]\n", 1299 ring->use_doorbell?"true":"false"); 1300 1301 ring->doorbell_index = 1302 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset 1303 1304 sprintf(ring->name, "sdma%d", i); 1305 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1306 AMDGPU_SDMA_IRQ_INSTANCE0 + i, 1307 AMDGPU_RING_PRIO_DEFAULT, NULL); 1308 if (r) 1309 return r; 1310 } 1311 1312 return r; 1313 } 1314 1315 static int sdma_v5_2_sw_fini(void *handle) 1316 { 1317 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1318 int i; 1319 1320 for (i = 0; i < adev->sdma.num_instances; i++) 1321 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1322 1323 sdma_v5_2_destroy_inst_ctx(adev); 1324 1325 return 0; 1326 } 1327 1328 static int sdma_v5_2_hw_init(void *handle) 1329 { 1330 int r; 1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1332 1333 r = sdma_v5_2_start(adev); 1334 1335 return r; 1336 } 1337 1338 static int sdma_v5_2_hw_fini(void *handle) 1339 { 1340 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1341 1342 if (amdgpu_sriov_vf(adev)) 1343 return 0; 1344 1345 sdma_v5_2_ctx_switch_enable(adev, false); 1346 sdma_v5_2_enable(adev, false); 1347 1348 return 0; 1349 } 1350 1351 static int sdma_v5_2_suspend(void *handle) 1352 { 1353 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1354 1355 return sdma_v5_2_hw_fini(adev); 1356 } 1357 1358 static int sdma_v5_2_resume(void *handle) 1359 { 1360 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1361 1362 return sdma_v5_2_hw_init(adev); 1363 } 1364 1365 static bool sdma_v5_2_is_idle(void *handle) 1366 { 1367 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1368 u32 i; 1369 1370 for (i = 0; i < adev->sdma.num_instances; i++) { 1371 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1372 1373 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1374 return false; 1375 } 1376 1377 return true; 1378 } 1379 1380 static int sdma_v5_2_wait_for_idle(void *handle) 1381 { 1382 unsigned i; 1383 u32 sdma0, sdma1, sdma2, sdma3; 1384 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1385 1386 for (i = 0; i < adev->usec_timeout; i++) { 1387 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1388 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1389 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); 1390 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); 1391 1392 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK) 1393 return 0; 1394 udelay(1); 1395 } 1396 return -ETIMEDOUT; 1397 } 1398 1399 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) 1400 { 1401 int i, r = 0; 1402 struct amdgpu_device *adev = ring->adev; 1403 u32 index = 0; 1404 u64 sdma_gfx_preempt; 1405 1406 amdgpu_sdma_get_index_from_ring(ring, &index); 1407 sdma_gfx_preempt = 1408 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT); 1409 1410 /* assert preemption condition */ 1411 amdgpu_ring_set_preempt_cond_exec(ring, false); 1412 1413 /* emit the trailing fence */ 1414 ring->trail_seq += 1; 1415 amdgpu_ring_alloc(ring, 10); 1416 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1417 ring->trail_seq, 0); 1418 amdgpu_ring_commit(ring); 1419 1420 /* assert IB preemption */ 1421 WREG32(sdma_gfx_preempt, 1); 1422 1423 /* poll the trailing fence */ 1424 for (i = 0; i < adev->usec_timeout; i++) { 1425 if (ring->trail_seq == 1426 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1427 break; 1428 udelay(1); 1429 } 1430 1431 if (i >= adev->usec_timeout) { 1432 r = -EINVAL; 1433 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1434 } 1435 1436 /* deassert IB preemption */ 1437 WREG32(sdma_gfx_preempt, 0); 1438 1439 /* deassert the preemption condition */ 1440 amdgpu_ring_set_preempt_cond_exec(ring, true); 1441 return r; 1442 } 1443 1444 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev, 1445 struct amdgpu_irq_src *source, 1446 unsigned type, 1447 enum amdgpu_interrupt_state state) 1448 { 1449 u32 sdma_cntl; 1450 1451 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); 1452 1453 sdma_cntl = RREG32(reg_offset); 1454 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1455 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1456 WREG32(reg_offset, sdma_cntl); 1457 1458 return 0; 1459 } 1460 1461 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, 1462 struct amdgpu_irq_src *source, 1463 struct amdgpu_iv_entry *entry) 1464 { 1465 DRM_DEBUG("IH: SDMA trap\n"); 1466 switch (entry->client_id) { 1467 case SOC15_IH_CLIENTID_SDMA0: 1468 switch (entry->ring_id) { 1469 case 0: 1470 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1471 break; 1472 case 1: 1473 /* XXX compute */ 1474 break; 1475 case 2: 1476 /* XXX compute */ 1477 break; 1478 case 3: 1479 /* XXX page queue*/ 1480 break; 1481 } 1482 break; 1483 case SOC15_IH_CLIENTID_SDMA1: 1484 switch (entry->ring_id) { 1485 case 0: 1486 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1487 break; 1488 case 1: 1489 /* XXX compute */ 1490 break; 1491 case 2: 1492 /* XXX compute */ 1493 break; 1494 case 3: 1495 /* XXX page queue*/ 1496 break; 1497 } 1498 break; 1499 case SOC15_IH_CLIENTID_SDMA2: 1500 switch (entry->ring_id) { 1501 case 0: 1502 amdgpu_fence_process(&adev->sdma.instance[2].ring); 1503 break; 1504 case 1: 1505 /* XXX compute */ 1506 break; 1507 case 2: 1508 /* XXX compute */ 1509 break; 1510 case 3: 1511 /* XXX page queue*/ 1512 break; 1513 } 1514 break; 1515 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid: 1516 switch (entry->ring_id) { 1517 case 0: 1518 amdgpu_fence_process(&adev->sdma.instance[3].ring); 1519 break; 1520 case 1: 1521 /* XXX compute */ 1522 break; 1523 case 2: 1524 /* XXX compute */ 1525 break; 1526 case 3: 1527 /* XXX page queue*/ 1528 break; 1529 } 1530 break; 1531 } 1532 return 0; 1533 } 1534 1535 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev, 1536 struct amdgpu_irq_src *source, 1537 struct amdgpu_iv_entry *entry) 1538 { 1539 return 0; 1540 } 1541 1542 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1543 bool enable) 1544 { 1545 uint32_t data, def; 1546 int i; 1547 1548 for (i = 0; i < adev->sdma.num_instances; i++) { 1549 1550 if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH) 1551 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG; 1552 1553 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1554 /* Enable sdma clock gating */ 1555 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1556 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1557 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1558 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1559 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1560 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1561 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1562 if (def != data) 1563 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1564 } else { 1565 /* Disable sdma clock gating */ 1566 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1567 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1568 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1569 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1570 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1571 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK | 1572 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK); 1573 if (def != data) 1574 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1575 } 1576 } 1577 } 1578 1579 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1580 bool enable) 1581 { 1582 uint32_t data, def; 1583 int i; 1584 1585 for (i = 0; i < adev->sdma.num_instances; i++) { 1586 1587 if (adev->sdma.instance[i].fw_version < 70 && adev->asic_type == CHIP_VANGOGH) 1588 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS; 1589 1590 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1591 /* Enable sdma mem light sleep */ 1592 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1593 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1594 if (def != data) 1595 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1596 1597 } else { 1598 /* Disable sdma mem light sleep */ 1599 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1600 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1601 if (def != data) 1602 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1603 1604 } 1605 } 1606 } 1607 1608 static int sdma_v5_2_set_clockgating_state(void *handle, 1609 enum amd_clockgating_state state) 1610 { 1611 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1612 1613 if (amdgpu_sriov_vf(adev)) 1614 return 0; 1615 1616 switch (adev->asic_type) { 1617 case CHIP_SIENNA_CICHLID: 1618 case CHIP_NAVY_FLOUNDER: 1619 case CHIP_VANGOGH: 1620 case CHIP_DIMGREY_CAVEFISH: 1621 case CHIP_BEIGE_GOBY: 1622 case CHIP_YELLOW_CARP: 1623 sdma_v5_2_update_medium_grain_clock_gating(adev, 1624 state == AMD_CG_STATE_GATE); 1625 sdma_v5_2_update_medium_grain_light_sleep(adev, 1626 state == AMD_CG_STATE_GATE); 1627 break; 1628 default: 1629 break; 1630 } 1631 1632 return 0; 1633 } 1634 1635 static int sdma_v5_2_set_powergating_state(void *handle, 1636 enum amd_powergating_state state) 1637 { 1638 return 0; 1639 } 1640 1641 static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags) 1642 { 1643 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1644 int data; 1645 1646 if (amdgpu_sriov_vf(adev)) 1647 *flags = 0; 1648 1649 /* AMD_CG_SUPPORT_SDMA_LS */ 1650 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1651 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1652 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1653 } 1654 1655 const struct amd_ip_funcs sdma_v5_2_ip_funcs = { 1656 .name = "sdma_v5_2", 1657 .early_init = sdma_v5_2_early_init, 1658 .late_init = NULL, 1659 .sw_init = sdma_v5_2_sw_init, 1660 .sw_fini = sdma_v5_2_sw_fini, 1661 .hw_init = sdma_v5_2_hw_init, 1662 .hw_fini = sdma_v5_2_hw_fini, 1663 .suspend = sdma_v5_2_suspend, 1664 .resume = sdma_v5_2_resume, 1665 .is_idle = sdma_v5_2_is_idle, 1666 .wait_for_idle = sdma_v5_2_wait_for_idle, 1667 .soft_reset = sdma_v5_2_soft_reset, 1668 .set_clockgating_state = sdma_v5_2_set_clockgating_state, 1669 .set_powergating_state = sdma_v5_2_set_powergating_state, 1670 .get_clockgating_state = sdma_v5_2_get_clockgating_state, 1671 }; 1672 1673 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { 1674 .type = AMDGPU_RING_TYPE_SDMA, 1675 .align_mask = 0xf, 1676 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1677 .support_64bit_ptrs = true, 1678 .vmhub = AMDGPU_GFXHUB_0, 1679 .get_rptr = sdma_v5_2_ring_get_rptr, 1680 .get_wptr = sdma_v5_2_ring_get_wptr, 1681 .set_wptr = sdma_v5_2_ring_set_wptr, 1682 .emit_frame_size = 1683 5 + /* sdma_v5_2_ring_init_cond_exec */ 1684 6 + /* sdma_v5_2_ring_emit_hdp_flush */ 1685 3 + /* hdp_invalidate */ 1686 6 + /* sdma_v5_2_ring_emit_pipeline_sync */ 1687 /* sdma_v5_2_ring_emit_vm_flush */ 1688 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1689 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1690 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */ 1691 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */ 1692 .emit_ib = sdma_v5_2_ring_emit_ib, 1693 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync, 1694 .emit_fence = sdma_v5_2_ring_emit_fence, 1695 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync, 1696 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush, 1697 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush, 1698 .test_ring = sdma_v5_2_ring_test_ring, 1699 .test_ib = sdma_v5_2_ring_test_ib, 1700 .insert_nop = sdma_v5_2_ring_insert_nop, 1701 .pad_ib = sdma_v5_2_ring_pad_ib, 1702 .emit_wreg = sdma_v5_2_ring_emit_wreg, 1703 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait, 1704 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, 1705 .init_cond_exec = sdma_v5_2_ring_init_cond_exec, 1706 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec, 1707 .preempt_ib = sdma_v5_2_ring_preempt_ib, 1708 }; 1709 1710 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) 1711 { 1712 int i; 1713 1714 for (i = 0; i < adev->sdma.num_instances; i++) { 1715 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs; 1716 adev->sdma.instance[i].ring.me = i; 1717 } 1718 } 1719 1720 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = { 1721 .set = sdma_v5_2_set_trap_irq_state, 1722 .process = sdma_v5_2_process_trap_irq, 1723 }; 1724 1725 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = { 1726 .process = sdma_v5_2_process_illegal_inst_irq, 1727 }; 1728 1729 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev) 1730 { 1731 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1732 adev->sdma.num_instances; 1733 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs; 1734 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs; 1735 } 1736 1737 /** 1738 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine 1739 * 1740 * @ib: indirect buffer to copy to 1741 * @src_offset: src GPU address 1742 * @dst_offset: dst GPU address 1743 * @byte_count: number of bytes to xfer 1744 * @tmz: if a secure copy should be used 1745 * 1746 * Copy GPU buffers using the DMA engine. 1747 * Used by the amdgpu ttm implementation to move pages if 1748 * registered as the asic copy callback. 1749 */ 1750 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib, 1751 uint64_t src_offset, 1752 uint64_t dst_offset, 1753 uint32_t byte_count, 1754 bool tmz) 1755 { 1756 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1757 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1758 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1759 ib->ptr[ib->length_dw++] = byte_count - 1; 1760 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1761 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1762 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1763 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1764 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1765 } 1766 1767 /** 1768 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine 1769 * 1770 * @ib: indirect buffer to fill 1771 * @src_data: value to write to buffer 1772 * @dst_offset: dst GPU address 1773 * @byte_count: number of bytes to xfer 1774 * 1775 * Fill GPU buffers using the DMA engine. 1776 */ 1777 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, 1778 uint32_t src_data, 1779 uint64_t dst_offset, 1780 uint32_t byte_count) 1781 { 1782 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1783 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1784 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1785 ib->ptr[ib->length_dw++] = src_data; 1786 ib->ptr[ib->length_dw++] = byte_count - 1; 1787 } 1788 1789 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { 1790 .copy_max_bytes = 0x400000, 1791 .copy_num_dw = 7, 1792 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, 1793 1794 .fill_max_bytes = 0x400000, 1795 .fill_num_dw = 5, 1796 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, 1797 }; 1798 1799 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) 1800 { 1801 if (adev->mman.buffer_funcs == NULL) { 1802 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs; 1803 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1804 } 1805 } 1806 1807 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { 1808 .copy_pte_num_dw = 7, 1809 .copy_pte = sdma_v5_2_vm_copy_pte, 1810 .write_pte = sdma_v5_2_vm_write_pte, 1811 .set_pte_pde = sdma_v5_2_vm_set_pte_pde, 1812 }; 1813 1814 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) 1815 { 1816 unsigned i; 1817 1818 if (adev->vm_manager.vm_pte_funcs == NULL) { 1819 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; 1820 for (i = 0; i < adev->sdma.num_instances; i++) { 1821 adev->vm_manager.vm_pte_scheds[i] = 1822 &adev->sdma.instance[i].ring.sched; 1823 } 1824 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1825 } 1826 } 1827 1828 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { 1829 .type = AMD_IP_BLOCK_TYPE_SDMA, 1830 .major = 5, 1831 .minor = 2, 1832 .rev = 0, 1833 .funcs = &sdma_v5_2_ip_funcs, 1834 }; 1835