1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "gc/gc_10_1_0_offset.h" 31 #include "gc/gc_10_1_0_sh_mask.h" 32 #include "hdp/hdp_5_0_0_offset.h" 33 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 34 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 35 36 #include "soc15_common.h" 37 #include "soc15.h" 38 #include "navi10_sdma_pkt_open.h" 39 #include "nbio_v2_3.h" 40 #include "sdma_v5_0.h" 41 42 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); 43 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); 44 45 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); 46 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); 47 48 #define SDMA1_REG_OFFSET 0x600 49 #define SDMA0_HYP_DEC_REG_START 0x5880 50 #define SDMA0_HYP_DEC_REG_END 0x5893 51 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 52 53 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); 54 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); 55 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); 56 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); 57 58 static const struct soc15_reg_golden golden_settings_sdma_5[] = { 59 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 60 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 61 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 62 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 63 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 64 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 65 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00), 71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00) 83 }; 84 85 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { 86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 88 }; 89 90 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = { 91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 93 }; 94 95 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 96 { 97 u32 base; 98 99 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 100 internal_offset <= SDMA0_HYP_DEC_REG_END) { 101 base = adev->reg_offset[GC_HWIP][0][1]; 102 if (instance == 1) 103 internal_offset += SDMA1_HYP_DEC_REG_OFFSET; 104 } else { 105 base = adev->reg_offset[GC_HWIP][0][0]; 106 if (instance == 1) 107 internal_offset += SDMA1_REG_OFFSET; 108 } 109 110 return base + internal_offset; 111 } 112 113 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) 114 { 115 switch (adev->asic_type) { 116 case CHIP_NAVI10: 117 soc15_program_register_sequence(adev, 118 golden_settings_sdma_5, 119 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 120 soc15_program_register_sequence(adev, 121 golden_settings_sdma_nv10, 122 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); 123 break; 124 case CHIP_NAVI14: 125 soc15_program_register_sequence(adev, 126 golden_settings_sdma_5, 127 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 128 soc15_program_register_sequence(adev, 129 golden_settings_sdma_nv14, 130 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14)); 131 break; 132 default: 133 break; 134 } 135 } 136 137 /** 138 * sdma_v5_0_init_microcode - load ucode images from disk 139 * 140 * @adev: amdgpu_device pointer 141 * 142 * Use the firmware interface to load the ucode images into 143 * the driver (not loaded into hw). 144 * Returns 0 on success, error on failure. 145 */ 146 147 // emulation only, won't work on real chip 148 // navi10 real chip need to use PSP to load firmware 149 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) 150 { 151 const char *chip_name; 152 char fw_name[30]; 153 int err = 0, i; 154 struct amdgpu_firmware_info *info = NULL; 155 const struct common_firmware_header *header = NULL; 156 const struct sdma_firmware_header_v1_0 *hdr; 157 158 DRM_DEBUG("\n"); 159 160 switch (adev->asic_type) { 161 case CHIP_NAVI10: 162 chip_name = "navi10"; 163 break; 164 case CHIP_NAVI14: 165 chip_name = "navi14"; 166 break; 167 default: 168 BUG(); 169 } 170 171 for (i = 0; i < adev->sdma.num_instances; i++) { 172 if (i == 0) 173 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 174 else 175 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 176 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 177 if (err) 178 goto out; 179 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 180 if (err) 181 goto out; 182 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 183 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 184 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 185 if (adev->sdma.instance[i].feature_version >= 20) 186 adev->sdma.instance[i].burst_nop = true; 187 DRM_DEBUG("psp_load == '%s'\n", 188 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 189 190 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 191 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 192 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 193 info->fw = adev->sdma.instance[i].fw; 194 header = (const struct common_firmware_header *)info->fw->data; 195 adev->firmware.fw_size += 196 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 197 } 198 } 199 out: 200 if (err) { 201 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name); 202 for (i = 0; i < adev->sdma.num_instances; i++) { 203 release_firmware(adev->sdma.instance[i].fw); 204 adev->sdma.instance[i].fw = NULL; 205 } 206 } 207 return err; 208 } 209 210 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring) 211 { 212 unsigned ret; 213 214 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 215 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 216 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 217 amdgpu_ring_write(ring, 1); 218 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 219 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 220 221 return ret; 222 } 223 224 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 225 unsigned offset) 226 { 227 unsigned cur; 228 229 BUG_ON(offset > ring->buf_mask); 230 BUG_ON(ring->ring[offset] != 0x55aa55aa); 231 232 cur = (ring->wptr - 1) & ring->buf_mask; 233 if (cur > offset) 234 ring->ring[offset] = cur - offset; 235 else 236 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 237 } 238 239 /** 240 * sdma_v5_0_ring_get_rptr - get the current read pointer 241 * 242 * @ring: amdgpu ring pointer 243 * 244 * Get the current rptr from the hardware (NAVI10+). 245 */ 246 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 247 { 248 u64 *rptr; 249 250 /* XXX check if swapping is necessary on BE */ 251 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 252 253 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 254 return ((*rptr) >> 2); 255 } 256 257 /** 258 * sdma_v5_0_ring_get_wptr - get the current write pointer 259 * 260 * @ring: amdgpu ring pointer 261 * 262 * Get the current wptr from the hardware (NAVI10+). 263 */ 264 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 265 { 266 struct amdgpu_device *adev = ring->adev; 267 u64 *wptr = NULL; 268 uint64_t local_wptr = 0; 269 270 if (ring->use_doorbell) { 271 /* XXX check if swapping is necessary on BE */ 272 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); 273 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); 274 *wptr = (*wptr) >> 2; 275 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); 276 } else { 277 u32 lowbit, highbit; 278 279 wptr = &local_wptr; 280 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2; 281 highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 282 283 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 284 ring->me, highbit, lowbit); 285 *wptr = highbit; 286 *wptr = (*wptr) << 32; 287 *wptr |= lowbit; 288 } 289 290 return *wptr; 291 } 292 293 /** 294 * sdma_v5_0_ring_set_wptr - commit the write pointer 295 * 296 * @ring: amdgpu ring pointer 297 * 298 * Write the wptr back to the hardware (NAVI10+). 299 */ 300 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 301 { 302 struct amdgpu_device *adev = ring->adev; 303 304 DRM_DEBUG("Setting write pointer\n"); 305 if (ring->use_doorbell) { 306 DRM_DEBUG("Using doorbell -- " 307 "wptr_offs == 0x%08x " 308 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 309 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 310 ring->wptr_offs, 311 lower_32_bits(ring->wptr << 2), 312 upper_32_bits(ring->wptr << 2)); 313 /* XXX check if swapping is necessary on BE */ 314 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 315 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 316 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 317 ring->doorbell_index, ring->wptr << 2); 318 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 319 } else { 320 DRM_DEBUG("Not using doorbell -- " 321 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 322 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 323 ring->me, 324 lower_32_bits(ring->wptr << 2), 325 ring->me, 326 upper_32_bits(ring->wptr << 2)); 327 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 328 lower_32_bits(ring->wptr << 2)); 329 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 330 upper_32_bits(ring->wptr << 2)); 331 } 332 } 333 334 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 335 { 336 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 337 int i; 338 339 for (i = 0; i < count; i++) 340 if (sdma && sdma->burst_nop && (i == 0)) 341 amdgpu_ring_write(ring, ring->funcs->nop | 342 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 343 else 344 amdgpu_ring_write(ring, ring->funcs->nop); 345 } 346 347 /** 348 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine 349 * 350 * @ring: amdgpu ring pointer 351 * @ib: IB object to schedule 352 * 353 * Schedule an IB in the DMA ring (NAVI10). 354 */ 355 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 356 struct amdgpu_job *job, 357 struct amdgpu_ib *ib, 358 uint32_t flags) 359 { 360 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 361 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 362 363 /* IB packet must end on a 8 DW boundary */ 364 sdma_v5_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 365 366 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 367 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 368 /* base must be 32 byte aligned */ 369 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 370 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 371 amdgpu_ring_write(ring, ib->length_dw); 372 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 373 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 374 } 375 376 /** 377 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 378 * 379 * @ring: amdgpu ring pointer 380 * 381 * Emit an hdp flush packet on the requested DMA ring. 382 */ 383 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 384 { 385 struct amdgpu_device *adev = ring->adev; 386 u32 ref_and_mask = 0; 387 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 388 389 if (ring->me == 0) 390 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 391 else 392 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 393 394 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 395 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 396 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 397 amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2); 398 amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2); 399 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 400 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 401 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 402 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 403 } 404 405 /** 406 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring 407 * 408 * @ring: amdgpu ring pointer 409 * @fence: amdgpu fence object 410 * 411 * Add a DMA fence packet to the ring to write 412 * the fence seq number and DMA trap packet to generate 413 * an interrupt if needed (NAVI10). 414 */ 415 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 416 unsigned flags) 417 { 418 struct amdgpu_device *adev = ring->adev; 419 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 420 /* write the fence */ 421 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 422 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 423 /* zero in first two bits */ 424 BUG_ON(addr & 0x3); 425 amdgpu_ring_write(ring, lower_32_bits(addr)); 426 amdgpu_ring_write(ring, upper_32_bits(addr)); 427 amdgpu_ring_write(ring, lower_32_bits(seq)); 428 429 /* optionally write high bits as well */ 430 if (write64bit) { 431 addr += 4; 432 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 433 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 434 /* zero in first two bits */ 435 BUG_ON(addr & 0x3); 436 amdgpu_ring_write(ring, lower_32_bits(addr)); 437 amdgpu_ring_write(ring, upper_32_bits(addr)); 438 amdgpu_ring_write(ring, upper_32_bits(seq)); 439 } 440 441 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 442 if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) { 443 /* generate an interrupt */ 444 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 445 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 446 } 447 } 448 449 450 /** 451 * sdma_v5_0_gfx_stop - stop the gfx async dma engines 452 * 453 * @adev: amdgpu_device pointer 454 * 455 * Stop the gfx async dma ring buffers (NAVI10). 456 */ 457 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev) 458 { 459 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 460 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 461 u32 rb_cntl, ib_cntl; 462 int i; 463 464 if ((adev->mman.buffer_funcs_ring == sdma0) || 465 (adev->mman.buffer_funcs_ring == sdma1)) 466 amdgpu_ttm_set_buffer_funcs_status(adev, false); 467 468 for (i = 0; i < adev->sdma.num_instances; i++) { 469 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 470 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 471 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 472 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 473 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 474 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 475 } 476 477 sdma0->sched.ready = false; 478 sdma1->sched.ready = false; 479 } 480 481 /** 482 * sdma_v5_0_rlc_stop - stop the compute async dma engines 483 * 484 * @adev: amdgpu_device pointer 485 * 486 * Stop the compute async dma queues (NAVI10). 487 */ 488 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) 489 { 490 /* XXX todo */ 491 } 492 493 /** 494 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 495 * 496 * @adev: amdgpu_device pointer 497 * @enable: enable/disable the DMA MEs context switch. 498 * 499 * Halt or unhalt the async dma engines context switch (NAVI10). 500 */ 501 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 502 { 503 u32 f32_cntl, phase_quantum = 0; 504 int i; 505 506 if (amdgpu_sdma_phase_quantum) { 507 unsigned value = amdgpu_sdma_phase_quantum; 508 unsigned unit = 0; 509 510 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 511 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 512 value = (value + 1) >> 1; 513 unit++; 514 } 515 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 516 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 517 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 518 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 519 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 520 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 521 WARN_ONCE(1, 522 "clamping sdma_phase_quantum to %uK clock cycles\n", 523 value << unit); 524 } 525 phase_quantum = 526 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 527 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 528 } 529 530 for (i = 0; i < adev->sdma.num_instances; i++) { 531 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 532 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 533 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 534 if (enable && amdgpu_sdma_phase_quantum) { 535 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 536 phase_quantum); 537 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 538 phase_quantum); 539 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 540 phase_quantum); 541 } 542 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 543 } 544 545 } 546 547 /** 548 * sdma_v5_0_enable - stop the async dma engines 549 * 550 * @adev: amdgpu_device pointer 551 * @enable: enable/disable the DMA MEs. 552 * 553 * Halt or unhalt the async dma engines (NAVI10). 554 */ 555 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) 556 { 557 u32 f32_cntl; 558 int i; 559 560 if (enable == false) { 561 sdma_v5_0_gfx_stop(adev); 562 sdma_v5_0_rlc_stop(adev); 563 } 564 565 for (i = 0; i < adev->sdma.num_instances; i++) { 566 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 567 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 568 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 569 } 570 } 571 572 /** 573 * sdma_v5_0_gfx_resume - setup and start the async dma engines 574 * 575 * @adev: amdgpu_device pointer 576 * 577 * Set up the gfx DMA ring buffers and enable them (NAVI10). 578 * Returns 0 for success, error for failure. 579 */ 580 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) 581 { 582 struct amdgpu_ring *ring; 583 u32 rb_cntl, ib_cntl; 584 u32 rb_bufsz; 585 u32 wb_offset; 586 u32 doorbell; 587 u32 doorbell_offset; 588 u32 temp; 589 u32 wptr_poll_cntl; 590 u64 wptr_gpu_addr; 591 int i, r; 592 593 for (i = 0; i < adev->sdma.num_instances; i++) { 594 ring = &adev->sdma.instance[i].ring; 595 wb_offset = (ring->rptr_offs * 4); 596 597 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 598 599 /* Set ring buffer size in dwords */ 600 rb_bufsz = order_base_2(ring->ring_size / 4); 601 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 602 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 603 #ifdef __BIG_ENDIAN 604 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 605 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 606 RPTR_WRITEBACK_SWAP_ENABLE, 1); 607 #endif 608 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 609 610 /* Initialize the ring buffer's read and write pointers */ 611 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 612 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 613 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 614 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 615 616 /* setup the wptr shadow polling */ 617 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 618 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 619 lower_32_bits(wptr_gpu_addr)); 620 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 621 upper_32_bits(wptr_gpu_addr)); 622 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, 623 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 624 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 625 SDMA0_GFX_RB_WPTR_POLL_CNTL, 626 F32_POLL_ENABLE, 1); 627 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 628 wptr_poll_cntl); 629 630 /* set the wb address whether it's enabled or not */ 631 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 632 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 633 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 634 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 635 636 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 637 638 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 639 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 640 641 ring->wptr = 0; 642 643 /* before programing wptr to a less value, need set minor_ptr_update first */ 644 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 645 646 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 647 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 648 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 649 } 650 651 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 652 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 653 654 if (ring->use_doorbell) { 655 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 656 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 657 OFFSET, ring->doorbell_index); 658 } else { 659 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 660 } 661 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 662 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 663 664 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 665 ring->doorbell_index, 20); 666 667 if (amdgpu_sriov_vf(adev)) 668 sdma_v5_0_ring_set_wptr(ring); 669 670 /* set minor_ptr_update to 0 after wptr programed */ 671 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 672 673 /* set utc l1 enable flag always to 1 */ 674 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 675 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 676 677 /* enable MCBP */ 678 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 679 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 680 681 /* Set up RESP_MODE to non-copy addresses */ 682 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 683 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 684 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 685 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 686 687 /* program default cache read and write policy */ 688 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 689 /* clean read policy and write policy bits */ 690 temp &= 0xFF0FFF; 691 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 692 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 693 694 if (!amdgpu_sriov_vf(adev)) { 695 /* unhalt engine */ 696 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 697 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 698 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 699 } 700 701 /* enable DMA RB */ 702 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 703 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 704 705 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 706 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 707 #ifdef __BIG_ENDIAN 708 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 709 #endif 710 /* enable DMA IBs */ 711 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 712 713 ring->sched.ready = true; 714 715 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 716 sdma_v5_0_ctx_switch_enable(adev, true); 717 sdma_v5_0_enable(adev, true); 718 } 719 720 r = amdgpu_ring_test_ring(ring); 721 if (r) { 722 ring->sched.ready = false; 723 return r; 724 } 725 726 if (adev->mman.buffer_funcs_ring == ring) 727 amdgpu_ttm_set_buffer_funcs_status(adev, true); 728 } 729 730 return 0; 731 } 732 733 /** 734 * sdma_v5_0_rlc_resume - setup and start the async dma engines 735 * 736 * @adev: amdgpu_device pointer 737 * 738 * Set up the compute DMA queues and enable them (NAVI10). 739 * Returns 0 for success, error for failure. 740 */ 741 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev) 742 { 743 return 0; 744 } 745 746 /** 747 * sdma_v5_0_load_microcode - load the sDMA ME ucode 748 * 749 * @adev: amdgpu_device pointer 750 * 751 * Loads the sDMA0/1 ucode. 752 * Returns 0 for success, -EINVAL if the ucode is not available. 753 */ 754 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev) 755 { 756 const struct sdma_firmware_header_v1_0 *hdr; 757 const __le32 *fw_data; 758 u32 fw_size; 759 int i, j; 760 761 /* halt the MEs */ 762 sdma_v5_0_enable(adev, false); 763 764 for (i = 0; i < adev->sdma.num_instances; i++) { 765 if (!adev->sdma.instance[i].fw) 766 return -EINVAL; 767 768 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 769 amdgpu_ucode_print_sdma_hdr(&hdr->header); 770 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 771 772 fw_data = (const __le32 *) 773 (adev->sdma.instance[i].fw->data + 774 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 775 776 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 777 778 for (j = 0; j < fw_size; j++) { 779 if (amdgpu_emu_mode == 1 && j % 500 == 0) 780 msleep(1); 781 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 782 } 783 784 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 785 } 786 787 return 0; 788 } 789 790 /** 791 * sdma_v5_0_start - setup and start the async dma engines 792 * 793 * @adev: amdgpu_device pointer 794 * 795 * Set up the DMA engines and enable them (NAVI10). 796 * Returns 0 for success, error for failure. 797 */ 798 static int sdma_v5_0_start(struct amdgpu_device *adev) 799 { 800 int r = 0; 801 802 if (amdgpu_sriov_vf(adev)) { 803 sdma_v5_0_ctx_switch_enable(adev, false); 804 sdma_v5_0_enable(adev, false); 805 806 /* set RB registers */ 807 r = sdma_v5_0_gfx_resume(adev); 808 return r; 809 } 810 811 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 812 r = sdma_v5_0_load_microcode(adev); 813 if (r) 814 return r; 815 816 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 817 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d) 818 msleep(1000); 819 } 820 821 /* unhalt the MEs */ 822 sdma_v5_0_enable(adev, true); 823 /* enable sdma ring preemption */ 824 sdma_v5_0_ctx_switch_enable(adev, true); 825 826 /* start the gfx rings and rlc compute queues */ 827 r = sdma_v5_0_gfx_resume(adev); 828 if (r) 829 return r; 830 r = sdma_v5_0_rlc_resume(adev); 831 832 return r; 833 } 834 835 /** 836 * sdma_v5_0_ring_test_ring - simple async dma engine test 837 * 838 * @ring: amdgpu_ring structure holding ring information 839 * 840 * Test the DMA engine by writing using it to write an 841 * value to memory. (NAVI10). 842 * Returns 0 for success, error for failure. 843 */ 844 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) 845 { 846 struct amdgpu_device *adev = ring->adev; 847 unsigned i; 848 unsigned index; 849 int r; 850 u32 tmp; 851 u64 gpu_addr; 852 853 r = amdgpu_device_wb_get(adev, &index); 854 if (r) { 855 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 856 return r; 857 } 858 859 gpu_addr = adev->wb.gpu_addr + (index * 4); 860 tmp = 0xCAFEDEAD; 861 adev->wb.wb[index] = cpu_to_le32(tmp); 862 863 r = amdgpu_ring_alloc(ring, 5); 864 if (r) { 865 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 866 amdgpu_device_wb_free(adev, index); 867 return r; 868 } 869 870 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 871 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 872 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 873 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 874 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 875 amdgpu_ring_write(ring, 0xDEADBEEF); 876 amdgpu_ring_commit(ring); 877 878 for (i = 0; i < adev->usec_timeout; i++) { 879 tmp = le32_to_cpu(adev->wb.wb[index]); 880 if (tmp == 0xDEADBEEF) 881 break; 882 if (amdgpu_emu_mode == 1) 883 msleep(1); 884 else 885 DRM_UDELAY(1); 886 } 887 888 if (i < adev->usec_timeout) { 889 if (amdgpu_emu_mode == 1) 890 DRM_INFO("ring test on %d succeeded in %d msecs\n", ring->idx, i); 891 else 892 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 893 } else { 894 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 895 ring->idx, tmp); 896 r = -EINVAL; 897 } 898 amdgpu_device_wb_free(adev, index); 899 900 return r; 901 } 902 903 /** 904 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine 905 * 906 * @ring: amdgpu_ring structure holding ring information 907 * 908 * Test a simple IB in the DMA ring (NAVI10). 909 * Returns 0 on success, error on failure. 910 */ 911 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 912 { 913 struct amdgpu_device *adev = ring->adev; 914 struct amdgpu_ib ib; 915 struct dma_fence *f = NULL; 916 unsigned index; 917 long r; 918 u32 tmp = 0; 919 u64 gpu_addr; 920 921 r = amdgpu_device_wb_get(adev, &index); 922 if (r) { 923 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 924 return r; 925 } 926 927 gpu_addr = adev->wb.gpu_addr + (index * 4); 928 tmp = 0xCAFEDEAD; 929 adev->wb.wb[index] = cpu_to_le32(tmp); 930 memset(&ib, 0, sizeof(ib)); 931 r = amdgpu_ib_get(adev, NULL, 256, &ib); 932 if (r) { 933 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 934 goto err0; 935 } 936 937 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 938 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 939 ib.ptr[1] = lower_32_bits(gpu_addr); 940 ib.ptr[2] = upper_32_bits(gpu_addr); 941 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 942 ib.ptr[4] = 0xDEADBEEF; 943 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 944 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 945 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 946 ib.length_dw = 8; 947 948 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 949 if (r) 950 goto err1; 951 952 r = dma_fence_wait_timeout(f, false, timeout); 953 if (r == 0) { 954 DRM_ERROR("amdgpu: IB test timed out\n"); 955 r = -ETIMEDOUT; 956 goto err1; 957 } else if (r < 0) { 958 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 959 goto err1; 960 } 961 tmp = le32_to_cpu(adev->wb.wb[index]); 962 if (tmp == 0xDEADBEEF) { 963 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 964 r = 0; 965 } else { 966 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 967 r = -EINVAL; 968 } 969 970 err1: 971 amdgpu_ib_free(adev, &ib, NULL); 972 dma_fence_put(f); 973 err0: 974 amdgpu_device_wb_free(adev, index); 975 return r; 976 } 977 978 979 /** 980 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART 981 * 982 * @ib: indirect buffer to fill with commands 983 * @pe: addr of the page entry 984 * @src: src addr to copy from 985 * @count: number of page entries to update 986 * 987 * Update PTEs by copying them from the GART using sDMA (NAVI10). 988 */ 989 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib, 990 uint64_t pe, uint64_t src, 991 unsigned count) 992 { 993 unsigned bytes = count * 8; 994 995 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 996 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 997 ib->ptr[ib->length_dw++] = bytes - 1; 998 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 999 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1000 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1001 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1002 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1003 1004 } 1005 1006 /** 1007 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually 1008 * 1009 * @ib: indirect buffer to fill with commands 1010 * @pe: addr of the page entry 1011 * @addr: dst addr to write into pe 1012 * @count: number of page entries to update 1013 * @incr: increase next addr by incr bytes 1014 * @flags: access flags 1015 * 1016 * Update PTEs by writing them manually using sDMA (NAVI10). 1017 */ 1018 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1019 uint64_t value, unsigned count, 1020 uint32_t incr) 1021 { 1022 unsigned ndw = count * 2; 1023 1024 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1025 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1026 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1027 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1028 ib->ptr[ib->length_dw++] = ndw - 1; 1029 for (; ndw > 0; ndw -= 2) { 1030 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1031 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1032 value += incr; 1033 } 1034 } 1035 1036 /** 1037 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA 1038 * 1039 * @ib: indirect buffer to fill with commands 1040 * @pe: addr of the page entry 1041 * @addr: dst addr to write into pe 1042 * @count: number of page entries to update 1043 * @incr: increase next addr by incr bytes 1044 * @flags: access flags 1045 * 1046 * Update the page tables using sDMA (NAVI10). 1047 */ 1048 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1049 uint64_t pe, 1050 uint64_t addr, unsigned count, 1051 uint32_t incr, uint64_t flags) 1052 { 1053 /* for physically contiguous pages (vram) */ 1054 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1055 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1056 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1057 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1058 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1059 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1060 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1061 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1062 ib->ptr[ib->length_dw++] = 0; 1063 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1064 } 1065 1066 /** 1067 * sdma_v5_0_ring_pad_ib - pad the IB to the required number of dw 1068 * 1069 * @ib: indirect buffer to fill with padding 1070 * 1071 */ 1072 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1073 { 1074 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1075 u32 pad_count; 1076 int i; 1077 1078 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1079 for (i = 0; i < pad_count; i++) 1080 if (sdma && sdma->burst_nop && (i == 0)) 1081 ib->ptr[ib->length_dw++] = 1082 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1083 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1084 else 1085 ib->ptr[ib->length_dw++] = 1086 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1087 } 1088 1089 1090 /** 1091 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline 1092 * 1093 * @ring: amdgpu_ring pointer 1094 * 1095 * Make sure all previous operations are completed (CIK). 1096 */ 1097 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1098 { 1099 uint32_t seq = ring->fence_drv.sync_seq; 1100 uint64_t addr = ring->fence_drv.gpu_addr; 1101 1102 /* wait for idle */ 1103 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1104 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1105 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1106 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1107 amdgpu_ring_write(ring, addr & 0xfffffffc); 1108 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1109 amdgpu_ring_write(ring, seq); /* reference */ 1110 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 1111 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1112 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1113 } 1114 1115 1116 /** 1117 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA 1118 * 1119 * @ring: amdgpu_ring pointer 1120 * @vm: amdgpu_vm pointer 1121 * 1122 * Update the page table base and flush the VM TLB 1123 * using sDMA (NAVI10). 1124 */ 1125 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1126 unsigned vmid, uint64_t pd_addr) 1127 { 1128 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1129 } 1130 1131 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring, 1132 uint32_t reg, uint32_t val) 1133 { 1134 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1135 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1136 amdgpu_ring_write(ring, reg); 1137 amdgpu_ring_write(ring, val); 1138 } 1139 1140 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1141 uint32_t val, uint32_t mask) 1142 { 1143 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1144 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1145 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1146 amdgpu_ring_write(ring, reg << 2); 1147 amdgpu_ring_write(ring, 0); 1148 amdgpu_ring_write(ring, val); /* reference */ 1149 amdgpu_ring_write(ring, mask); /* mask */ 1150 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1151 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1152 } 1153 1154 static int sdma_v5_0_early_init(void *handle) 1155 { 1156 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1157 1158 adev->sdma.num_instances = 2; 1159 1160 sdma_v5_0_set_ring_funcs(adev); 1161 sdma_v5_0_set_buffer_funcs(adev); 1162 sdma_v5_0_set_vm_pte_funcs(adev); 1163 sdma_v5_0_set_irq_funcs(adev); 1164 1165 return 0; 1166 } 1167 1168 1169 static int sdma_v5_0_sw_init(void *handle) 1170 { 1171 struct amdgpu_ring *ring; 1172 int r, i; 1173 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1174 1175 /* SDMA trap event */ 1176 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 1177 SDMA0_5_0__SRCID__SDMA_TRAP, 1178 &adev->sdma.trap_irq); 1179 if (r) 1180 return r; 1181 1182 /* SDMA trap event */ 1183 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 1184 SDMA1_5_0__SRCID__SDMA_TRAP, 1185 &adev->sdma.trap_irq); 1186 if (r) 1187 return r; 1188 1189 r = sdma_v5_0_init_microcode(adev); 1190 if (r) { 1191 DRM_ERROR("Failed to load sdma firmware!\n"); 1192 return r; 1193 } 1194 1195 for (i = 0; i < adev->sdma.num_instances; i++) { 1196 ring = &adev->sdma.instance[i].ring; 1197 ring->ring_obj = NULL; 1198 ring->use_doorbell = true; 1199 1200 DRM_INFO("use_doorbell being set to: [%s]\n", 1201 ring->use_doorbell?"true":"false"); 1202 1203 ring->doorbell_index = (i == 0) ? 1204 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset 1205 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset 1206 1207 sprintf(ring->name, "sdma%d", i); 1208 r = amdgpu_ring_init(adev, ring, 1024, 1209 &adev->sdma.trap_irq, 1210 (i == 0) ? 1211 AMDGPU_SDMA_IRQ_INSTANCE0 : 1212 AMDGPU_SDMA_IRQ_INSTANCE1); 1213 if (r) 1214 return r; 1215 } 1216 1217 return r; 1218 } 1219 1220 static int sdma_v5_0_sw_fini(void *handle) 1221 { 1222 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1223 int i; 1224 1225 for (i = 0; i < adev->sdma.num_instances; i++) 1226 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1227 1228 return 0; 1229 } 1230 1231 static int sdma_v5_0_hw_init(void *handle) 1232 { 1233 int r; 1234 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1235 1236 sdma_v5_0_init_golden_registers(adev); 1237 1238 r = sdma_v5_0_start(adev); 1239 1240 return r; 1241 } 1242 1243 static int sdma_v5_0_hw_fini(void *handle) 1244 { 1245 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1246 1247 if (amdgpu_sriov_vf(adev)) 1248 return 0; 1249 1250 sdma_v5_0_ctx_switch_enable(adev, false); 1251 sdma_v5_0_enable(adev, false); 1252 1253 return 0; 1254 } 1255 1256 static int sdma_v5_0_suspend(void *handle) 1257 { 1258 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1259 1260 return sdma_v5_0_hw_fini(adev); 1261 } 1262 1263 static int sdma_v5_0_resume(void *handle) 1264 { 1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1266 1267 return sdma_v5_0_hw_init(adev); 1268 } 1269 1270 static bool sdma_v5_0_is_idle(void *handle) 1271 { 1272 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1273 u32 i; 1274 1275 for (i = 0; i < adev->sdma.num_instances; i++) { 1276 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1277 1278 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1279 return false; 1280 } 1281 1282 return true; 1283 } 1284 1285 static int sdma_v5_0_wait_for_idle(void *handle) 1286 { 1287 unsigned i; 1288 u32 sdma0, sdma1; 1289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1290 1291 for (i = 0; i < adev->usec_timeout; i++) { 1292 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1293 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1294 1295 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1296 return 0; 1297 udelay(1); 1298 } 1299 return -ETIMEDOUT; 1300 } 1301 1302 static int sdma_v5_0_soft_reset(void *handle) 1303 { 1304 /* todo */ 1305 1306 return 0; 1307 } 1308 1309 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring) 1310 { 1311 int i, r = 0; 1312 struct amdgpu_device *adev = ring->adev; 1313 u32 index = 0; 1314 u64 sdma_gfx_preempt; 1315 1316 amdgpu_sdma_get_index_from_ring(ring, &index); 1317 if (index == 0) 1318 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT; 1319 else 1320 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT; 1321 1322 /* assert preemption condition */ 1323 amdgpu_ring_set_preempt_cond_exec(ring, false); 1324 1325 /* emit the trailing fence */ 1326 ring->trail_seq += 1; 1327 amdgpu_ring_alloc(ring, 10); 1328 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1329 ring->trail_seq, 0); 1330 amdgpu_ring_commit(ring); 1331 1332 /* assert IB preemption */ 1333 WREG32(sdma_gfx_preempt, 1); 1334 1335 /* poll the trailing fence */ 1336 for (i = 0; i < adev->usec_timeout; i++) { 1337 if (ring->trail_seq == 1338 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1339 break; 1340 DRM_UDELAY(1); 1341 } 1342 1343 if (i >= adev->usec_timeout) { 1344 r = -EINVAL; 1345 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1346 } 1347 1348 /* deassert IB preemption */ 1349 WREG32(sdma_gfx_preempt, 0); 1350 1351 /* deassert the preemption condition */ 1352 amdgpu_ring_set_preempt_cond_exec(ring, true); 1353 return r; 1354 } 1355 1356 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev, 1357 struct amdgpu_irq_src *source, 1358 unsigned type, 1359 enum amdgpu_interrupt_state state) 1360 { 1361 u32 sdma_cntl; 1362 1363 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? 1364 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1365 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1366 1367 sdma_cntl = RREG32(reg_offset); 1368 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1369 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1370 WREG32(reg_offset, sdma_cntl); 1371 1372 return 0; 1373 } 1374 1375 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, 1376 struct amdgpu_irq_src *source, 1377 struct amdgpu_iv_entry *entry) 1378 { 1379 DRM_DEBUG("IH: SDMA trap\n"); 1380 switch (entry->client_id) { 1381 case SOC15_IH_CLIENTID_SDMA0: 1382 switch (entry->ring_id) { 1383 case 0: 1384 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1385 break; 1386 case 1: 1387 /* XXX compute */ 1388 break; 1389 case 2: 1390 /* XXX compute */ 1391 break; 1392 case 3: 1393 /* XXX page queue*/ 1394 break; 1395 } 1396 break; 1397 case SOC15_IH_CLIENTID_SDMA1: 1398 switch (entry->ring_id) { 1399 case 0: 1400 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1401 break; 1402 case 1: 1403 /* XXX compute */ 1404 break; 1405 case 2: 1406 /* XXX compute */ 1407 break; 1408 case 3: 1409 /* XXX page queue*/ 1410 break; 1411 } 1412 break; 1413 } 1414 return 0; 1415 } 1416 1417 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1418 struct amdgpu_irq_src *source, 1419 struct amdgpu_iv_entry *entry) 1420 { 1421 return 0; 1422 } 1423 1424 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1425 bool enable) 1426 { 1427 uint32_t data, def; 1428 int i; 1429 1430 for (i = 0; i < adev->sdma.num_instances; i++) { 1431 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1432 /* Enable sdma clock gating */ 1433 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1434 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1435 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1436 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1437 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1438 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1439 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1440 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1441 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1442 if (def != data) 1443 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1444 } else { 1445 /* Disable sdma clock gating */ 1446 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1447 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1448 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1449 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1450 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1451 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1452 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1453 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1454 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1455 if (def != data) 1456 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1457 } 1458 } 1459 } 1460 1461 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1462 bool enable) 1463 { 1464 uint32_t data, def; 1465 int i; 1466 1467 for (i = 0; i < adev->sdma.num_instances; i++) { 1468 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1469 /* Enable sdma mem light sleep */ 1470 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1471 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1472 if (def != data) 1473 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1474 1475 } else { 1476 /* Disable sdma mem light sleep */ 1477 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1478 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1479 if (def != data) 1480 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1481 1482 } 1483 } 1484 } 1485 1486 static int sdma_v5_0_set_clockgating_state(void *handle, 1487 enum amd_clockgating_state state) 1488 { 1489 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1490 1491 if (amdgpu_sriov_vf(adev)) 1492 return 0; 1493 1494 switch (adev->asic_type) { 1495 case CHIP_NAVI10: 1496 case CHIP_NAVI14: 1497 sdma_v5_0_update_medium_grain_clock_gating(adev, 1498 state == AMD_CG_STATE_GATE ? true : false); 1499 sdma_v5_0_update_medium_grain_light_sleep(adev, 1500 state == AMD_CG_STATE_GATE ? true : false); 1501 break; 1502 default: 1503 break; 1504 } 1505 1506 return 0; 1507 } 1508 1509 static int sdma_v5_0_set_powergating_state(void *handle, 1510 enum amd_powergating_state state) 1511 { 1512 return 0; 1513 } 1514 1515 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags) 1516 { 1517 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1518 int data; 1519 1520 if (amdgpu_sriov_vf(adev)) 1521 *flags = 0; 1522 1523 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1524 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1525 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1526 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1527 1528 /* AMD_CG_SUPPORT_SDMA_LS */ 1529 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1530 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1531 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1532 } 1533 1534 const struct amd_ip_funcs sdma_v5_0_ip_funcs = { 1535 .name = "sdma_v5_0", 1536 .early_init = sdma_v5_0_early_init, 1537 .late_init = NULL, 1538 .sw_init = sdma_v5_0_sw_init, 1539 .sw_fini = sdma_v5_0_sw_fini, 1540 .hw_init = sdma_v5_0_hw_init, 1541 .hw_fini = sdma_v5_0_hw_fini, 1542 .suspend = sdma_v5_0_suspend, 1543 .resume = sdma_v5_0_resume, 1544 .is_idle = sdma_v5_0_is_idle, 1545 .wait_for_idle = sdma_v5_0_wait_for_idle, 1546 .soft_reset = sdma_v5_0_soft_reset, 1547 .set_clockgating_state = sdma_v5_0_set_clockgating_state, 1548 .set_powergating_state = sdma_v5_0_set_powergating_state, 1549 .get_clockgating_state = sdma_v5_0_get_clockgating_state, 1550 }; 1551 1552 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 1553 .type = AMDGPU_RING_TYPE_SDMA, 1554 .align_mask = 0xf, 1555 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1556 .support_64bit_ptrs = true, 1557 .vmhub = AMDGPU_GFXHUB_0, 1558 .get_rptr = sdma_v5_0_ring_get_rptr, 1559 .get_wptr = sdma_v5_0_ring_get_wptr, 1560 .set_wptr = sdma_v5_0_ring_set_wptr, 1561 .emit_frame_size = 1562 5 + /* sdma_v5_0_ring_init_cond_exec */ 1563 6 + /* sdma_v5_0_ring_emit_hdp_flush */ 1564 3 + /* hdp_invalidate */ 1565 6 + /* sdma_v5_0_ring_emit_pipeline_sync */ 1566 /* sdma_v5_0_ring_emit_vm_flush */ 1567 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1568 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1569 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ 1570 .emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */ 1571 .emit_ib = sdma_v5_0_ring_emit_ib, 1572 .emit_fence = sdma_v5_0_ring_emit_fence, 1573 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync, 1574 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush, 1575 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush, 1576 .test_ring = sdma_v5_0_ring_test_ring, 1577 .test_ib = sdma_v5_0_ring_test_ib, 1578 .insert_nop = sdma_v5_0_ring_insert_nop, 1579 .pad_ib = sdma_v5_0_ring_pad_ib, 1580 .emit_wreg = sdma_v5_0_ring_emit_wreg, 1581 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait, 1582 .init_cond_exec = sdma_v5_0_ring_init_cond_exec, 1583 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec, 1584 .preempt_ib = sdma_v5_0_ring_preempt_ib, 1585 }; 1586 1587 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) 1588 { 1589 int i; 1590 1591 for (i = 0; i < adev->sdma.num_instances; i++) { 1592 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; 1593 adev->sdma.instance[i].ring.me = i; 1594 } 1595 } 1596 1597 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = { 1598 .set = sdma_v5_0_set_trap_irq_state, 1599 .process = sdma_v5_0_process_trap_irq, 1600 }; 1601 1602 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = { 1603 .process = sdma_v5_0_process_illegal_inst_irq, 1604 }; 1605 1606 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev) 1607 { 1608 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1609 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; 1610 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; 1611 } 1612 1613 /** 1614 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine 1615 * 1616 * @ring: amdgpu_ring structure holding ring information 1617 * @src_offset: src GPU address 1618 * @dst_offset: dst GPU address 1619 * @byte_count: number of bytes to xfer 1620 * 1621 * Copy GPU buffers using the DMA engine (NAVI10). 1622 * Used by the amdgpu ttm implementation to move pages if 1623 * registered as the asic copy callback. 1624 */ 1625 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib, 1626 uint64_t src_offset, 1627 uint64_t dst_offset, 1628 uint32_t byte_count) 1629 { 1630 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1631 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1632 ib->ptr[ib->length_dw++] = byte_count - 1; 1633 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1634 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1635 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1636 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1637 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1638 } 1639 1640 /** 1641 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine 1642 * 1643 * @ring: amdgpu_ring structure holding ring information 1644 * @src_data: value to write to buffer 1645 * @dst_offset: dst GPU address 1646 * @byte_count: number of bytes to xfer 1647 * 1648 * Fill GPU buffers using the DMA engine (NAVI10). 1649 */ 1650 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib, 1651 uint32_t src_data, 1652 uint64_t dst_offset, 1653 uint32_t byte_count) 1654 { 1655 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1656 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1657 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1658 ib->ptr[ib->length_dw++] = src_data; 1659 ib->ptr[ib->length_dw++] = byte_count - 1; 1660 } 1661 1662 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { 1663 .copy_max_bytes = 0x400000, 1664 .copy_num_dw = 7, 1665 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer, 1666 1667 .fill_max_bytes = 0x400000, 1668 .fill_num_dw = 5, 1669 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer, 1670 }; 1671 1672 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) 1673 { 1674 if (adev->mman.buffer_funcs == NULL) { 1675 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; 1676 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1677 } 1678 } 1679 1680 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 1681 .copy_pte_num_dw = 7, 1682 .copy_pte = sdma_v5_0_vm_copy_pte, 1683 .write_pte = sdma_v5_0_vm_write_pte, 1684 .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 1685 }; 1686 1687 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1688 { 1689 struct drm_gpu_scheduler *sched; 1690 unsigned i; 1691 1692 if (adev->vm_manager.vm_pte_funcs == NULL) { 1693 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; 1694 for (i = 0; i < adev->sdma.num_instances; i++) { 1695 sched = &adev->sdma.instance[i].ring.sched; 1696 adev->vm_manager.vm_pte_rqs[i] = 1697 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 1698 } 1699 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 1700 } 1701 } 1702 1703 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { 1704 .type = AMD_IP_BLOCK_TYPE_SDMA, 1705 .major = 5, 1706 .minor = 0, 1707 .rev = 0, 1708 .funcs = &sdma_v5_0_ip_funcs, 1709 }; 1710