1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "gc/gc_10_1_0_offset.h" 31 #include "gc/gc_10_1_0_sh_mask.h" 32 #include "hdp/hdp_5_0_0_offset.h" 33 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 34 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 35 36 #include "soc15_common.h" 37 #include "soc15.h" 38 #include "navi10_sdma_pkt_open.h" 39 #include "nbio_v2_3.h" 40 #include "sdma_v5_0.h" 41 42 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); 43 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); 44 45 #define SDMA1_REG_OFFSET 0x600 46 #define SDMA0_HYP_DEC_REG_START 0x5880 47 #define SDMA0_HYP_DEC_REG_END 0x5893 48 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 49 50 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); 51 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); 52 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); 53 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); 54 55 static const struct soc15_reg_golden golden_settings_sdma_5[] = { 56 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 57 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 58 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 59 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 60 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 61 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 62 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 63 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 64 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 65 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00), 68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00) 80 }; 81 82 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { 83 }; 84 85 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 86 { 87 u32 base; 88 89 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 90 internal_offset <= SDMA0_HYP_DEC_REG_END) { 91 base = adev->reg_offset[GC_HWIP][0][1]; 92 if (instance == 1) 93 internal_offset += SDMA1_HYP_DEC_REG_OFFSET; 94 } else { 95 base = adev->reg_offset[GC_HWIP][0][0]; 96 if (instance == 1) 97 internal_offset += SDMA1_REG_OFFSET; 98 } 99 100 return base + internal_offset; 101 } 102 103 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) 104 { 105 switch (adev->asic_type) { 106 case CHIP_NAVI10: 107 soc15_program_register_sequence(adev, 108 golden_settings_sdma_5, 109 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 110 soc15_program_register_sequence(adev, 111 golden_settings_sdma_nv10, 112 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); 113 break; 114 default: 115 break; 116 } 117 } 118 119 /** 120 * sdma_v5_0_init_microcode - load ucode images from disk 121 * 122 * @adev: amdgpu_device pointer 123 * 124 * Use the firmware interface to load the ucode images into 125 * the driver (not loaded into hw). 126 * Returns 0 on success, error on failure. 127 */ 128 129 // emulation only, won't work on real chip 130 // navi10 real chip need to use PSP to load firmware 131 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) 132 { 133 const char *chip_name; 134 char fw_name[30]; 135 int err = 0, i; 136 struct amdgpu_firmware_info *info = NULL; 137 const struct common_firmware_header *header = NULL; 138 const struct sdma_firmware_header_v1_0 *hdr; 139 140 DRM_DEBUG("\n"); 141 142 switch (adev->asic_type) { 143 case CHIP_NAVI10: 144 chip_name = "navi10"; 145 break; 146 default: 147 BUG(); 148 } 149 150 for (i = 0; i < adev->sdma.num_instances; i++) { 151 if (i == 0) 152 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 153 else 154 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 155 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 156 if (err) 157 goto out; 158 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 159 if (err) 160 goto out; 161 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 162 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 163 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 164 if (adev->sdma.instance[i].feature_version >= 20) 165 adev->sdma.instance[i].burst_nop = true; 166 DRM_DEBUG("psp_load == '%s'\n", 167 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 168 169 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 170 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 171 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 172 info->fw = adev->sdma.instance[i].fw; 173 header = (const struct common_firmware_header *)info->fw->data; 174 adev->firmware.fw_size += 175 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 176 } 177 } 178 out: 179 if (err) { 180 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name); 181 for (i = 0; i < adev->sdma.num_instances; i++) { 182 release_firmware(adev->sdma.instance[i].fw); 183 adev->sdma.instance[i].fw = NULL; 184 } 185 } 186 return err; 187 } 188 189 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring) 190 { 191 unsigned ret; 192 193 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 194 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 195 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 196 amdgpu_ring_write(ring, 1); 197 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 198 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 199 200 return ret; 201 } 202 203 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 204 unsigned offset) 205 { 206 unsigned cur; 207 208 BUG_ON(offset > ring->buf_mask); 209 BUG_ON(ring->ring[offset] != 0x55aa55aa); 210 211 cur = (ring->wptr - 1) & ring->buf_mask; 212 if (cur > offset) 213 ring->ring[offset] = cur - offset; 214 else 215 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 216 } 217 218 /** 219 * sdma_v5_0_ring_get_rptr - get the current read pointer 220 * 221 * @ring: amdgpu ring pointer 222 * 223 * Get the current rptr from the hardware (NAVI10+). 224 */ 225 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 226 { 227 u64 *rptr; 228 229 /* XXX check if swapping is necessary on BE */ 230 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 231 232 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 233 return ((*rptr) >> 2); 234 } 235 236 /** 237 * sdma_v5_0_ring_get_wptr - get the current write pointer 238 * 239 * @ring: amdgpu ring pointer 240 * 241 * Get the current wptr from the hardware (NAVI10+). 242 */ 243 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 244 { 245 struct amdgpu_device *adev = ring->adev; 246 u64 *wptr = NULL; 247 uint64_t local_wptr = 0; 248 249 if (ring->use_doorbell) { 250 /* XXX check if swapping is necessary on BE */ 251 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); 252 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); 253 *wptr = (*wptr) >> 2; 254 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); 255 } else { 256 u32 lowbit, highbit; 257 258 wptr = &local_wptr; 259 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2; 260 highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 261 262 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 263 ring->me, highbit, lowbit); 264 *wptr = highbit; 265 *wptr = (*wptr) << 32; 266 *wptr |= lowbit; 267 } 268 269 return *wptr; 270 } 271 272 /** 273 * sdma_v5_0_ring_set_wptr - commit the write pointer 274 * 275 * @ring: amdgpu ring pointer 276 * 277 * Write the wptr back to the hardware (NAVI10+). 278 */ 279 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 280 { 281 struct amdgpu_device *adev = ring->adev; 282 283 DRM_DEBUG("Setting write pointer\n"); 284 if (ring->use_doorbell) { 285 DRM_DEBUG("Using doorbell -- " 286 "wptr_offs == 0x%08x " 287 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 288 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 289 ring->wptr_offs, 290 lower_32_bits(ring->wptr << 2), 291 upper_32_bits(ring->wptr << 2)); 292 /* XXX check if swapping is necessary on BE */ 293 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 294 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 295 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 296 ring->doorbell_index, ring->wptr << 2); 297 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 298 } else { 299 DRM_DEBUG("Not using doorbell -- " 300 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 301 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 302 ring->me, 303 lower_32_bits(ring->wptr << 2), 304 ring->me, 305 upper_32_bits(ring->wptr << 2)); 306 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 307 lower_32_bits(ring->wptr << 2)); 308 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 309 upper_32_bits(ring->wptr << 2)); 310 } 311 } 312 313 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 314 { 315 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 316 int i; 317 318 for (i = 0; i < count; i++) 319 if (sdma && sdma->burst_nop && (i == 0)) 320 amdgpu_ring_write(ring, ring->funcs->nop | 321 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 322 else 323 amdgpu_ring_write(ring, ring->funcs->nop); 324 } 325 326 /** 327 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine 328 * 329 * @ring: amdgpu ring pointer 330 * @ib: IB object to schedule 331 * 332 * Schedule an IB in the DMA ring (NAVI10). 333 */ 334 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 335 struct amdgpu_job *job, 336 struct amdgpu_ib *ib, 337 uint32_t flags) 338 { 339 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 340 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 341 342 /* IB packet must end on a 8 DW boundary */ 343 sdma_v5_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 344 345 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 346 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 347 /* base must be 32 byte aligned */ 348 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 349 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 350 amdgpu_ring_write(ring, ib->length_dw); 351 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 352 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 353 } 354 355 /** 356 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 357 * 358 * @ring: amdgpu ring pointer 359 * 360 * Emit an hdp flush packet on the requested DMA ring. 361 */ 362 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 363 { 364 struct amdgpu_device *adev = ring->adev; 365 u32 ref_and_mask = 0; 366 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 367 368 if (ring->me == 0) 369 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 370 else 371 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 372 373 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 374 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 375 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 376 amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2); 377 amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2); 378 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 379 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 380 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 381 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 382 } 383 384 /** 385 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring 386 * 387 * @ring: amdgpu ring pointer 388 * @fence: amdgpu fence object 389 * 390 * Add a DMA fence packet to the ring to write 391 * the fence seq number and DMA trap packet to generate 392 * an interrupt if needed (NAVI10). 393 */ 394 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 395 unsigned flags) 396 { 397 struct amdgpu_device *adev = ring->adev; 398 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 399 /* write the fence */ 400 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 401 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 402 /* zero in first two bits */ 403 BUG_ON(addr & 0x3); 404 amdgpu_ring_write(ring, lower_32_bits(addr)); 405 amdgpu_ring_write(ring, upper_32_bits(addr)); 406 amdgpu_ring_write(ring, lower_32_bits(seq)); 407 408 /* optionally write high bits as well */ 409 if (write64bit) { 410 addr += 4; 411 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 412 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 413 /* zero in first two bits */ 414 BUG_ON(addr & 0x3); 415 amdgpu_ring_write(ring, lower_32_bits(addr)); 416 amdgpu_ring_write(ring, upper_32_bits(addr)); 417 amdgpu_ring_write(ring, upper_32_bits(seq)); 418 } 419 420 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 421 if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) { 422 /* generate an interrupt */ 423 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 424 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 425 } 426 } 427 428 429 /** 430 * sdma_v5_0_gfx_stop - stop the gfx async dma engines 431 * 432 * @adev: amdgpu_device pointer 433 * 434 * Stop the gfx async dma ring buffers (NAVI10). 435 */ 436 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev) 437 { 438 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 439 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 440 u32 rb_cntl, ib_cntl; 441 int i; 442 443 if ((adev->mman.buffer_funcs_ring == sdma0) || 444 (adev->mman.buffer_funcs_ring == sdma1)) 445 amdgpu_ttm_set_buffer_funcs_status(adev, false); 446 447 for (i = 0; i < adev->sdma.num_instances; i++) { 448 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 449 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 450 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 451 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 452 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 453 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 454 } 455 456 sdma0->sched.ready = false; 457 sdma1->sched.ready = false; 458 } 459 460 /** 461 * sdma_v5_0_rlc_stop - stop the compute async dma engines 462 * 463 * @adev: amdgpu_device pointer 464 * 465 * Stop the compute async dma queues (NAVI10). 466 */ 467 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) 468 { 469 /* XXX todo */ 470 } 471 472 /** 473 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 474 * 475 * @adev: amdgpu_device pointer 476 * @enable: enable/disable the DMA MEs context switch. 477 * 478 * Halt or unhalt the async dma engines context switch (NAVI10). 479 */ 480 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 481 { 482 u32 f32_cntl, phase_quantum = 0; 483 int i; 484 485 if (amdgpu_sdma_phase_quantum) { 486 unsigned value = amdgpu_sdma_phase_quantum; 487 unsigned unit = 0; 488 489 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 490 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 491 value = (value + 1) >> 1; 492 unit++; 493 } 494 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 495 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 496 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 497 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 498 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 499 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 500 WARN_ONCE(1, 501 "clamping sdma_phase_quantum to %uK clock cycles\n", 502 value << unit); 503 } 504 phase_quantum = 505 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 506 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 507 } 508 509 for (i = 0; i < adev->sdma.num_instances; i++) { 510 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 511 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 512 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 513 if (enable && amdgpu_sdma_phase_quantum) { 514 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 515 phase_quantum); 516 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 517 phase_quantum); 518 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 519 phase_quantum); 520 } 521 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 522 } 523 524 } 525 526 /** 527 * sdma_v5_0_enable - stop the async dma engines 528 * 529 * @adev: amdgpu_device pointer 530 * @enable: enable/disable the DMA MEs. 531 * 532 * Halt or unhalt the async dma engines (NAVI10). 533 */ 534 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) 535 { 536 u32 f32_cntl; 537 int i; 538 539 if (enable == false) { 540 sdma_v5_0_gfx_stop(adev); 541 sdma_v5_0_rlc_stop(adev); 542 } 543 544 for (i = 0; i < adev->sdma.num_instances; i++) { 545 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 546 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 547 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 548 } 549 } 550 551 /** 552 * sdma_v5_0_gfx_resume - setup and start the async dma engines 553 * 554 * @adev: amdgpu_device pointer 555 * 556 * Set up the gfx DMA ring buffers and enable them (NAVI10). 557 * Returns 0 for success, error for failure. 558 */ 559 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) 560 { 561 struct amdgpu_ring *ring; 562 u32 rb_cntl, ib_cntl; 563 u32 rb_bufsz; 564 u32 wb_offset; 565 u32 doorbell; 566 u32 doorbell_offset; 567 u32 temp; 568 u32 wptr_poll_cntl; 569 u64 wptr_gpu_addr; 570 int i, r; 571 572 for (i = 0; i < adev->sdma.num_instances; i++) { 573 ring = &adev->sdma.instance[i].ring; 574 wb_offset = (ring->rptr_offs * 4); 575 576 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 577 578 /* Set ring buffer size in dwords */ 579 rb_bufsz = order_base_2(ring->ring_size / 4); 580 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 581 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 582 #ifdef __BIG_ENDIAN 583 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 584 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 585 RPTR_WRITEBACK_SWAP_ENABLE, 1); 586 #endif 587 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 588 589 /* Initialize the ring buffer's read and write pointers */ 590 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 591 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 592 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 593 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 594 595 /* setup the wptr shadow polling */ 596 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 597 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 598 lower_32_bits(wptr_gpu_addr)); 599 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 600 upper_32_bits(wptr_gpu_addr)); 601 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, 602 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 603 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 604 SDMA0_GFX_RB_WPTR_POLL_CNTL, 605 F32_POLL_ENABLE, 1); 606 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 607 wptr_poll_cntl); 608 609 /* set the wb address whether it's enabled or not */ 610 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 611 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 612 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 613 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 614 615 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 616 617 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 618 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 619 620 ring->wptr = 0; 621 622 /* before programing wptr to a less value, need set minor_ptr_update first */ 623 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 624 625 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 626 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 627 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 628 } 629 630 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 631 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 632 633 if (ring->use_doorbell) { 634 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 635 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 636 OFFSET, ring->doorbell_index); 637 } else { 638 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 639 } 640 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 641 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 642 643 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 644 ring->doorbell_index, 20); 645 646 if (amdgpu_sriov_vf(adev)) 647 sdma_v5_0_ring_set_wptr(ring); 648 649 /* set minor_ptr_update to 0 after wptr programed */ 650 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 651 652 /* set utc l1 enable flag always to 1 */ 653 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 654 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 655 656 /* enable MCBP */ 657 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 658 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 659 660 /* Set up RESP_MODE to non-copy addresses */ 661 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 662 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 663 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 664 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 665 666 /* program default cache read and write policy */ 667 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 668 /* clean read policy and write policy bits */ 669 temp &= 0xFF0FFF; 670 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 671 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 672 673 if (!amdgpu_sriov_vf(adev)) { 674 /* unhalt engine */ 675 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 676 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 677 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 678 } 679 680 /* enable DMA RB */ 681 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 682 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 683 684 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 685 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 686 #ifdef __BIG_ENDIAN 687 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 688 #endif 689 /* enable DMA IBs */ 690 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 691 692 ring->sched.ready = true; 693 694 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 695 sdma_v5_0_ctx_switch_enable(adev, true); 696 sdma_v5_0_enable(adev, true); 697 } 698 699 r = amdgpu_ring_test_ring(ring); 700 if (r) { 701 ring->sched.ready = false; 702 return r; 703 } 704 705 if (adev->mman.buffer_funcs_ring == ring) 706 amdgpu_ttm_set_buffer_funcs_status(adev, true); 707 } 708 709 return 0; 710 } 711 712 /** 713 * sdma_v5_0_rlc_resume - setup and start the async dma engines 714 * 715 * @adev: amdgpu_device pointer 716 * 717 * Set up the compute DMA queues and enable them (NAVI10). 718 * Returns 0 for success, error for failure. 719 */ 720 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev) 721 { 722 return 0; 723 } 724 725 /** 726 * sdma_v5_0_load_microcode - load the sDMA ME ucode 727 * 728 * @adev: amdgpu_device pointer 729 * 730 * Loads the sDMA0/1 ucode. 731 * Returns 0 for success, -EINVAL if the ucode is not available. 732 */ 733 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev) 734 { 735 const struct sdma_firmware_header_v1_0 *hdr; 736 const __le32 *fw_data; 737 u32 fw_size; 738 int i, j; 739 740 /* halt the MEs */ 741 sdma_v5_0_enable(adev, false); 742 743 for (i = 0; i < adev->sdma.num_instances; i++) { 744 if (!adev->sdma.instance[i].fw) 745 return -EINVAL; 746 747 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 748 amdgpu_ucode_print_sdma_hdr(&hdr->header); 749 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 750 751 fw_data = (const __le32 *) 752 (adev->sdma.instance[i].fw->data + 753 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 754 755 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 756 757 for (j = 0; j < fw_size; j++) { 758 if (amdgpu_emu_mode == 1 && j % 500 == 0) 759 msleep(1); 760 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 761 } 762 763 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 764 } 765 766 return 0; 767 } 768 769 /** 770 * sdma_v5_0_start - setup and start the async dma engines 771 * 772 * @adev: amdgpu_device pointer 773 * 774 * Set up the DMA engines and enable them (NAVI10). 775 * Returns 0 for success, error for failure. 776 */ 777 static int sdma_v5_0_start(struct amdgpu_device *adev) 778 { 779 int r = 0; 780 781 if (amdgpu_sriov_vf(adev)) { 782 sdma_v5_0_ctx_switch_enable(adev, false); 783 sdma_v5_0_enable(adev, false); 784 785 /* set RB registers */ 786 r = sdma_v5_0_gfx_resume(adev); 787 return r; 788 } 789 790 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 791 r = sdma_v5_0_load_microcode(adev); 792 if (r) 793 return r; 794 795 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 796 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d) 797 msleep(1000); 798 } 799 800 /* unhalt the MEs */ 801 sdma_v5_0_enable(adev, true); 802 /* enable sdma ring preemption */ 803 sdma_v5_0_ctx_switch_enable(adev, true); 804 805 /* start the gfx rings and rlc compute queues */ 806 r = sdma_v5_0_gfx_resume(adev); 807 if (r) 808 return r; 809 r = sdma_v5_0_rlc_resume(adev); 810 811 return r; 812 } 813 814 /** 815 * sdma_v5_0_ring_test_ring - simple async dma engine test 816 * 817 * @ring: amdgpu_ring structure holding ring information 818 * 819 * Test the DMA engine by writing using it to write an 820 * value to memory. (NAVI10). 821 * Returns 0 for success, error for failure. 822 */ 823 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) 824 { 825 struct amdgpu_device *adev = ring->adev; 826 unsigned i; 827 unsigned index; 828 int r; 829 u32 tmp; 830 u64 gpu_addr; 831 832 r = amdgpu_device_wb_get(adev, &index); 833 if (r) { 834 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 835 return r; 836 } 837 838 gpu_addr = adev->wb.gpu_addr + (index * 4); 839 tmp = 0xCAFEDEAD; 840 adev->wb.wb[index] = cpu_to_le32(tmp); 841 842 r = amdgpu_ring_alloc(ring, 5); 843 if (r) { 844 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 845 amdgpu_device_wb_free(adev, index); 846 return r; 847 } 848 849 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 850 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 851 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 852 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 853 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 854 amdgpu_ring_write(ring, 0xDEADBEEF); 855 amdgpu_ring_commit(ring); 856 857 for (i = 0; i < adev->usec_timeout; i++) { 858 tmp = le32_to_cpu(adev->wb.wb[index]); 859 if (tmp == 0xDEADBEEF) 860 break; 861 if (amdgpu_emu_mode == 1) 862 msleep(1); 863 else 864 DRM_UDELAY(1); 865 } 866 867 if (i < adev->usec_timeout) { 868 if (amdgpu_emu_mode == 1) 869 DRM_INFO("ring test on %d succeeded in %d msecs\n", ring->idx, i); 870 else 871 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 872 } else { 873 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 874 ring->idx, tmp); 875 r = -EINVAL; 876 } 877 amdgpu_device_wb_free(adev, index); 878 879 return r; 880 } 881 882 /** 883 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine 884 * 885 * @ring: amdgpu_ring structure holding ring information 886 * 887 * Test a simple IB in the DMA ring (NAVI10). 888 * Returns 0 on success, error on failure. 889 */ 890 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 891 { 892 struct amdgpu_device *adev = ring->adev; 893 struct amdgpu_ib ib; 894 struct dma_fence *f = NULL; 895 unsigned index; 896 long r; 897 u32 tmp = 0; 898 u64 gpu_addr; 899 900 r = amdgpu_device_wb_get(adev, &index); 901 if (r) { 902 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 903 return r; 904 } 905 906 gpu_addr = adev->wb.gpu_addr + (index * 4); 907 tmp = 0xCAFEDEAD; 908 adev->wb.wb[index] = cpu_to_le32(tmp); 909 memset(&ib, 0, sizeof(ib)); 910 r = amdgpu_ib_get(adev, NULL, 256, &ib); 911 if (r) { 912 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 913 goto err0; 914 } 915 916 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 917 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 918 ib.ptr[1] = lower_32_bits(gpu_addr); 919 ib.ptr[2] = upper_32_bits(gpu_addr); 920 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 921 ib.ptr[4] = 0xDEADBEEF; 922 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 923 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 924 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 925 ib.length_dw = 8; 926 927 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 928 if (r) 929 goto err1; 930 931 r = dma_fence_wait_timeout(f, false, timeout); 932 if (r == 0) { 933 DRM_ERROR("amdgpu: IB test timed out\n"); 934 r = -ETIMEDOUT; 935 goto err1; 936 } else if (r < 0) { 937 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 938 goto err1; 939 } 940 tmp = le32_to_cpu(adev->wb.wb[index]); 941 if (tmp == 0xDEADBEEF) { 942 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 943 r = 0; 944 } else { 945 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 946 r = -EINVAL; 947 } 948 949 err1: 950 amdgpu_ib_free(adev, &ib, NULL); 951 dma_fence_put(f); 952 err0: 953 amdgpu_device_wb_free(adev, index); 954 return r; 955 } 956 957 958 /** 959 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART 960 * 961 * @ib: indirect buffer to fill with commands 962 * @pe: addr of the page entry 963 * @src: src addr to copy from 964 * @count: number of page entries to update 965 * 966 * Update PTEs by copying them from the GART using sDMA (NAVI10). 967 */ 968 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib, 969 uint64_t pe, uint64_t src, 970 unsigned count) 971 { 972 unsigned bytes = count * 8; 973 974 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 975 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 976 ib->ptr[ib->length_dw++] = bytes - 1; 977 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 978 ib->ptr[ib->length_dw++] = lower_32_bits(src); 979 ib->ptr[ib->length_dw++] = upper_32_bits(src); 980 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 981 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 982 983 } 984 985 /** 986 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually 987 * 988 * @ib: indirect buffer to fill with commands 989 * @pe: addr of the page entry 990 * @addr: dst addr to write into pe 991 * @count: number of page entries to update 992 * @incr: increase next addr by incr bytes 993 * @flags: access flags 994 * 995 * Update PTEs by writing them manually using sDMA (NAVI10). 996 */ 997 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 998 uint64_t value, unsigned count, 999 uint32_t incr) 1000 { 1001 unsigned ndw = count * 2; 1002 1003 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1004 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1005 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1006 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1007 ib->ptr[ib->length_dw++] = ndw - 1; 1008 for (; ndw > 0; ndw -= 2) { 1009 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1010 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1011 value += incr; 1012 } 1013 } 1014 1015 /** 1016 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA 1017 * 1018 * @ib: indirect buffer to fill with commands 1019 * @pe: addr of the page entry 1020 * @addr: dst addr to write into pe 1021 * @count: number of page entries to update 1022 * @incr: increase next addr by incr bytes 1023 * @flags: access flags 1024 * 1025 * Update the page tables using sDMA (NAVI10). 1026 */ 1027 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1028 uint64_t pe, 1029 uint64_t addr, unsigned count, 1030 uint32_t incr, uint64_t flags) 1031 { 1032 /* for physically contiguous pages (vram) */ 1033 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1034 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1035 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1036 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1037 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1038 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1039 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1040 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1041 ib->ptr[ib->length_dw++] = 0; 1042 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1043 } 1044 1045 /** 1046 * sdma_v5_0_ring_pad_ib - pad the IB to the required number of dw 1047 * 1048 * @ib: indirect buffer to fill with padding 1049 * 1050 */ 1051 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1052 { 1053 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1054 u32 pad_count; 1055 int i; 1056 1057 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1058 for (i = 0; i < pad_count; i++) 1059 if (sdma && sdma->burst_nop && (i == 0)) 1060 ib->ptr[ib->length_dw++] = 1061 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1062 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1063 else 1064 ib->ptr[ib->length_dw++] = 1065 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1066 } 1067 1068 1069 /** 1070 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline 1071 * 1072 * @ring: amdgpu_ring pointer 1073 * 1074 * Make sure all previous operations are completed (CIK). 1075 */ 1076 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1077 { 1078 uint32_t seq = ring->fence_drv.sync_seq; 1079 uint64_t addr = ring->fence_drv.gpu_addr; 1080 1081 /* wait for idle */ 1082 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1083 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1084 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1085 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1086 amdgpu_ring_write(ring, addr & 0xfffffffc); 1087 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1088 amdgpu_ring_write(ring, seq); /* reference */ 1089 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 1090 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1091 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1092 } 1093 1094 1095 /** 1096 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA 1097 * 1098 * @ring: amdgpu_ring pointer 1099 * @vm: amdgpu_vm pointer 1100 * 1101 * Update the page table base and flush the VM TLB 1102 * using sDMA (NAVI10). 1103 */ 1104 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1105 unsigned vmid, uint64_t pd_addr) 1106 { 1107 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1108 } 1109 1110 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring, 1111 uint32_t reg, uint32_t val) 1112 { 1113 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1114 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1115 amdgpu_ring_write(ring, reg); 1116 amdgpu_ring_write(ring, val); 1117 } 1118 1119 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1120 uint32_t val, uint32_t mask) 1121 { 1122 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1123 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1124 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1125 amdgpu_ring_write(ring, reg << 2); 1126 amdgpu_ring_write(ring, 0); 1127 amdgpu_ring_write(ring, val); /* reference */ 1128 amdgpu_ring_write(ring, mask); /* mask */ 1129 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1130 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1131 } 1132 1133 static int sdma_v5_0_early_init(void *handle) 1134 { 1135 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1136 1137 adev->sdma.num_instances = 2; 1138 1139 sdma_v5_0_set_ring_funcs(adev); 1140 sdma_v5_0_set_buffer_funcs(adev); 1141 sdma_v5_0_set_vm_pte_funcs(adev); 1142 sdma_v5_0_set_irq_funcs(adev); 1143 1144 return 0; 1145 } 1146 1147 1148 static int sdma_v5_0_sw_init(void *handle) 1149 { 1150 struct amdgpu_ring *ring; 1151 int r, i; 1152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1153 1154 /* SDMA trap event */ 1155 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 1156 SDMA0_5_0__SRCID__SDMA_TRAP, 1157 &adev->sdma.trap_irq); 1158 if (r) 1159 return r; 1160 1161 /* SDMA trap event */ 1162 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 1163 SDMA1_5_0__SRCID__SDMA_TRAP, 1164 &adev->sdma.trap_irq); 1165 if (r) 1166 return r; 1167 1168 r = sdma_v5_0_init_microcode(adev); 1169 if (r) { 1170 DRM_ERROR("Failed to load sdma firmware!\n"); 1171 return r; 1172 } 1173 1174 for (i = 0; i < adev->sdma.num_instances; i++) { 1175 ring = &adev->sdma.instance[i].ring; 1176 ring->ring_obj = NULL; 1177 ring->use_doorbell = true; 1178 1179 DRM_INFO("use_doorbell being set to: [%s]\n", 1180 ring->use_doorbell?"true":"false"); 1181 1182 ring->doorbell_index = (i == 0) ? 1183 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset 1184 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset 1185 1186 sprintf(ring->name, "sdma%d", i); 1187 r = amdgpu_ring_init(adev, ring, 1024, 1188 &adev->sdma.trap_irq, 1189 (i == 0) ? 1190 AMDGPU_SDMA_IRQ_INSTANCE0 : 1191 AMDGPU_SDMA_IRQ_INSTANCE1); 1192 if (r) 1193 return r; 1194 } 1195 1196 return r; 1197 } 1198 1199 static int sdma_v5_0_sw_fini(void *handle) 1200 { 1201 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1202 int i; 1203 1204 for (i = 0; i < adev->sdma.num_instances; i++) 1205 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1206 1207 return 0; 1208 } 1209 1210 static int sdma_v5_0_hw_init(void *handle) 1211 { 1212 int r; 1213 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1214 1215 sdma_v5_0_init_golden_registers(adev); 1216 1217 r = sdma_v5_0_start(adev); 1218 1219 return r; 1220 } 1221 1222 static int sdma_v5_0_hw_fini(void *handle) 1223 { 1224 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1225 1226 if (amdgpu_sriov_vf(adev)) 1227 return 0; 1228 1229 sdma_v5_0_ctx_switch_enable(adev, false); 1230 sdma_v5_0_enable(adev, false); 1231 1232 return 0; 1233 } 1234 1235 static int sdma_v5_0_suspend(void *handle) 1236 { 1237 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1238 1239 return sdma_v5_0_hw_fini(adev); 1240 } 1241 1242 static int sdma_v5_0_resume(void *handle) 1243 { 1244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1245 1246 return sdma_v5_0_hw_init(adev); 1247 } 1248 1249 static bool sdma_v5_0_is_idle(void *handle) 1250 { 1251 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1252 u32 i; 1253 1254 for (i = 0; i < adev->sdma.num_instances; i++) { 1255 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1256 1257 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1258 return false; 1259 } 1260 1261 return true; 1262 } 1263 1264 static int sdma_v5_0_wait_for_idle(void *handle) 1265 { 1266 unsigned i; 1267 u32 sdma0, sdma1; 1268 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1269 1270 for (i = 0; i < adev->usec_timeout; i++) { 1271 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1272 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1273 1274 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1275 return 0; 1276 udelay(1); 1277 } 1278 return -ETIMEDOUT; 1279 } 1280 1281 static int sdma_v5_0_soft_reset(void *handle) 1282 { 1283 /* todo */ 1284 1285 return 0; 1286 } 1287 1288 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring) 1289 { 1290 int i, r = 0; 1291 struct amdgpu_device *adev = ring->adev; 1292 u32 index = 0; 1293 u64 sdma_gfx_preempt; 1294 1295 amdgpu_sdma_get_index_from_ring(ring, &index); 1296 if (index == 0) 1297 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT; 1298 else 1299 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT; 1300 1301 /* assert preemption condition */ 1302 amdgpu_ring_set_preempt_cond_exec(ring, false); 1303 1304 /* emit the trailing fence */ 1305 ring->trail_seq += 1; 1306 amdgpu_ring_alloc(ring, 10); 1307 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1308 ring->trail_seq, 0); 1309 amdgpu_ring_commit(ring); 1310 1311 /* assert IB preemption */ 1312 WREG32(sdma_gfx_preempt, 1); 1313 1314 /* poll the trailing fence */ 1315 for (i = 0; i < adev->usec_timeout; i++) { 1316 if (ring->trail_seq == 1317 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1318 break; 1319 DRM_UDELAY(1); 1320 } 1321 1322 if (i >= adev->usec_timeout) { 1323 r = -EINVAL; 1324 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1325 } 1326 1327 /* deassert IB preemption */ 1328 WREG32(sdma_gfx_preempt, 0); 1329 1330 /* deassert the preemption condition */ 1331 amdgpu_ring_set_preempt_cond_exec(ring, true); 1332 return r; 1333 } 1334 1335 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev, 1336 struct amdgpu_irq_src *source, 1337 unsigned type, 1338 enum amdgpu_interrupt_state state) 1339 { 1340 u32 sdma_cntl; 1341 1342 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? 1343 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1344 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1345 1346 sdma_cntl = RREG32(reg_offset); 1347 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1348 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1349 WREG32(reg_offset, sdma_cntl); 1350 1351 return 0; 1352 } 1353 1354 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, 1355 struct amdgpu_irq_src *source, 1356 struct amdgpu_iv_entry *entry) 1357 { 1358 DRM_DEBUG("IH: SDMA trap\n"); 1359 switch (entry->client_id) { 1360 case SOC15_IH_CLIENTID_SDMA0: 1361 switch (entry->ring_id) { 1362 case 0: 1363 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1364 break; 1365 case 1: 1366 /* XXX compute */ 1367 break; 1368 case 2: 1369 /* XXX compute */ 1370 break; 1371 case 3: 1372 /* XXX page queue*/ 1373 break; 1374 } 1375 break; 1376 case SOC15_IH_CLIENTID_SDMA1: 1377 switch (entry->ring_id) { 1378 case 0: 1379 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1380 break; 1381 case 1: 1382 /* XXX compute */ 1383 break; 1384 case 2: 1385 /* XXX compute */ 1386 break; 1387 case 3: 1388 /* XXX page queue*/ 1389 break; 1390 } 1391 break; 1392 } 1393 return 0; 1394 } 1395 1396 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1397 struct amdgpu_irq_src *source, 1398 struct amdgpu_iv_entry *entry) 1399 { 1400 return 0; 1401 } 1402 1403 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1404 bool enable) 1405 { 1406 uint32_t data, def; 1407 int i; 1408 1409 for (i = 0; i < adev->sdma.num_instances; i++) { 1410 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1411 /* Enable sdma clock gating */ 1412 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1413 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1414 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1415 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1416 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1417 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1418 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1419 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1420 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1421 if (def != data) 1422 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1423 } else { 1424 /* Disable sdma clock gating */ 1425 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1426 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1427 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1428 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1429 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1430 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1431 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1432 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1433 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1434 if (def != data) 1435 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1436 } 1437 } 1438 } 1439 1440 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1441 bool enable) 1442 { 1443 uint32_t data, def; 1444 int i; 1445 1446 for (i = 0; i < adev->sdma.num_instances; i++) { 1447 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1448 /* Enable sdma mem light sleep */ 1449 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1450 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1451 if (def != data) 1452 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1453 1454 } else { 1455 /* Disable sdma mem light sleep */ 1456 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1457 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1458 if (def != data) 1459 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1460 1461 } 1462 } 1463 } 1464 1465 static int sdma_v5_0_set_clockgating_state(void *handle, 1466 enum amd_clockgating_state state) 1467 { 1468 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1469 1470 if (amdgpu_sriov_vf(adev)) 1471 return 0; 1472 1473 switch (adev->asic_type) { 1474 case CHIP_NAVI10: 1475 sdma_v5_0_update_medium_grain_clock_gating(adev, 1476 state == AMD_CG_STATE_GATE ? true : false); 1477 sdma_v5_0_update_medium_grain_light_sleep(adev, 1478 state == AMD_CG_STATE_GATE ? true : false); 1479 break; 1480 default: 1481 break; 1482 } 1483 1484 return 0; 1485 } 1486 1487 static int sdma_v5_0_set_powergating_state(void *handle, 1488 enum amd_powergating_state state) 1489 { 1490 return 0; 1491 } 1492 1493 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags) 1494 { 1495 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1496 int data; 1497 1498 if (amdgpu_sriov_vf(adev)) 1499 *flags = 0; 1500 1501 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1502 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1503 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1504 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1505 1506 /* AMD_CG_SUPPORT_SDMA_LS */ 1507 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1508 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1509 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1510 } 1511 1512 const struct amd_ip_funcs sdma_v5_0_ip_funcs = { 1513 .name = "sdma_v5_0", 1514 .early_init = sdma_v5_0_early_init, 1515 .late_init = NULL, 1516 .sw_init = sdma_v5_0_sw_init, 1517 .sw_fini = sdma_v5_0_sw_fini, 1518 .hw_init = sdma_v5_0_hw_init, 1519 .hw_fini = sdma_v5_0_hw_fini, 1520 .suspend = sdma_v5_0_suspend, 1521 .resume = sdma_v5_0_resume, 1522 .is_idle = sdma_v5_0_is_idle, 1523 .wait_for_idle = sdma_v5_0_wait_for_idle, 1524 .soft_reset = sdma_v5_0_soft_reset, 1525 .set_clockgating_state = sdma_v5_0_set_clockgating_state, 1526 .set_powergating_state = sdma_v5_0_set_powergating_state, 1527 .get_clockgating_state = sdma_v5_0_get_clockgating_state, 1528 }; 1529 1530 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 1531 .type = AMDGPU_RING_TYPE_SDMA, 1532 .align_mask = 0xf, 1533 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1534 .support_64bit_ptrs = true, 1535 .vmhub = AMDGPU_GFXHUB, 1536 .get_rptr = sdma_v5_0_ring_get_rptr, 1537 .get_wptr = sdma_v5_0_ring_get_wptr, 1538 .set_wptr = sdma_v5_0_ring_set_wptr, 1539 .emit_frame_size = 1540 5 + /* sdma_v5_0_ring_init_cond_exec */ 1541 6 + /* sdma_v5_0_ring_emit_hdp_flush */ 1542 3 + /* hdp_invalidate */ 1543 6 + /* sdma_v5_0_ring_emit_pipeline_sync */ 1544 /* sdma_v5_0_ring_emit_vm_flush */ 1545 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1546 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1547 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ 1548 .emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */ 1549 .emit_ib = sdma_v5_0_ring_emit_ib, 1550 .emit_fence = sdma_v5_0_ring_emit_fence, 1551 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync, 1552 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush, 1553 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush, 1554 .test_ring = sdma_v5_0_ring_test_ring, 1555 .test_ib = sdma_v5_0_ring_test_ib, 1556 .insert_nop = sdma_v5_0_ring_insert_nop, 1557 .pad_ib = sdma_v5_0_ring_pad_ib, 1558 .emit_wreg = sdma_v5_0_ring_emit_wreg, 1559 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait, 1560 .init_cond_exec = sdma_v5_0_ring_init_cond_exec, 1561 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec, 1562 .preempt_ib = sdma_v5_0_ring_preempt_ib, 1563 }; 1564 1565 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) 1566 { 1567 int i; 1568 1569 for (i = 0; i < adev->sdma.num_instances; i++) { 1570 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; 1571 adev->sdma.instance[i].ring.me = i; 1572 } 1573 } 1574 1575 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = { 1576 .set = sdma_v5_0_set_trap_irq_state, 1577 .process = sdma_v5_0_process_trap_irq, 1578 }; 1579 1580 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = { 1581 .process = sdma_v5_0_process_illegal_inst_irq, 1582 }; 1583 1584 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev) 1585 { 1586 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1587 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; 1588 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; 1589 } 1590 1591 /** 1592 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine 1593 * 1594 * @ring: amdgpu_ring structure holding ring information 1595 * @src_offset: src GPU address 1596 * @dst_offset: dst GPU address 1597 * @byte_count: number of bytes to xfer 1598 * 1599 * Copy GPU buffers using the DMA engine (NAVI10). 1600 * Used by the amdgpu ttm implementation to move pages if 1601 * registered as the asic copy callback. 1602 */ 1603 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib, 1604 uint64_t src_offset, 1605 uint64_t dst_offset, 1606 uint32_t byte_count) 1607 { 1608 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1609 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1610 ib->ptr[ib->length_dw++] = byte_count - 1; 1611 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1612 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1613 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1614 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1615 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1616 } 1617 1618 /** 1619 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine 1620 * 1621 * @ring: amdgpu_ring structure holding ring information 1622 * @src_data: value to write to buffer 1623 * @dst_offset: dst GPU address 1624 * @byte_count: number of bytes to xfer 1625 * 1626 * Fill GPU buffers using the DMA engine (NAVI10). 1627 */ 1628 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib, 1629 uint32_t src_data, 1630 uint64_t dst_offset, 1631 uint32_t byte_count) 1632 { 1633 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1634 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1635 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1636 ib->ptr[ib->length_dw++] = src_data; 1637 ib->ptr[ib->length_dw++] = byte_count - 1; 1638 } 1639 1640 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { 1641 .copy_max_bytes = 0x400000, 1642 .copy_num_dw = 7, 1643 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer, 1644 1645 .fill_max_bytes = 0x400000, 1646 .fill_num_dw = 5, 1647 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer, 1648 }; 1649 1650 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) 1651 { 1652 if (adev->mman.buffer_funcs == NULL) { 1653 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; 1654 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1655 } 1656 } 1657 1658 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 1659 .copy_pte_num_dw = 7, 1660 .copy_pte = sdma_v5_0_vm_copy_pte, 1661 .write_pte = sdma_v5_0_vm_write_pte, 1662 .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 1663 }; 1664 1665 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1666 { 1667 struct drm_gpu_scheduler *sched; 1668 unsigned i; 1669 1670 if (adev->vm_manager.vm_pte_funcs == NULL) { 1671 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; 1672 for (i = 0; i < adev->sdma.num_instances; i++) { 1673 sched = &adev->sdma.instance[i].ring.sched; 1674 adev->vm_manager.vm_pte_rqs[i] = 1675 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 1676 } 1677 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 1678 } 1679 } 1680 1681 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { 1682 .type = AMD_IP_BLOCK_TYPE_SDMA, 1683 .major = 5, 1684 .minor = 0, 1685 .rev = 0, 1686 .funcs = &sdma_v5_0_ip_funcs, 1687 }; 1688