1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_1_0_offset.h" 34 #include "gc/gc_10_1_0_sh_mask.h" 35 #include "hdp/hdp_5_0_0_offset.h" 36 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 37 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "navi10_sdma_pkt_open.h" 42 #include "nbio_v2_3.h" 43 #include "sdma_v5_0.h" 44 45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); 47 48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); 50 51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin"); 53 54 #define SDMA1_REG_OFFSET 0x600 55 #define SDMA0_HYP_DEC_REG_START 0x5880 56 #define SDMA0_HYP_DEC_REG_END 0x5893 57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 58 59 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); 60 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); 61 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); 62 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); 63 64 static const struct soc15_reg_golden golden_settings_sdma_5[] = { 65 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00), 77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00) 89 }; 90 91 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { 92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 94 }; 95 96 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = { 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 99 }; 100 101 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = { 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 104 }; 105 106 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 107 { 108 u32 base; 109 110 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 111 internal_offset <= SDMA0_HYP_DEC_REG_END) { 112 base = adev->reg_offset[GC_HWIP][0][1]; 113 if (instance == 1) 114 internal_offset += SDMA1_HYP_DEC_REG_OFFSET; 115 } else { 116 base = adev->reg_offset[GC_HWIP][0][0]; 117 if (instance == 1) 118 internal_offset += SDMA1_REG_OFFSET; 119 } 120 121 return base + internal_offset; 122 } 123 124 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) 125 { 126 switch (adev->asic_type) { 127 case CHIP_NAVI10: 128 soc15_program_register_sequence(adev, 129 golden_settings_sdma_5, 130 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 131 soc15_program_register_sequence(adev, 132 golden_settings_sdma_nv10, 133 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); 134 break; 135 case CHIP_NAVI14: 136 soc15_program_register_sequence(adev, 137 golden_settings_sdma_5, 138 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 139 soc15_program_register_sequence(adev, 140 golden_settings_sdma_nv14, 141 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14)); 142 break; 143 case CHIP_NAVI12: 144 soc15_program_register_sequence(adev, 145 golden_settings_sdma_5, 146 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 147 soc15_program_register_sequence(adev, 148 golden_settings_sdma_nv12, 149 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12)); 150 break; 151 default: 152 break; 153 } 154 } 155 156 /** 157 * sdma_v5_0_init_microcode - load ucode images from disk 158 * 159 * @adev: amdgpu_device pointer 160 * 161 * Use the firmware interface to load the ucode images into 162 * the driver (not loaded into hw). 163 * Returns 0 on success, error on failure. 164 */ 165 166 // emulation only, won't work on real chip 167 // navi10 real chip need to use PSP to load firmware 168 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) 169 { 170 const char *chip_name; 171 char fw_name[30]; 172 int err = 0, i; 173 struct amdgpu_firmware_info *info = NULL; 174 const struct common_firmware_header *header = NULL; 175 const struct sdma_firmware_header_v1_0 *hdr; 176 177 DRM_DEBUG("\n"); 178 179 switch (adev->asic_type) { 180 case CHIP_NAVI10: 181 chip_name = "navi10"; 182 break; 183 case CHIP_NAVI14: 184 chip_name = "navi14"; 185 break; 186 case CHIP_NAVI12: 187 chip_name = "navi12"; 188 break; 189 default: 190 BUG(); 191 } 192 193 for (i = 0; i < adev->sdma.num_instances; i++) { 194 if (i == 0) 195 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 196 else 197 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 198 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 199 if (err) 200 goto out; 201 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 202 if (err) 203 goto out; 204 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 205 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 206 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 207 if (adev->sdma.instance[i].feature_version >= 20) 208 adev->sdma.instance[i].burst_nop = true; 209 DRM_DEBUG("psp_load == '%s'\n", 210 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 211 212 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 213 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 214 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 215 info->fw = adev->sdma.instance[i].fw; 216 header = (const struct common_firmware_header *)info->fw->data; 217 adev->firmware.fw_size += 218 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 219 } 220 } 221 out: 222 if (err) { 223 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name); 224 for (i = 0; i < adev->sdma.num_instances; i++) { 225 release_firmware(adev->sdma.instance[i].fw); 226 adev->sdma.instance[i].fw = NULL; 227 } 228 } 229 return err; 230 } 231 232 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring) 233 { 234 unsigned ret; 235 236 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 237 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 238 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 239 amdgpu_ring_write(ring, 1); 240 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 241 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 242 243 return ret; 244 } 245 246 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 247 unsigned offset) 248 { 249 unsigned cur; 250 251 BUG_ON(offset > ring->buf_mask); 252 BUG_ON(ring->ring[offset] != 0x55aa55aa); 253 254 cur = (ring->wptr - 1) & ring->buf_mask; 255 if (cur > offset) 256 ring->ring[offset] = cur - offset; 257 else 258 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 259 } 260 261 /** 262 * sdma_v5_0_ring_get_rptr - get the current read pointer 263 * 264 * @ring: amdgpu ring pointer 265 * 266 * Get the current rptr from the hardware (NAVI10+). 267 */ 268 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 269 { 270 u64 *rptr; 271 272 /* XXX check if swapping is necessary on BE */ 273 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 274 275 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 276 return ((*rptr) >> 2); 277 } 278 279 /** 280 * sdma_v5_0_ring_get_wptr - get the current write pointer 281 * 282 * @ring: amdgpu ring pointer 283 * 284 * Get the current wptr from the hardware (NAVI10+). 285 */ 286 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 287 { 288 struct amdgpu_device *adev = ring->adev; 289 u64 *wptr = NULL; 290 uint64_t local_wptr = 0; 291 292 if (ring->use_doorbell) { 293 /* XXX check if swapping is necessary on BE */ 294 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); 295 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); 296 *wptr = (*wptr) >> 2; 297 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); 298 } else { 299 u32 lowbit, highbit; 300 301 wptr = &local_wptr; 302 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2; 303 highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 304 305 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 306 ring->me, highbit, lowbit); 307 *wptr = highbit; 308 *wptr = (*wptr) << 32; 309 *wptr |= lowbit; 310 } 311 312 return *wptr; 313 } 314 315 /** 316 * sdma_v5_0_ring_set_wptr - commit the write pointer 317 * 318 * @ring: amdgpu ring pointer 319 * 320 * Write the wptr back to the hardware (NAVI10+). 321 */ 322 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 323 { 324 struct amdgpu_device *adev = ring->adev; 325 326 DRM_DEBUG("Setting write pointer\n"); 327 if (ring->use_doorbell) { 328 DRM_DEBUG("Using doorbell -- " 329 "wptr_offs == 0x%08x " 330 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 331 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 332 ring->wptr_offs, 333 lower_32_bits(ring->wptr << 2), 334 upper_32_bits(ring->wptr << 2)); 335 /* XXX check if swapping is necessary on BE */ 336 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 337 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 338 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 339 ring->doorbell_index, ring->wptr << 2); 340 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 341 } else { 342 DRM_DEBUG("Not using doorbell -- " 343 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 344 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 345 ring->me, 346 lower_32_bits(ring->wptr << 2), 347 ring->me, 348 upper_32_bits(ring->wptr << 2)); 349 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 350 lower_32_bits(ring->wptr << 2)); 351 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 352 upper_32_bits(ring->wptr << 2)); 353 } 354 } 355 356 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 357 { 358 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 359 int i; 360 361 for (i = 0; i < count; i++) 362 if (sdma && sdma->burst_nop && (i == 0)) 363 amdgpu_ring_write(ring, ring->funcs->nop | 364 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 365 else 366 amdgpu_ring_write(ring, ring->funcs->nop); 367 } 368 369 /** 370 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine 371 * 372 * @ring: amdgpu ring pointer 373 * @ib: IB object to schedule 374 * 375 * Schedule an IB in the DMA ring (NAVI10). 376 */ 377 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 378 struct amdgpu_job *job, 379 struct amdgpu_ib *ib, 380 uint32_t flags) 381 { 382 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 383 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 384 385 /* IB packet must end on a 8 DW boundary */ 386 sdma_v5_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 387 388 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 389 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 390 /* base must be 32 byte aligned */ 391 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 392 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 393 amdgpu_ring_write(ring, ib->length_dw); 394 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 395 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 396 } 397 398 /** 399 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 400 * 401 * @ring: amdgpu ring pointer 402 * 403 * Emit an hdp flush packet on the requested DMA ring. 404 */ 405 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 406 { 407 struct amdgpu_device *adev = ring->adev; 408 u32 ref_and_mask = 0; 409 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 410 411 if (ring->me == 0) 412 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 413 else 414 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 415 416 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 417 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 418 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 419 amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2); 420 amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2); 421 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 422 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 423 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 424 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 425 } 426 427 /** 428 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring 429 * 430 * @ring: amdgpu ring pointer 431 * @fence: amdgpu fence object 432 * 433 * Add a DMA fence packet to the ring to write 434 * the fence seq number and DMA trap packet to generate 435 * an interrupt if needed (NAVI10). 436 */ 437 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 438 unsigned flags) 439 { 440 struct amdgpu_device *adev = ring->adev; 441 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 442 /* write the fence */ 443 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 444 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 445 /* zero in first two bits */ 446 BUG_ON(addr & 0x3); 447 amdgpu_ring_write(ring, lower_32_bits(addr)); 448 amdgpu_ring_write(ring, upper_32_bits(addr)); 449 amdgpu_ring_write(ring, lower_32_bits(seq)); 450 451 /* optionally write high bits as well */ 452 if (write64bit) { 453 addr += 4; 454 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 455 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 456 /* zero in first two bits */ 457 BUG_ON(addr & 0x3); 458 amdgpu_ring_write(ring, lower_32_bits(addr)); 459 amdgpu_ring_write(ring, upper_32_bits(addr)); 460 amdgpu_ring_write(ring, upper_32_bits(seq)); 461 } 462 463 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 464 if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) { 465 /* generate an interrupt */ 466 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 467 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 468 } 469 } 470 471 472 /** 473 * sdma_v5_0_gfx_stop - stop the gfx async dma engines 474 * 475 * @adev: amdgpu_device pointer 476 * 477 * Stop the gfx async dma ring buffers (NAVI10). 478 */ 479 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev) 480 { 481 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 482 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 483 u32 rb_cntl, ib_cntl; 484 int i; 485 486 if ((adev->mman.buffer_funcs_ring == sdma0) || 487 (adev->mman.buffer_funcs_ring == sdma1)) 488 amdgpu_ttm_set_buffer_funcs_status(adev, false); 489 490 for (i = 0; i < adev->sdma.num_instances; i++) { 491 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 492 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 493 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 494 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 495 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 496 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 497 } 498 499 sdma0->sched.ready = false; 500 sdma1->sched.ready = false; 501 } 502 503 /** 504 * sdma_v5_0_rlc_stop - stop the compute async dma engines 505 * 506 * @adev: amdgpu_device pointer 507 * 508 * Stop the compute async dma queues (NAVI10). 509 */ 510 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) 511 { 512 /* XXX todo */ 513 } 514 515 /** 516 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 517 * 518 * @adev: amdgpu_device pointer 519 * @enable: enable/disable the DMA MEs context switch. 520 * 521 * Halt or unhalt the async dma engines context switch (NAVI10). 522 */ 523 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 524 { 525 u32 f32_cntl, phase_quantum = 0; 526 int i; 527 528 if (amdgpu_sdma_phase_quantum) { 529 unsigned value = amdgpu_sdma_phase_quantum; 530 unsigned unit = 0; 531 532 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 533 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 534 value = (value + 1) >> 1; 535 unit++; 536 } 537 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 538 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 539 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 540 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 541 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 542 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 543 WARN_ONCE(1, 544 "clamping sdma_phase_quantum to %uK clock cycles\n", 545 value << unit); 546 } 547 phase_quantum = 548 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 549 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 550 } 551 552 for (i = 0; i < adev->sdma.num_instances; i++) { 553 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 554 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 555 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 556 if (enable && amdgpu_sdma_phase_quantum) { 557 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 558 phase_quantum); 559 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 560 phase_quantum); 561 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 562 phase_quantum); 563 } 564 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 565 } 566 567 } 568 569 /** 570 * sdma_v5_0_enable - stop the async dma engines 571 * 572 * @adev: amdgpu_device pointer 573 * @enable: enable/disable the DMA MEs. 574 * 575 * Halt or unhalt the async dma engines (NAVI10). 576 */ 577 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) 578 { 579 u32 f32_cntl; 580 int i; 581 582 if (enable == false) { 583 sdma_v5_0_gfx_stop(adev); 584 sdma_v5_0_rlc_stop(adev); 585 } 586 587 for (i = 0; i < adev->sdma.num_instances; i++) { 588 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 589 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 590 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 591 } 592 } 593 594 /** 595 * sdma_v5_0_gfx_resume - setup and start the async dma engines 596 * 597 * @adev: amdgpu_device pointer 598 * 599 * Set up the gfx DMA ring buffers and enable them (NAVI10). 600 * Returns 0 for success, error for failure. 601 */ 602 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) 603 { 604 struct amdgpu_ring *ring; 605 u32 rb_cntl, ib_cntl; 606 u32 rb_bufsz; 607 u32 wb_offset; 608 u32 doorbell; 609 u32 doorbell_offset; 610 u32 temp; 611 u32 wptr_poll_cntl; 612 u64 wptr_gpu_addr; 613 int i, r; 614 615 for (i = 0; i < adev->sdma.num_instances; i++) { 616 ring = &adev->sdma.instance[i].ring; 617 wb_offset = (ring->rptr_offs * 4); 618 619 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 620 621 /* Set ring buffer size in dwords */ 622 rb_bufsz = order_base_2(ring->ring_size / 4); 623 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 624 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 625 #ifdef __BIG_ENDIAN 626 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 627 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 628 RPTR_WRITEBACK_SWAP_ENABLE, 1); 629 #endif 630 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 631 632 /* Initialize the ring buffer's read and write pointers */ 633 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 634 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 635 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 636 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 637 638 /* setup the wptr shadow polling */ 639 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 640 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 641 lower_32_bits(wptr_gpu_addr)); 642 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 643 upper_32_bits(wptr_gpu_addr)); 644 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, 645 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 646 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 647 SDMA0_GFX_RB_WPTR_POLL_CNTL, 648 F32_POLL_ENABLE, 1); 649 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 650 wptr_poll_cntl); 651 652 /* set the wb address whether it's enabled or not */ 653 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 654 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 655 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 656 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 657 658 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 659 660 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 661 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 662 663 ring->wptr = 0; 664 665 /* before programing wptr to a less value, need set minor_ptr_update first */ 666 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 667 668 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 669 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 670 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 671 } 672 673 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 674 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 675 676 if (ring->use_doorbell) { 677 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 678 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 679 OFFSET, ring->doorbell_index); 680 } else { 681 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 682 } 683 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 684 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 685 686 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 687 ring->doorbell_index, 20); 688 689 if (amdgpu_sriov_vf(adev)) 690 sdma_v5_0_ring_set_wptr(ring); 691 692 /* set minor_ptr_update to 0 after wptr programed */ 693 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 694 695 /* set utc l1 enable flag always to 1 */ 696 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 697 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 698 699 /* enable MCBP */ 700 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 701 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 702 703 /* Set up RESP_MODE to non-copy addresses */ 704 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 705 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 706 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 707 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 708 709 /* program default cache read and write policy */ 710 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 711 /* clean read policy and write policy bits */ 712 temp &= 0xFF0FFF; 713 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 714 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 715 716 if (!amdgpu_sriov_vf(adev)) { 717 /* unhalt engine */ 718 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 719 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 720 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 721 } 722 723 /* enable DMA RB */ 724 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 725 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 726 727 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 728 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 729 #ifdef __BIG_ENDIAN 730 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 731 #endif 732 /* enable DMA IBs */ 733 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 734 735 ring->sched.ready = true; 736 737 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 738 sdma_v5_0_ctx_switch_enable(adev, true); 739 sdma_v5_0_enable(adev, true); 740 } 741 742 r = amdgpu_ring_test_ring(ring); 743 if (r) { 744 ring->sched.ready = false; 745 return r; 746 } 747 748 if (adev->mman.buffer_funcs_ring == ring) 749 amdgpu_ttm_set_buffer_funcs_status(adev, true); 750 } 751 752 return 0; 753 } 754 755 /** 756 * sdma_v5_0_rlc_resume - setup and start the async dma engines 757 * 758 * @adev: amdgpu_device pointer 759 * 760 * Set up the compute DMA queues and enable them (NAVI10). 761 * Returns 0 for success, error for failure. 762 */ 763 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev) 764 { 765 return 0; 766 } 767 768 /** 769 * sdma_v5_0_load_microcode - load the sDMA ME ucode 770 * 771 * @adev: amdgpu_device pointer 772 * 773 * Loads the sDMA0/1 ucode. 774 * Returns 0 for success, -EINVAL if the ucode is not available. 775 */ 776 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev) 777 { 778 const struct sdma_firmware_header_v1_0 *hdr; 779 const __le32 *fw_data; 780 u32 fw_size; 781 int i, j; 782 783 /* halt the MEs */ 784 sdma_v5_0_enable(adev, false); 785 786 for (i = 0; i < adev->sdma.num_instances; i++) { 787 if (!adev->sdma.instance[i].fw) 788 return -EINVAL; 789 790 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 791 amdgpu_ucode_print_sdma_hdr(&hdr->header); 792 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 793 794 fw_data = (const __le32 *) 795 (adev->sdma.instance[i].fw->data + 796 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 797 798 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 799 800 for (j = 0; j < fw_size; j++) { 801 if (amdgpu_emu_mode == 1 && j % 500 == 0) 802 msleep(1); 803 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 804 } 805 806 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 807 } 808 809 return 0; 810 } 811 812 /** 813 * sdma_v5_0_start - setup and start the async dma engines 814 * 815 * @adev: amdgpu_device pointer 816 * 817 * Set up the DMA engines and enable them (NAVI10). 818 * Returns 0 for success, error for failure. 819 */ 820 static int sdma_v5_0_start(struct amdgpu_device *adev) 821 { 822 int r = 0; 823 824 if (amdgpu_sriov_vf(adev)) { 825 sdma_v5_0_ctx_switch_enable(adev, false); 826 sdma_v5_0_enable(adev, false); 827 828 /* set RB registers */ 829 r = sdma_v5_0_gfx_resume(adev); 830 return r; 831 } 832 833 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 834 r = sdma_v5_0_load_microcode(adev); 835 if (r) 836 return r; 837 838 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 839 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d) 840 msleep(1000); 841 } 842 843 /* unhalt the MEs */ 844 sdma_v5_0_enable(adev, true); 845 /* enable sdma ring preemption */ 846 sdma_v5_0_ctx_switch_enable(adev, true); 847 848 /* start the gfx rings and rlc compute queues */ 849 r = sdma_v5_0_gfx_resume(adev); 850 if (r) 851 return r; 852 r = sdma_v5_0_rlc_resume(adev); 853 854 return r; 855 } 856 857 /** 858 * sdma_v5_0_ring_test_ring - simple async dma engine test 859 * 860 * @ring: amdgpu_ring structure holding ring information 861 * 862 * Test the DMA engine by writing using it to write an 863 * value to memory. (NAVI10). 864 * Returns 0 for success, error for failure. 865 */ 866 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) 867 { 868 struct amdgpu_device *adev = ring->adev; 869 unsigned i; 870 unsigned index; 871 int r; 872 u32 tmp; 873 u64 gpu_addr; 874 875 r = amdgpu_device_wb_get(adev, &index); 876 if (r) { 877 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 878 return r; 879 } 880 881 gpu_addr = adev->wb.gpu_addr + (index * 4); 882 tmp = 0xCAFEDEAD; 883 adev->wb.wb[index] = cpu_to_le32(tmp); 884 885 r = amdgpu_ring_alloc(ring, 5); 886 if (r) { 887 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 888 amdgpu_device_wb_free(adev, index); 889 return r; 890 } 891 892 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 893 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 894 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 895 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 896 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 897 amdgpu_ring_write(ring, 0xDEADBEEF); 898 amdgpu_ring_commit(ring); 899 900 for (i = 0; i < adev->usec_timeout; i++) { 901 tmp = le32_to_cpu(adev->wb.wb[index]); 902 if (tmp == 0xDEADBEEF) 903 break; 904 if (amdgpu_emu_mode == 1) 905 msleep(1); 906 else 907 udelay(1); 908 } 909 910 if (i < adev->usec_timeout) { 911 if (amdgpu_emu_mode == 1) 912 DRM_INFO("ring test on %d succeeded in %d msecs\n", ring->idx, i); 913 else 914 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 915 } else { 916 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 917 ring->idx, tmp); 918 r = -EINVAL; 919 } 920 amdgpu_device_wb_free(adev, index); 921 922 return r; 923 } 924 925 /** 926 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine 927 * 928 * @ring: amdgpu_ring structure holding ring information 929 * 930 * Test a simple IB in the DMA ring (NAVI10). 931 * Returns 0 on success, error on failure. 932 */ 933 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 934 { 935 struct amdgpu_device *adev = ring->adev; 936 struct amdgpu_ib ib; 937 struct dma_fence *f = NULL; 938 unsigned index; 939 long r; 940 u32 tmp = 0; 941 u64 gpu_addr; 942 943 r = amdgpu_device_wb_get(adev, &index); 944 if (r) { 945 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 946 return r; 947 } 948 949 gpu_addr = adev->wb.gpu_addr + (index * 4); 950 tmp = 0xCAFEDEAD; 951 adev->wb.wb[index] = cpu_to_le32(tmp); 952 memset(&ib, 0, sizeof(ib)); 953 r = amdgpu_ib_get(adev, NULL, 256, &ib); 954 if (r) { 955 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 956 goto err0; 957 } 958 959 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 960 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 961 ib.ptr[1] = lower_32_bits(gpu_addr); 962 ib.ptr[2] = upper_32_bits(gpu_addr); 963 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 964 ib.ptr[4] = 0xDEADBEEF; 965 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 966 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 967 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 968 ib.length_dw = 8; 969 970 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 971 if (r) 972 goto err1; 973 974 r = dma_fence_wait_timeout(f, false, timeout); 975 if (r == 0) { 976 DRM_ERROR("amdgpu: IB test timed out\n"); 977 r = -ETIMEDOUT; 978 goto err1; 979 } else if (r < 0) { 980 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 981 goto err1; 982 } 983 tmp = le32_to_cpu(adev->wb.wb[index]); 984 if (tmp == 0xDEADBEEF) { 985 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 986 r = 0; 987 } else { 988 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 989 r = -EINVAL; 990 } 991 992 err1: 993 amdgpu_ib_free(adev, &ib, NULL); 994 dma_fence_put(f); 995 err0: 996 amdgpu_device_wb_free(adev, index); 997 return r; 998 } 999 1000 1001 /** 1002 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART 1003 * 1004 * @ib: indirect buffer to fill with commands 1005 * @pe: addr of the page entry 1006 * @src: src addr to copy from 1007 * @count: number of page entries to update 1008 * 1009 * Update PTEs by copying them from the GART using sDMA (NAVI10). 1010 */ 1011 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib, 1012 uint64_t pe, uint64_t src, 1013 unsigned count) 1014 { 1015 unsigned bytes = count * 8; 1016 1017 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1018 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1019 ib->ptr[ib->length_dw++] = bytes - 1; 1020 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1021 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1022 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1023 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1024 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1025 1026 } 1027 1028 /** 1029 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually 1030 * 1031 * @ib: indirect buffer to fill with commands 1032 * @pe: addr of the page entry 1033 * @addr: dst addr to write into pe 1034 * @count: number of page entries to update 1035 * @incr: increase next addr by incr bytes 1036 * @flags: access flags 1037 * 1038 * Update PTEs by writing them manually using sDMA (NAVI10). 1039 */ 1040 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1041 uint64_t value, unsigned count, 1042 uint32_t incr) 1043 { 1044 unsigned ndw = count * 2; 1045 1046 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1047 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1048 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1049 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1050 ib->ptr[ib->length_dw++] = ndw - 1; 1051 for (; ndw > 0; ndw -= 2) { 1052 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1053 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1054 value += incr; 1055 } 1056 } 1057 1058 /** 1059 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA 1060 * 1061 * @ib: indirect buffer to fill with commands 1062 * @pe: addr of the page entry 1063 * @addr: dst addr to write into pe 1064 * @count: number of page entries to update 1065 * @incr: increase next addr by incr bytes 1066 * @flags: access flags 1067 * 1068 * Update the page tables using sDMA (NAVI10). 1069 */ 1070 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1071 uint64_t pe, 1072 uint64_t addr, unsigned count, 1073 uint32_t incr, uint64_t flags) 1074 { 1075 /* for physically contiguous pages (vram) */ 1076 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1077 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1078 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1079 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1080 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1081 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1082 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1083 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1084 ib->ptr[ib->length_dw++] = 0; 1085 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1086 } 1087 1088 /** 1089 * sdma_v5_0_ring_pad_ib - pad the IB to the required number of dw 1090 * 1091 * @ib: indirect buffer to fill with padding 1092 * 1093 */ 1094 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1095 { 1096 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1097 u32 pad_count; 1098 int i; 1099 1100 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1101 for (i = 0; i < pad_count; i++) 1102 if (sdma && sdma->burst_nop && (i == 0)) 1103 ib->ptr[ib->length_dw++] = 1104 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1105 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1106 else 1107 ib->ptr[ib->length_dw++] = 1108 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1109 } 1110 1111 1112 /** 1113 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline 1114 * 1115 * @ring: amdgpu_ring pointer 1116 * 1117 * Make sure all previous operations are completed (CIK). 1118 */ 1119 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1120 { 1121 uint32_t seq = ring->fence_drv.sync_seq; 1122 uint64_t addr = ring->fence_drv.gpu_addr; 1123 1124 /* wait for idle */ 1125 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1126 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1127 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1128 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1129 amdgpu_ring_write(ring, addr & 0xfffffffc); 1130 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1131 amdgpu_ring_write(ring, seq); /* reference */ 1132 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 1133 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1134 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1135 } 1136 1137 1138 /** 1139 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA 1140 * 1141 * @ring: amdgpu_ring pointer 1142 * @vm: amdgpu_vm pointer 1143 * 1144 * Update the page table base and flush the VM TLB 1145 * using sDMA (NAVI10). 1146 */ 1147 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1148 unsigned vmid, uint64_t pd_addr) 1149 { 1150 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1151 } 1152 1153 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring, 1154 uint32_t reg, uint32_t val) 1155 { 1156 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1157 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1158 amdgpu_ring_write(ring, reg); 1159 amdgpu_ring_write(ring, val); 1160 } 1161 1162 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1163 uint32_t val, uint32_t mask) 1164 { 1165 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1166 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1167 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1168 amdgpu_ring_write(ring, reg << 2); 1169 amdgpu_ring_write(ring, 0); 1170 amdgpu_ring_write(ring, val); /* reference */ 1171 amdgpu_ring_write(ring, mask); /* mask */ 1172 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1173 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1174 } 1175 1176 static int sdma_v5_0_early_init(void *handle) 1177 { 1178 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1179 1180 adev->sdma.num_instances = 2; 1181 1182 sdma_v5_0_set_ring_funcs(adev); 1183 sdma_v5_0_set_buffer_funcs(adev); 1184 sdma_v5_0_set_vm_pte_funcs(adev); 1185 sdma_v5_0_set_irq_funcs(adev); 1186 1187 return 0; 1188 } 1189 1190 1191 static int sdma_v5_0_sw_init(void *handle) 1192 { 1193 struct amdgpu_ring *ring; 1194 int r, i; 1195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1196 1197 /* SDMA trap event */ 1198 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 1199 SDMA0_5_0__SRCID__SDMA_TRAP, 1200 &adev->sdma.trap_irq); 1201 if (r) 1202 return r; 1203 1204 /* SDMA trap event */ 1205 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 1206 SDMA1_5_0__SRCID__SDMA_TRAP, 1207 &adev->sdma.trap_irq); 1208 if (r) 1209 return r; 1210 1211 r = sdma_v5_0_init_microcode(adev); 1212 if (r) { 1213 DRM_ERROR("Failed to load sdma firmware!\n"); 1214 return r; 1215 } 1216 1217 for (i = 0; i < adev->sdma.num_instances; i++) { 1218 ring = &adev->sdma.instance[i].ring; 1219 ring->ring_obj = NULL; 1220 ring->use_doorbell = true; 1221 1222 DRM_INFO("use_doorbell being set to: [%s]\n", 1223 ring->use_doorbell?"true":"false"); 1224 1225 ring->doorbell_index = (i == 0) ? 1226 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset 1227 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset 1228 1229 sprintf(ring->name, "sdma%d", i); 1230 r = amdgpu_ring_init(adev, ring, 1024, 1231 &adev->sdma.trap_irq, 1232 (i == 0) ? 1233 AMDGPU_SDMA_IRQ_INSTANCE0 : 1234 AMDGPU_SDMA_IRQ_INSTANCE1); 1235 if (r) 1236 return r; 1237 } 1238 1239 return r; 1240 } 1241 1242 static int sdma_v5_0_sw_fini(void *handle) 1243 { 1244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1245 int i; 1246 1247 for (i = 0; i < adev->sdma.num_instances; i++) 1248 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1249 1250 return 0; 1251 } 1252 1253 static int sdma_v5_0_hw_init(void *handle) 1254 { 1255 int r; 1256 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1257 1258 sdma_v5_0_init_golden_registers(adev); 1259 1260 r = sdma_v5_0_start(adev); 1261 1262 return r; 1263 } 1264 1265 static int sdma_v5_0_hw_fini(void *handle) 1266 { 1267 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1268 1269 if (amdgpu_sriov_vf(adev)) 1270 return 0; 1271 1272 sdma_v5_0_ctx_switch_enable(adev, false); 1273 sdma_v5_0_enable(adev, false); 1274 1275 return 0; 1276 } 1277 1278 static int sdma_v5_0_suspend(void *handle) 1279 { 1280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1281 1282 return sdma_v5_0_hw_fini(adev); 1283 } 1284 1285 static int sdma_v5_0_resume(void *handle) 1286 { 1287 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1288 1289 return sdma_v5_0_hw_init(adev); 1290 } 1291 1292 static bool sdma_v5_0_is_idle(void *handle) 1293 { 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1295 u32 i; 1296 1297 for (i = 0; i < adev->sdma.num_instances; i++) { 1298 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1299 1300 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1301 return false; 1302 } 1303 1304 return true; 1305 } 1306 1307 static int sdma_v5_0_wait_for_idle(void *handle) 1308 { 1309 unsigned i; 1310 u32 sdma0, sdma1; 1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1312 1313 for (i = 0; i < adev->usec_timeout; i++) { 1314 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1315 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1316 1317 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1318 return 0; 1319 udelay(1); 1320 } 1321 return -ETIMEDOUT; 1322 } 1323 1324 static int sdma_v5_0_soft_reset(void *handle) 1325 { 1326 /* todo */ 1327 1328 return 0; 1329 } 1330 1331 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring) 1332 { 1333 int i, r = 0; 1334 struct amdgpu_device *adev = ring->adev; 1335 u32 index = 0; 1336 u64 sdma_gfx_preempt; 1337 1338 amdgpu_sdma_get_index_from_ring(ring, &index); 1339 if (index == 0) 1340 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT; 1341 else 1342 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT; 1343 1344 /* assert preemption condition */ 1345 amdgpu_ring_set_preempt_cond_exec(ring, false); 1346 1347 /* emit the trailing fence */ 1348 ring->trail_seq += 1; 1349 amdgpu_ring_alloc(ring, 10); 1350 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1351 ring->trail_seq, 0); 1352 amdgpu_ring_commit(ring); 1353 1354 /* assert IB preemption */ 1355 WREG32(sdma_gfx_preempt, 1); 1356 1357 /* poll the trailing fence */ 1358 for (i = 0; i < adev->usec_timeout; i++) { 1359 if (ring->trail_seq == 1360 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1361 break; 1362 udelay(1); 1363 } 1364 1365 if (i >= adev->usec_timeout) { 1366 r = -EINVAL; 1367 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1368 } 1369 1370 /* deassert IB preemption */ 1371 WREG32(sdma_gfx_preempt, 0); 1372 1373 /* deassert the preemption condition */ 1374 amdgpu_ring_set_preempt_cond_exec(ring, true); 1375 return r; 1376 } 1377 1378 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev, 1379 struct amdgpu_irq_src *source, 1380 unsigned type, 1381 enum amdgpu_interrupt_state state) 1382 { 1383 u32 sdma_cntl; 1384 1385 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? 1386 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1387 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1388 1389 sdma_cntl = RREG32(reg_offset); 1390 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1391 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1392 WREG32(reg_offset, sdma_cntl); 1393 1394 return 0; 1395 } 1396 1397 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, 1398 struct amdgpu_irq_src *source, 1399 struct amdgpu_iv_entry *entry) 1400 { 1401 DRM_DEBUG("IH: SDMA trap\n"); 1402 switch (entry->client_id) { 1403 case SOC15_IH_CLIENTID_SDMA0: 1404 switch (entry->ring_id) { 1405 case 0: 1406 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1407 break; 1408 case 1: 1409 /* XXX compute */ 1410 break; 1411 case 2: 1412 /* XXX compute */ 1413 break; 1414 case 3: 1415 /* XXX page queue*/ 1416 break; 1417 } 1418 break; 1419 case SOC15_IH_CLIENTID_SDMA1: 1420 switch (entry->ring_id) { 1421 case 0: 1422 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1423 break; 1424 case 1: 1425 /* XXX compute */ 1426 break; 1427 case 2: 1428 /* XXX compute */ 1429 break; 1430 case 3: 1431 /* XXX page queue*/ 1432 break; 1433 } 1434 break; 1435 } 1436 return 0; 1437 } 1438 1439 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1440 struct amdgpu_irq_src *source, 1441 struct amdgpu_iv_entry *entry) 1442 { 1443 return 0; 1444 } 1445 1446 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1447 bool enable) 1448 { 1449 uint32_t data, def; 1450 int i; 1451 1452 for (i = 0; i < adev->sdma.num_instances; i++) { 1453 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1454 /* Enable sdma clock gating */ 1455 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1456 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1457 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1458 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1459 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1460 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1461 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1462 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1463 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1464 if (def != data) 1465 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1466 } else { 1467 /* Disable sdma clock gating */ 1468 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1469 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1470 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1471 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1472 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1473 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1474 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1475 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1476 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1477 if (def != data) 1478 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1479 } 1480 } 1481 } 1482 1483 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1484 bool enable) 1485 { 1486 uint32_t data, def; 1487 int i; 1488 1489 for (i = 0; i < adev->sdma.num_instances; i++) { 1490 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1491 /* Enable sdma mem light sleep */ 1492 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1493 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1494 if (def != data) 1495 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1496 1497 } else { 1498 /* Disable sdma mem light sleep */ 1499 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1500 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1501 if (def != data) 1502 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1503 1504 } 1505 } 1506 } 1507 1508 static int sdma_v5_0_set_clockgating_state(void *handle, 1509 enum amd_clockgating_state state) 1510 { 1511 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1512 1513 if (amdgpu_sriov_vf(adev)) 1514 return 0; 1515 1516 switch (adev->asic_type) { 1517 case CHIP_NAVI10: 1518 case CHIP_NAVI14: 1519 case CHIP_NAVI12: 1520 sdma_v5_0_update_medium_grain_clock_gating(adev, 1521 state == AMD_CG_STATE_GATE ? true : false); 1522 sdma_v5_0_update_medium_grain_light_sleep(adev, 1523 state == AMD_CG_STATE_GATE ? true : false); 1524 break; 1525 default: 1526 break; 1527 } 1528 1529 return 0; 1530 } 1531 1532 static int sdma_v5_0_set_powergating_state(void *handle, 1533 enum amd_powergating_state state) 1534 { 1535 return 0; 1536 } 1537 1538 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags) 1539 { 1540 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1541 int data; 1542 1543 if (amdgpu_sriov_vf(adev)) 1544 *flags = 0; 1545 1546 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1547 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1548 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1549 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1550 1551 /* AMD_CG_SUPPORT_SDMA_LS */ 1552 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1553 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1554 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1555 } 1556 1557 const struct amd_ip_funcs sdma_v5_0_ip_funcs = { 1558 .name = "sdma_v5_0", 1559 .early_init = sdma_v5_0_early_init, 1560 .late_init = NULL, 1561 .sw_init = sdma_v5_0_sw_init, 1562 .sw_fini = sdma_v5_0_sw_fini, 1563 .hw_init = sdma_v5_0_hw_init, 1564 .hw_fini = sdma_v5_0_hw_fini, 1565 .suspend = sdma_v5_0_suspend, 1566 .resume = sdma_v5_0_resume, 1567 .is_idle = sdma_v5_0_is_idle, 1568 .wait_for_idle = sdma_v5_0_wait_for_idle, 1569 .soft_reset = sdma_v5_0_soft_reset, 1570 .set_clockgating_state = sdma_v5_0_set_clockgating_state, 1571 .set_powergating_state = sdma_v5_0_set_powergating_state, 1572 .get_clockgating_state = sdma_v5_0_get_clockgating_state, 1573 }; 1574 1575 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 1576 .type = AMDGPU_RING_TYPE_SDMA, 1577 .align_mask = 0xf, 1578 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1579 .support_64bit_ptrs = true, 1580 .vmhub = AMDGPU_GFXHUB_0, 1581 .get_rptr = sdma_v5_0_ring_get_rptr, 1582 .get_wptr = sdma_v5_0_ring_get_wptr, 1583 .set_wptr = sdma_v5_0_ring_set_wptr, 1584 .emit_frame_size = 1585 5 + /* sdma_v5_0_ring_init_cond_exec */ 1586 6 + /* sdma_v5_0_ring_emit_hdp_flush */ 1587 3 + /* hdp_invalidate */ 1588 6 + /* sdma_v5_0_ring_emit_pipeline_sync */ 1589 /* sdma_v5_0_ring_emit_vm_flush */ 1590 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1591 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1592 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ 1593 .emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */ 1594 .emit_ib = sdma_v5_0_ring_emit_ib, 1595 .emit_fence = sdma_v5_0_ring_emit_fence, 1596 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync, 1597 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush, 1598 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush, 1599 .test_ring = sdma_v5_0_ring_test_ring, 1600 .test_ib = sdma_v5_0_ring_test_ib, 1601 .insert_nop = sdma_v5_0_ring_insert_nop, 1602 .pad_ib = sdma_v5_0_ring_pad_ib, 1603 .emit_wreg = sdma_v5_0_ring_emit_wreg, 1604 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait, 1605 .init_cond_exec = sdma_v5_0_ring_init_cond_exec, 1606 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec, 1607 .preempt_ib = sdma_v5_0_ring_preempt_ib, 1608 }; 1609 1610 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) 1611 { 1612 int i; 1613 1614 for (i = 0; i < adev->sdma.num_instances; i++) { 1615 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; 1616 adev->sdma.instance[i].ring.me = i; 1617 } 1618 } 1619 1620 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = { 1621 .set = sdma_v5_0_set_trap_irq_state, 1622 .process = sdma_v5_0_process_trap_irq, 1623 }; 1624 1625 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = { 1626 .process = sdma_v5_0_process_illegal_inst_irq, 1627 }; 1628 1629 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev) 1630 { 1631 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1632 adev->sdma.num_instances; 1633 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; 1634 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; 1635 } 1636 1637 /** 1638 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine 1639 * 1640 * @ring: amdgpu_ring structure holding ring information 1641 * @src_offset: src GPU address 1642 * @dst_offset: dst GPU address 1643 * @byte_count: number of bytes to xfer 1644 * 1645 * Copy GPU buffers using the DMA engine (NAVI10). 1646 * Used by the amdgpu ttm implementation to move pages if 1647 * registered as the asic copy callback. 1648 */ 1649 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib, 1650 uint64_t src_offset, 1651 uint64_t dst_offset, 1652 uint32_t byte_count) 1653 { 1654 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1655 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1656 ib->ptr[ib->length_dw++] = byte_count - 1; 1657 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1658 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1659 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1660 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1661 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1662 } 1663 1664 /** 1665 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine 1666 * 1667 * @ring: amdgpu_ring structure holding ring information 1668 * @src_data: value to write to buffer 1669 * @dst_offset: dst GPU address 1670 * @byte_count: number of bytes to xfer 1671 * 1672 * Fill GPU buffers using the DMA engine (NAVI10). 1673 */ 1674 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib, 1675 uint32_t src_data, 1676 uint64_t dst_offset, 1677 uint32_t byte_count) 1678 { 1679 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1680 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1681 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1682 ib->ptr[ib->length_dw++] = src_data; 1683 ib->ptr[ib->length_dw++] = byte_count - 1; 1684 } 1685 1686 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { 1687 .copy_max_bytes = 0x400000, 1688 .copy_num_dw = 7, 1689 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer, 1690 1691 .fill_max_bytes = 0x400000, 1692 .fill_num_dw = 5, 1693 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer, 1694 }; 1695 1696 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) 1697 { 1698 if (adev->mman.buffer_funcs == NULL) { 1699 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; 1700 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1701 } 1702 } 1703 1704 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 1705 .copy_pte_num_dw = 7, 1706 .copy_pte = sdma_v5_0_vm_copy_pte, 1707 .write_pte = sdma_v5_0_vm_write_pte, 1708 .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 1709 }; 1710 1711 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1712 { 1713 struct drm_gpu_scheduler *sched; 1714 unsigned i; 1715 1716 if (adev->vm_manager.vm_pte_funcs == NULL) { 1717 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; 1718 for (i = 0; i < adev->sdma.num_instances; i++) { 1719 sched = &adev->sdma.instance[i].ring.sched; 1720 adev->vm_manager.vm_pte_rqs[i] = 1721 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 1722 } 1723 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 1724 } 1725 } 1726 1727 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { 1728 .type = AMD_IP_BLOCK_TYPE_SDMA, 1729 .major = 5, 1730 .minor = 0, 1731 .rev = 0, 1732 .funcs = &sdma_v5_0_ip_funcs, 1733 }; 1734