1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_1_0_offset.h" 34 #include "gc/gc_10_1_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "navi10_sdma_pkt_open.h" 41 #include "nbio_v2_3.h" 42 #include "sdma_common.h" 43 #include "sdma_v5_0.h" 44 45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); 47 48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); 50 51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin"); 53 54 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin"); 56 57 #define SDMA1_REG_OFFSET 0x600 58 #define SDMA0_HYP_DEC_REG_START 0x5880 59 #define SDMA0_HYP_DEC_REG_END 0x5893 60 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 61 62 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); 63 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); 64 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); 65 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); 66 67 static const struct soc15_reg_golden golden_settings_sdma_5[] = { 68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00), 80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00) 92 }; 93 94 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = { 95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 115 }; 116 117 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { 118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 120 }; 121 122 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = { 123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 125 }; 126 127 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = { 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 134 }; 135 136 static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = { 137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00) 165 }; 166 167 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 168 { 169 u32 base; 170 171 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 172 internal_offset <= SDMA0_HYP_DEC_REG_END) { 173 base = adev->reg_offset[GC_HWIP][0][1]; 174 if (instance == 1) 175 internal_offset += SDMA1_HYP_DEC_REG_OFFSET; 176 } else { 177 base = adev->reg_offset[GC_HWIP][0][0]; 178 if (instance == 1) 179 internal_offset += SDMA1_REG_OFFSET; 180 } 181 182 return base + internal_offset; 183 } 184 185 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) 186 { 187 switch (adev->ip_versions[SDMA0_HWIP][0]) { 188 case IP_VERSION(5, 0, 0): 189 soc15_program_register_sequence(adev, 190 golden_settings_sdma_5, 191 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 192 soc15_program_register_sequence(adev, 193 golden_settings_sdma_nv10, 194 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); 195 break; 196 case IP_VERSION(5, 0, 2): 197 soc15_program_register_sequence(adev, 198 golden_settings_sdma_5, 199 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 200 soc15_program_register_sequence(adev, 201 golden_settings_sdma_nv14, 202 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14)); 203 break; 204 case IP_VERSION(5, 0, 5): 205 if (amdgpu_sriov_vf(adev)) 206 soc15_program_register_sequence(adev, 207 golden_settings_sdma_5_sriov, 208 (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov)); 209 else 210 soc15_program_register_sequence(adev, 211 golden_settings_sdma_5, 212 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 213 soc15_program_register_sequence(adev, 214 golden_settings_sdma_nv12, 215 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12)); 216 break; 217 case IP_VERSION(5, 0, 1): 218 soc15_program_register_sequence(adev, 219 golden_settings_sdma_cyan_skillfish, 220 (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish)); 221 break; 222 default: 223 break; 224 } 225 } 226 227 /** 228 * sdma_v5_0_init_microcode - load ucode images from disk 229 * 230 * @adev: amdgpu_device pointer 231 * 232 * Use the firmware interface to load the ucode images into 233 * the driver (not loaded into hw). 234 * Returns 0 on success, error on failure. 235 */ 236 237 // emulation only, won't work on real chip 238 // navi10 real chip need to use PSP to load firmware 239 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) 240 { 241 const char *chip_name; 242 char fw_name[40]; 243 int ret, i; 244 245 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5))) 246 return 0; 247 248 DRM_DEBUG("\n"); 249 250 switch (adev->ip_versions[SDMA0_HWIP][0]) { 251 case IP_VERSION(5, 0, 0): 252 chip_name = "navi10"; 253 break; 254 case IP_VERSION(5, 0, 2): 255 chip_name = "navi14"; 256 break; 257 case IP_VERSION(5, 0, 5): 258 chip_name = "navi12"; 259 break; 260 case IP_VERSION(5, 0, 1): 261 chip_name = "cyan_skillfish2"; 262 break; 263 default: 264 BUG(); 265 } 266 267 for (i = 0; i < adev->sdma.num_instances; i++) { 268 if (i == 0) 269 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 270 else 271 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 272 ret = amdgpu_sdma_init_microcode(adev, fw_name, i, false); 273 if (ret) 274 return ret; 275 } 276 277 return ret; 278 } 279 280 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring) 281 { 282 unsigned ret; 283 284 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 285 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 286 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 287 amdgpu_ring_write(ring, 1); 288 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 289 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 290 291 return ret; 292 } 293 294 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 295 unsigned offset) 296 { 297 unsigned cur; 298 299 BUG_ON(offset > ring->buf_mask); 300 BUG_ON(ring->ring[offset] != 0x55aa55aa); 301 302 cur = (ring->wptr - 1) & ring->buf_mask; 303 if (cur > offset) 304 ring->ring[offset] = cur - offset; 305 else 306 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 307 } 308 309 /** 310 * sdma_v5_0_ring_get_rptr - get the current read pointer 311 * 312 * @ring: amdgpu ring pointer 313 * 314 * Get the current rptr from the hardware (NAVI10+). 315 */ 316 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 317 { 318 u64 *rptr; 319 320 /* XXX check if swapping is necessary on BE */ 321 rptr = (u64 *)ring->rptr_cpu_addr; 322 323 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 324 return ((*rptr) >> 2); 325 } 326 327 /** 328 * sdma_v5_0_ring_get_wptr - get the current write pointer 329 * 330 * @ring: amdgpu ring pointer 331 * 332 * Get the current wptr from the hardware (NAVI10+). 333 */ 334 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 335 { 336 struct amdgpu_device *adev = ring->adev; 337 u64 wptr; 338 339 if (ring->use_doorbell) { 340 /* XXX check if swapping is necessary on BE */ 341 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); 342 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 343 } else { 344 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 345 wptr = wptr << 32; 346 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 347 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 348 } 349 350 return wptr >> 2; 351 } 352 353 /** 354 * sdma_v5_0_ring_set_wptr - commit the write pointer 355 * 356 * @ring: amdgpu ring pointer 357 * 358 * Write the wptr back to the hardware (NAVI10+). 359 */ 360 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 361 { 362 struct amdgpu_device *adev = ring->adev; 363 uint32_t *wptr_saved; 364 uint32_t *is_queue_unmap; 365 uint64_t aggregated_db_index; 366 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size; 367 368 DRM_DEBUG("Setting write pointer\n"); 369 if (ring->is_mes_queue) { 370 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 371 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 372 sizeof(uint32_t)); 373 aggregated_db_index = 374 amdgpu_mes_get_aggregated_doorbell_index(adev, 375 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 376 377 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 378 ring->wptr << 2); 379 *wptr_saved = ring->wptr << 2; 380 if (*is_queue_unmap) { 381 WDOORBELL64(aggregated_db_index, ring->wptr << 2); 382 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 383 ring->doorbell_index, ring->wptr << 2); 384 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 385 } else { 386 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 387 ring->doorbell_index, ring->wptr << 2); 388 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 389 390 if (*is_queue_unmap) 391 WDOORBELL64(aggregated_db_index, 392 ring->wptr << 2); 393 } 394 } else { 395 if (ring->use_doorbell) { 396 DRM_DEBUG("Using doorbell -- " 397 "wptr_offs == 0x%08x " 398 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 399 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 400 ring->wptr_offs, 401 lower_32_bits(ring->wptr << 2), 402 upper_32_bits(ring->wptr << 2)); 403 /* XXX check if swapping is necessary on BE */ 404 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 405 ring->wptr << 2); 406 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 407 ring->doorbell_index, ring->wptr << 2); 408 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 409 } else { 410 DRM_DEBUG("Not using doorbell -- " 411 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 412 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 413 ring->me, 414 lower_32_bits(ring->wptr << 2), 415 ring->me, 416 upper_32_bits(ring->wptr << 2)); 417 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, 418 ring->me, mmSDMA0_GFX_RB_WPTR), 419 lower_32_bits(ring->wptr << 2)); 420 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, 421 ring->me, mmSDMA0_GFX_RB_WPTR_HI), 422 upper_32_bits(ring->wptr << 2)); 423 } 424 } 425 } 426 427 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 428 { 429 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 430 int i; 431 432 for (i = 0; i < count; i++) 433 if (sdma && sdma->burst_nop && (i == 0)) 434 amdgpu_ring_write(ring, ring->funcs->nop | 435 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 436 else 437 amdgpu_ring_write(ring, ring->funcs->nop); 438 } 439 440 /** 441 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine 442 * 443 * @ring: amdgpu ring pointer 444 * @job: job to retrieve vmid from 445 * @ib: IB object to schedule 446 * @flags: unused 447 * 448 * Schedule an IB in the DMA ring (NAVI10). 449 */ 450 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 451 struct amdgpu_job *job, 452 struct amdgpu_ib *ib, 453 uint32_t flags) 454 { 455 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 456 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 457 458 /* An IB packet must end on a 8 DW boundary--the next dword 459 * must be on a 8-dword boundary. Our IB packet below is 6 460 * dwords long, thus add x number of NOPs, such that, in 461 * modular arithmetic, 462 * wptr + 6 + x = 8k, k >= 0, which in C is, 463 * (wptr + 6 + x) % 8 = 0. 464 * The expression below, is a solution of x. 465 */ 466 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 467 468 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 469 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 470 /* base must be 32 byte aligned */ 471 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 472 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 473 amdgpu_ring_write(ring, ib->length_dw); 474 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 475 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 476 } 477 478 /** 479 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 480 * 481 * @ring: amdgpu ring pointer 482 * 483 * flush the IB by graphics cache rinse. 484 */ 485 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 486 { 487 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 488 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 489 SDMA_GCR_GLI_INV(1); 490 491 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 492 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 493 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 494 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 495 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 496 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 497 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 498 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 499 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 500 } 501 502 /** 503 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 504 * 505 * @ring: amdgpu ring pointer 506 * 507 * Emit an hdp flush packet on the requested DMA ring. 508 */ 509 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 510 { 511 struct amdgpu_device *adev = ring->adev; 512 u32 ref_and_mask = 0; 513 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 514 515 if (ring->me == 0) 516 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 517 else 518 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 519 520 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 521 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 522 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 523 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 524 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 525 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 526 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 527 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 528 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 529 } 530 531 /** 532 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring 533 * 534 * @ring: amdgpu ring pointer 535 * @addr: address 536 * @seq: sequence number 537 * @flags: fence related flags 538 * 539 * Add a DMA fence packet to the ring to write 540 * the fence seq number and DMA trap packet to generate 541 * an interrupt if needed (NAVI10). 542 */ 543 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 544 unsigned flags) 545 { 546 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 547 /* write the fence */ 548 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 549 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 550 /* zero in first two bits */ 551 BUG_ON(addr & 0x3); 552 amdgpu_ring_write(ring, lower_32_bits(addr)); 553 amdgpu_ring_write(ring, upper_32_bits(addr)); 554 amdgpu_ring_write(ring, lower_32_bits(seq)); 555 556 /* optionally write high bits as well */ 557 if (write64bit) { 558 addr += 4; 559 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 560 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 561 /* zero in first two bits */ 562 BUG_ON(addr & 0x3); 563 amdgpu_ring_write(ring, lower_32_bits(addr)); 564 amdgpu_ring_write(ring, upper_32_bits(addr)); 565 amdgpu_ring_write(ring, upper_32_bits(seq)); 566 } 567 568 if (flags & AMDGPU_FENCE_FLAG_INT) { 569 uint32_t ctx = ring->is_mes_queue ? 570 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0; 571 /* generate an interrupt */ 572 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 573 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx)); 574 } 575 } 576 577 578 /** 579 * sdma_v5_0_gfx_stop - stop the gfx async dma engines 580 * 581 * @adev: amdgpu_device pointer 582 * 583 * Stop the gfx async dma ring buffers (NAVI10). 584 */ 585 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev) 586 { 587 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 588 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 589 u32 rb_cntl, ib_cntl; 590 int i; 591 592 if ((adev->mman.buffer_funcs_ring == sdma0) || 593 (adev->mman.buffer_funcs_ring == sdma1)) 594 amdgpu_ttm_set_buffer_funcs_status(adev, false); 595 596 for (i = 0; i < adev->sdma.num_instances; i++) { 597 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 598 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 599 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 600 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 601 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 602 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 603 } 604 } 605 606 /** 607 * sdma_v5_0_rlc_stop - stop the compute async dma engines 608 * 609 * @adev: amdgpu_device pointer 610 * 611 * Stop the compute async dma queues (NAVI10). 612 */ 613 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) 614 { 615 /* XXX todo */ 616 } 617 618 /** 619 * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch 620 * 621 * @adev: amdgpu_device pointer 622 * @enable: enable/disable the DMA MEs context switch. 623 * 624 * Halt or unhalt the async dma engines context switch (NAVI10). 625 */ 626 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 627 { 628 u32 f32_cntl = 0, phase_quantum = 0; 629 int i; 630 631 if (amdgpu_sdma_phase_quantum) { 632 unsigned value = amdgpu_sdma_phase_quantum; 633 unsigned unit = 0; 634 635 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 636 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 637 value = (value + 1) >> 1; 638 unit++; 639 } 640 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 641 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 642 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 643 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 644 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 645 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 646 WARN_ONCE(1, 647 "clamping sdma_phase_quantum to %uK clock cycles\n", 648 value << unit); 649 } 650 phase_quantum = 651 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 652 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 653 } 654 655 for (i = 0; i < adev->sdma.num_instances; i++) { 656 if (!amdgpu_sriov_vf(adev)) { 657 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 658 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 659 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 660 } 661 662 if (enable && amdgpu_sdma_phase_quantum) { 663 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 664 phase_quantum); 665 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 666 phase_quantum); 667 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 668 phase_quantum); 669 } 670 if (!amdgpu_sriov_vf(adev)) 671 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 672 } 673 674 } 675 676 /** 677 * sdma_v5_0_enable - stop the async dma engines 678 * 679 * @adev: amdgpu_device pointer 680 * @enable: enable/disable the DMA MEs. 681 * 682 * Halt or unhalt the async dma engines (NAVI10). 683 */ 684 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) 685 { 686 u32 f32_cntl; 687 int i; 688 689 if (!enable) { 690 sdma_v5_0_gfx_stop(adev); 691 sdma_v5_0_rlc_stop(adev); 692 } 693 694 if (amdgpu_sriov_vf(adev)) 695 return; 696 697 for (i = 0; i < adev->sdma.num_instances; i++) { 698 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 699 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 700 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 701 } 702 } 703 704 /** 705 * sdma_v5_0_gfx_resume - setup and start the async dma engines 706 * 707 * @adev: amdgpu_device pointer 708 * 709 * Set up the gfx DMA ring buffers and enable them (NAVI10). 710 * Returns 0 for success, error for failure. 711 */ 712 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) 713 { 714 struct amdgpu_ring *ring; 715 u32 rb_cntl, ib_cntl; 716 u32 rb_bufsz; 717 u32 doorbell; 718 u32 doorbell_offset; 719 u32 temp; 720 u32 wptr_poll_cntl; 721 u64 wptr_gpu_addr; 722 int i, r; 723 724 for (i = 0; i < adev->sdma.num_instances; i++) { 725 ring = &adev->sdma.instance[i].ring; 726 727 if (!amdgpu_sriov_vf(adev)) 728 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 729 730 /* Set ring buffer size in dwords */ 731 rb_bufsz = order_base_2(ring->ring_size / 4); 732 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 733 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 734 #ifdef __BIG_ENDIAN 735 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 736 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 737 RPTR_WRITEBACK_SWAP_ENABLE, 1); 738 #endif 739 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 740 741 /* Initialize the ring buffer's read and write pointers */ 742 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 743 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 744 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 745 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 746 747 /* setup the wptr shadow polling */ 748 wptr_gpu_addr = ring->wptr_gpu_addr; 749 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 750 lower_32_bits(wptr_gpu_addr)); 751 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 752 upper_32_bits(wptr_gpu_addr)); 753 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 754 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 755 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 756 SDMA0_GFX_RB_WPTR_POLL_CNTL, 757 F32_POLL_ENABLE, 1); 758 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 759 wptr_poll_cntl); 760 761 /* set the wb address whether it's enabled or not */ 762 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 763 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 764 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 765 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 766 767 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 768 769 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), 770 ring->gpu_addr >> 8); 771 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), 772 ring->gpu_addr >> 40); 773 774 ring->wptr = 0; 775 776 /* before programing wptr to a less value, need set minor_ptr_update first */ 777 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 778 779 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 780 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 781 lower_32_bits(ring->wptr << 2)); 782 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 783 upper_32_bits(ring->wptr << 2)); 784 } 785 786 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 787 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 788 mmSDMA0_GFX_DOORBELL_OFFSET)); 789 790 if (ring->use_doorbell) { 791 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 792 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 793 OFFSET, ring->doorbell_index); 794 } else { 795 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 796 } 797 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 798 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), 799 doorbell_offset); 800 801 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 802 ring->doorbell_index, 20); 803 804 if (amdgpu_sriov_vf(adev)) 805 sdma_v5_0_ring_set_wptr(ring); 806 807 /* set minor_ptr_update to 0 after wptr programed */ 808 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 809 810 if (!amdgpu_sriov_vf(adev)) { 811 /* set utc l1 enable flag always to 1 */ 812 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 813 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 814 815 /* enable MCBP */ 816 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 817 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 818 819 /* Set up RESP_MODE to non-copy addresses */ 820 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 821 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 822 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 823 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 824 825 /* program default cache read and write policy */ 826 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 827 /* clean read policy and write policy bits */ 828 temp &= 0xFF0FFF; 829 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 830 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 831 } 832 833 if (!amdgpu_sriov_vf(adev)) { 834 /* unhalt engine */ 835 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 836 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 837 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 838 } 839 840 /* enable DMA RB */ 841 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 842 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 843 844 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 845 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 846 #ifdef __BIG_ENDIAN 847 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 848 #endif 849 /* enable DMA IBs */ 850 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 851 852 ring->sched.ready = true; 853 854 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 855 sdma_v5_0_ctx_switch_enable(adev, true); 856 sdma_v5_0_enable(adev, true); 857 } 858 859 r = amdgpu_ring_test_helper(ring); 860 if (r) 861 return r; 862 863 if (adev->mman.buffer_funcs_ring == ring) 864 amdgpu_ttm_set_buffer_funcs_status(adev, true); 865 } 866 867 return 0; 868 } 869 870 /** 871 * sdma_v5_0_rlc_resume - setup and start the async dma engines 872 * 873 * @adev: amdgpu_device pointer 874 * 875 * Set up the compute DMA queues and enable them (NAVI10). 876 * Returns 0 for success, error for failure. 877 */ 878 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev) 879 { 880 return 0; 881 } 882 883 /** 884 * sdma_v5_0_load_microcode - load the sDMA ME ucode 885 * 886 * @adev: amdgpu_device pointer 887 * 888 * Loads the sDMA0/1 ucode. 889 * Returns 0 for success, -EINVAL if the ucode is not available. 890 */ 891 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev) 892 { 893 const struct sdma_firmware_header_v1_0 *hdr; 894 const __le32 *fw_data; 895 u32 fw_size; 896 int i, j; 897 898 /* halt the MEs */ 899 sdma_v5_0_enable(adev, false); 900 901 for (i = 0; i < adev->sdma.num_instances; i++) { 902 if (!adev->sdma.instance[i].fw) 903 return -EINVAL; 904 905 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 906 amdgpu_ucode_print_sdma_hdr(&hdr->header); 907 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 908 909 fw_data = (const __le32 *) 910 (adev->sdma.instance[i].fw->data + 911 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 912 913 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 914 915 for (j = 0; j < fw_size; j++) { 916 if (amdgpu_emu_mode == 1 && j % 500 == 0) 917 msleep(1); 918 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 919 } 920 921 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 922 } 923 924 return 0; 925 } 926 927 /** 928 * sdma_v5_0_start - setup and start the async dma engines 929 * 930 * @adev: amdgpu_device pointer 931 * 932 * Set up the DMA engines and enable them (NAVI10). 933 * Returns 0 for success, error for failure. 934 */ 935 static int sdma_v5_0_start(struct amdgpu_device *adev) 936 { 937 int r = 0; 938 939 if (amdgpu_sriov_vf(adev)) { 940 sdma_v5_0_ctx_switch_enable(adev, false); 941 sdma_v5_0_enable(adev, false); 942 943 /* set RB registers */ 944 r = sdma_v5_0_gfx_resume(adev); 945 return r; 946 } 947 948 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 949 r = sdma_v5_0_load_microcode(adev); 950 if (r) 951 return r; 952 } 953 954 /* unhalt the MEs */ 955 sdma_v5_0_enable(adev, true); 956 /* enable sdma ring preemption */ 957 sdma_v5_0_ctx_switch_enable(adev, true); 958 959 /* start the gfx rings and rlc compute queues */ 960 r = sdma_v5_0_gfx_resume(adev); 961 if (r) 962 return r; 963 r = sdma_v5_0_rlc_resume(adev); 964 965 return r; 966 } 967 968 static int sdma_v5_0_mqd_init(struct amdgpu_device *adev, void *mqd, 969 struct amdgpu_mqd_prop *prop) 970 { 971 struct v10_sdma_mqd *m = mqd; 972 uint64_t wb_gpu_addr; 973 974 m->sdmax_rlcx_rb_cntl = 975 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | 976 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | 977 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | 978 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT; 979 980 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); 981 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); 982 983 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0, 984 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 985 986 wb_gpu_addr = prop->wptr_gpu_addr; 987 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); 988 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); 989 990 wb_gpu_addr = prop->rptr_gpu_addr; 991 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); 992 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); 993 994 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, 0, 995 mmSDMA0_GFX_IB_CNTL)); 996 997 m->sdmax_rlcx_doorbell_offset = 998 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT; 999 1000 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1); 1001 1002 return 0; 1003 } 1004 1005 static void sdma_v5_0_set_mqd_funcs(struct amdgpu_device *adev) 1006 { 1007 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd); 1008 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_0_mqd_init; 1009 } 1010 1011 /** 1012 * sdma_v5_0_ring_test_ring - simple async dma engine test 1013 * 1014 * @ring: amdgpu_ring structure holding ring information 1015 * 1016 * Test the DMA engine by writing using it to write an 1017 * value to memory. (NAVI10). 1018 * Returns 0 for success, error for failure. 1019 */ 1020 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) 1021 { 1022 struct amdgpu_device *adev = ring->adev; 1023 unsigned i; 1024 unsigned index; 1025 int r; 1026 u32 tmp; 1027 u64 gpu_addr; 1028 volatile uint32_t *cpu_ptr = NULL; 1029 1030 tmp = 0xCAFEDEAD; 1031 1032 if (ring->is_mes_queue) { 1033 uint32_t offset = 0; 1034 offset = amdgpu_mes_ctx_get_offs(ring, 1035 AMDGPU_MES_CTX_PADDING_OFFS); 1036 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 1037 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 1038 *cpu_ptr = tmp; 1039 } else { 1040 r = amdgpu_device_wb_get(adev, &index); 1041 if (r) { 1042 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 1043 return r; 1044 } 1045 1046 gpu_addr = adev->wb.gpu_addr + (index * 4); 1047 adev->wb.wb[index] = cpu_to_le32(tmp); 1048 } 1049 1050 r = amdgpu_ring_alloc(ring, 20); 1051 if (r) { 1052 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 1053 amdgpu_device_wb_free(adev, index); 1054 return r; 1055 } 1056 1057 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1058 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1059 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1060 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1061 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1062 amdgpu_ring_write(ring, 0xDEADBEEF); 1063 amdgpu_ring_commit(ring); 1064 1065 for (i = 0; i < adev->usec_timeout; i++) { 1066 if (ring->is_mes_queue) 1067 tmp = le32_to_cpu(*cpu_ptr); 1068 else 1069 tmp = le32_to_cpu(adev->wb.wb[index]); 1070 if (tmp == 0xDEADBEEF) 1071 break; 1072 if (amdgpu_emu_mode == 1) 1073 msleep(1); 1074 else 1075 udelay(1); 1076 } 1077 1078 if (i >= adev->usec_timeout) 1079 r = -ETIMEDOUT; 1080 1081 if (!ring->is_mes_queue) 1082 amdgpu_device_wb_free(adev, index); 1083 1084 return r; 1085 } 1086 1087 /** 1088 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine 1089 * 1090 * @ring: amdgpu_ring structure holding ring information 1091 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1092 * 1093 * Test a simple IB in the DMA ring (NAVI10). 1094 * Returns 0 on success, error on failure. 1095 */ 1096 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1097 { 1098 struct amdgpu_device *adev = ring->adev; 1099 struct amdgpu_ib ib; 1100 struct dma_fence *f = NULL; 1101 unsigned index; 1102 long r; 1103 u32 tmp = 0; 1104 u64 gpu_addr; 1105 volatile uint32_t *cpu_ptr = NULL; 1106 1107 tmp = 0xCAFEDEAD; 1108 memset(&ib, 0, sizeof(ib)); 1109 1110 if (ring->is_mes_queue) { 1111 uint32_t offset = 0; 1112 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 1113 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 1114 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 1115 1116 offset = amdgpu_mes_ctx_get_offs(ring, 1117 AMDGPU_MES_CTX_PADDING_OFFS); 1118 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 1119 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 1120 *cpu_ptr = tmp; 1121 } else { 1122 r = amdgpu_device_wb_get(adev, &index); 1123 if (r) { 1124 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1125 return r; 1126 } 1127 1128 gpu_addr = adev->wb.gpu_addr + (index * 4); 1129 adev->wb.wb[index] = cpu_to_le32(tmp); 1130 1131 r = amdgpu_ib_get(adev, NULL, 256, 1132 AMDGPU_IB_POOL_DIRECT, &ib); 1133 if (r) { 1134 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1135 goto err0; 1136 } 1137 } 1138 1139 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1140 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1141 ib.ptr[1] = lower_32_bits(gpu_addr); 1142 ib.ptr[2] = upper_32_bits(gpu_addr); 1143 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1144 ib.ptr[4] = 0xDEADBEEF; 1145 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1146 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1147 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1148 ib.length_dw = 8; 1149 1150 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1151 if (r) 1152 goto err1; 1153 1154 r = dma_fence_wait_timeout(f, false, timeout); 1155 if (r == 0) { 1156 DRM_ERROR("amdgpu: IB test timed out\n"); 1157 r = -ETIMEDOUT; 1158 goto err1; 1159 } else if (r < 0) { 1160 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1161 goto err1; 1162 } 1163 1164 if (ring->is_mes_queue) 1165 tmp = le32_to_cpu(*cpu_ptr); 1166 else 1167 tmp = le32_to_cpu(adev->wb.wb[index]); 1168 1169 if (tmp == 0xDEADBEEF) 1170 r = 0; 1171 else 1172 r = -EINVAL; 1173 1174 err1: 1175 amdgpu_ib_free(adev, &ib, NULL); 1176 dma_fence_put(f); 1177 err0: 1178 if (!ring->is_mes_queue) 1179 amdgpu_device_wb_free(adev, index); 1180 return r; 1181 } 1182 1183 1184 /** 1185 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART 1186 * 1187 * @ib: indirect buffer to fill with commands 1188 * @pe: addr of the page entry 1189 * @src: src addr to copy from 1190 * @count: number of page entries to update 1191 * 1192 * Update PTEs by copying them from the GART using sDMA (NAVI10). 1193 */ 1194 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib, 1195 uint64_t pe, uint64_t src, 1196 unsigned count) 1197 { 1198 unsigned bytes = count * 8; 1199 1200 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1201 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1202 ib->ptr[ib->length_dw++] = bytes - 1; 1203 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1204 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1205 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1206 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1207 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1208 1209 } 1210 1211 /** 1212 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually 1213 * 1214 * @ib: indirect buffer to fill with commands 1215 * @pe: addr of the page entry 1216 * @value: dst addr to write into pe 1217 * @count: number of page entries to update 1218 * @incr: increase next addr by incr bytes 1219 * 1220 * Update PTEs by writing them manually using sDMA (NAVI10). 1221 */ 1222 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1223 uint64_t value, unsigned count, 1224 uint32_t incr) 1225 { 1226 unsigned ndw = count * 2; 1227 1228 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1229 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1230 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1231 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1232 ib->ptr[ib->length_dw++] = ndw - 1; 1233 for (; ndw > 0; ndw -= 2) { 1234 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1235 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1236 value += incr; 1237 } 1238 } 1239 1240 /** 1241 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA 1242 * 1243 * @ib: indirect buffer to fill with commands 1244 * @pe: addr of the page entry 1245 * @addr: dst addr to write into pe 1246 * @count: number of page entries to update 1247 * @incr: increase next addr by incr bytes 1248 * @flags: access flags 1249 * 1250 * Update the page tables using sDMA (NAVI10). 1251 */ 1252 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1253 uint64_t pe, 1254 uint64_t addr, unsigned count, 1255 uint32_t incr, uint64_t flags) 1256 { 1257 /* for physically contiguous pages (vram) */ 1258 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1259 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1260 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1261 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1262 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1263 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1264 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1265 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1266 ib->ptr[ib->length_dw++] = 0; 1267 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1268 } 1269 1270 /** 1271 * sdma_v5_0_ring_pad_ib - pad the IB 1272 * @ring: amdgpu_ring structure holding ring information 1273 * @ib: indirect buffer to fill with padding 1274 * 1275 * Pad the IB with NOPs to a boundary multiple of 8. 1276 */ 1277 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1278 { 1279 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1280 u32 pad_count; 1281 int i; 1282 1283 pad_count = (-ib->length_dw) & 0x7; 1284 for (i = 0; i < pad_count; i++) 1285 if (sdma && sdma->burst_nop && (i == 0)) 1286 ib->ptr[ib->length_dw++] = 1287 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1288 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1289 else 1290 ib->ptr[ib->length_dw++] = 1291 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1292 } 1293 1294 1295 /** 1296 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline 1297 * 1298 * @ring: amdgpu_ring pointer 1299 * 1300 * Make sure all previous operations are completed (CIK). 1301 */ 1302 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1303 { 1304 uint32_t seq = ring->fence_drv.sync_seq; 1305 uint64_t addr = ring->fence_drv.gpu_addr; 1306 1307 /* wait for idle */ 1308 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1309 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1310 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1311 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1312 amdgpu_ring_write(ring, addr & 0xfffffffc); 1313 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1314 amdgpu_ring_write(ring, seq); /* reference */ 1315 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1316 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1317 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1318 } 1319 1320 1321 /** 1322 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA 1323 * 1324 * @ring: amdgpu_ring pointer 1325 * @vmid: vmid number to use 1326 * @pd_addr: address 1327 * 1328 * Update the page table base and flush the VM TLB 1329 * using sDMA (NAVI10). 1330 */ 1331 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1332 unsigned vmid, uint64_t pd_addr) 1333 { 1334 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1335 } 1336 1337 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring, 1338 uint32_t reg, uint32_t val) 1339 { 1340 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1341 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1342 amdgpu_ring_write(ring, reg); 1343 amdgpu_ring_write(ring, val); 1344 } 1345 1346 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1347 uint32_t val, uint32_t mask) 1348 { 1349 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1350 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1351 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1352 amdgpu_ring_write(ring, reg << 2); 1353 amdgpu_ring_write(ring, 0); 1354 amdgpu_ring_write(ring, val); /* reference */ 1355 amdgpu_ring_write(ring, mask); /* mask */ 1356 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1357 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1358 } 1359 1360 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1361 uint32_t reg0, uint32_t reg1, 1362 uint32_t ref, uint32_t mask) 1363 { 1364 amdgpu_ring_emit_wreg(ring, reg0, ref); 1365 /* wait for a cycle to reset vm_inv_eng*_ack */ 1366 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1367 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1368 } 1369 1370 static int sdma_v5_0_early_init(void *handle) 1371 { 1372 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1373 1374 sdma_v5_0_set_ring_funcs(adev); 1375 sdma_v5_0_set_buffer_funcs(adev); 1376 sdma_v5_0_set_vm_pte_funcs(adev); 1377 sdma_v5_0_set_irq_funcs(adev); 1378 sdma_v5_0_set_mqd_funcs(adev); 1379 1380 return 0; 1381 } 1382 1383 1384 static int sdma_v5_0_sw_init(void *handle) 1385 { 1386 struct amdgpu_ring *ring; 1387 int r, i; 1388 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1389 1390 /* SDMA trap event */ 1391 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 1392 SDMA0_5_0__SRCID__SDMA_TRAP, 1393 &adev->sdma.trap_irq); 1394 if (r) 1395 return r; 1396 1397 /* SDMA trap event */ 1398 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 1399 SDMA1_5_0__SRCID__SDMA_TRAP, 1400 &adev->sdma.trap_irq); 1401 if (r) 1402 return r; 1403 1404 r = sdma_v5_0_init_microcode(adev); 1405 if (r) { 1406 DRM_ERROR("Failed to load sdma firmware!\n"); 1407 return r; 1408 } 1409 1410 for (i = 0; i < adev->sdma.num_instances; i++) { 1411 ring = &adev->sdma.instance[i].ring; 1412 ring->ring_obj = NULL; 1413 ring->use_doorbell = true; 1414 1415 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1416 ring->use_doorbell?"true":"false"); 1417 1418 ring->doorbell_index = (i == 0) ? 1419 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset 1420 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset 1421 1422 sprintf(ring->name, "sdma%d", i); 1423 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1424 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 1425 AMDGPU_SDMA_IRQ_INSTANCE1, 1426 AMDGPU_RING_PRIO_DEFAULT, NULL); 1427 if (r) 1428 return r; 1429 } 1430 1431 return r; 1432 } 1433 1434 static int sdma_v5_0_sw_fini(void *handle) 1435 { 1436 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1437 int i; 1438 1439 for (i = 0; i < adev->sdma.num_instances; i++) 1440 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1441 1442 amdgpu_sdma_destroy_inst_ctx(adev, false); 1443 1444 return 0; 1445 } 1446 1447 static int sdma_v5_0_hw_init(void *handle) 1448 { 1449 int r; 1450 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1451 1452 sdma_v5_0_init_golden_registers(adev); 1453 1454 r = sdma_v5_0_start(adev); 1455 1456 return r; 1457 } 1458 1459 static int sdma_v5_0_hw_fini(void *handle) 1460 { 1461 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1462 1463 if (amdgpu_sriov_vf(adev)) 1464 return 0; 1465 1466 sdma_v5_0_ctx_switch_enable(adev, false); 1467 sdma_v5_0_enable(adev, false); 1468 1469 return 0; 1470 } 1471 1472 static int sdma_v5_0_suspend(void *handle) 1473 { 1474 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1475 1476 return sdma_v5_0_hw_fini(adev); 1477 } 1478 1479 static int sdma_v5_0_resume(void *handle) 1480 { 1481 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1482 1483 return sdma_v5_0_hw_init(adev); 1484 } 1485 1486 static bool sdma_v5_0_is_idle(void *handle) 1487 { 1488 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1489 u32 i; 1490 1491 for (i = 0; i < adev->sdma.num_instances; i++) { 1492 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1493 1494 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1495 return false; 1496 } 1497 1498 return true; 1499 } 1500 1501 static int sdma_v5_0_wait_for_idle(void *handle) 1502 { 1503 unsigned i; 1504 u32 sdma0, sdma1; 1505 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1506 1507 for (i = 0; i < adev->usec_timeout; i++) { 1508 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1509 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1510 1511 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1512 return 0; 1513 udelay(1); 1514 } 1515 return -ETIMEDOUT; 1516 } 1517 1518 static int sdma_v5_0_soft_reset(void *handle) 1519 { 1520 /* todo */ 1521 1522 return 0; 1523 } 1524 1525 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring) 1526 { 1527 int i, r = 0; 1528 struct amdgpu_device *adev = ring->adev; 1529 u32 index = 0; 1530 u64 sdma_gfx_preempt; 1531 1532 amdgpu_sdma_get_index_from_ring(ring, &index); 1533 if (index == 0) 1534 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT; 1535 else 1536 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT; 1537 1538 /* assert preemption condition */ 1539 amdgpu_ring_set_preempt_cond_exec(ring, false); 1540 1541 /* emit the trailing fence */ 1542 ring->trail_seq += 1; 1543 amdgpu_ring_alloc(ring, 10); 1544 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1545 ring->trail_seq, 0); 1546 amdgpu_ring_commit(ring); 1547 1548 /* assert IB preemption */ 1549 WREG32(sdma_gfx_preempt, 1); 1550 1551 /* poll the trailing fence */ 1552 for (i = 0; i < adev->usec_timeout; i++) { 1553 if (ring->trail_seq == 1554 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1555 break; 1556 udelay(1); 1557 } 1558 1559 if (i >= adev->usec_timeout) { 1560 r = -EINVAL; 1561 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1562 } 1563 1564 /* deassert IB preemption */ 1565 WREG32(sdma_gfx_preempt, 0); 1566 1567 /* deassert the preemption condition */ 1568 amdgpu_ring_set_preempt_cond_exec(ring, true); 1569 return r; 1570 } 1571 1572 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev, 1573 struct amdgpu_irq_src *source, 1574 unsigned type, 1575 enum amdgpu_interrupt_state state) 1576 { 1577 u32 sdma_cntl; 1578 1579 if (!amdgpu_sriov_vf(adev)) { 1580 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? 1581 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1582 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1583 1584 sdma_cntl = RREG32(reg_offset); 1585 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1586 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1587 WREG32(reg_offset, sdma_cntl); 1588 } 1589 1590 return 0; 1591 } 1592 1593 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, 1594 struct amdgpu_irq_src *source, 1595 struct amdgpu_iv_entry *entry) 1596 { 1597 uint32_t mes_queue_id = entry->src_data[0]; 1598 1599 DRM_DEBUG("IH: SDMA trap\n"); 1600 1601 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 1602 struct amdgpu_mes_queue *queue; 1603 1604 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 1605 1606 spin_lock(&adev->mes.queue_id_lock); 1607 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 1608 if (queue) { 1609 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); 1610 amdgpu_fence_process(queue->ring); 1611 } 1612 spin_unlock(&adev->mes.queue_id_lock); 1613 return 0; 1614 } 1615 1616 switch (entry->client_id) { 1617 case SOC15_IH_CLIENTID_SDMA0: 1618 switch (entry->ring_id) { 1619 case 0: 1620 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1621 break; 1622 case 1: 1623 /* XXX compute */ 1624 break; 1625 case 2: 1626 /* XXX compute */ 1627 break; 1628 case 3: 1629 /* XXX page queue*/ 1630 break; 1631 } 1632 break; 1633 case SOC15_IH_CLIENTID_SDMA1: 1634 switch (entry->ring_id) { 1635 case 0: 1636 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1637 break; 1638 case 1: 1639 /* XXX compute */ 1640 break; 1641 case 2: 1642 /* XXX compute */ 1643 break; 1644 case 3: 1645 /* XXX page queue*/ 1646 break; 1647 } 1648 break; 1649 } 1650 return 0; 1651 } 1652 1653 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1654 struct amdgpu_irq_src *source, 1655 struct amdgpu_iv_entry *entry) 1656 { 1657 return 0; 1658 } 1659 1660 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1661 bool enable) 1662 { 1663 uint32_t data, def; 1664 int i; 1665 1666 for (i = 0; i < adev->sdma.num_instances; i++) { 1667 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1668 /* Enable sdma clock gating */ 1669 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1670 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1671 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1672 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1673 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1674 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1675 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1676 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1677 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1678 if (def != data) 1679 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1680 } else { 1681 /* Disable sdma clock gating */ 1682 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1683 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1684 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1685 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1686 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1687 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1688 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1689 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1690 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1691 if (def != data) 1692 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1693 } 1694 } 1695 } 1696 1697 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1698 bool enable) 1699 { 1700 uint32_t data, def; 1701 int i; 1702 1703 for (i = 0; i < adev->sdma.num_instances; i++) { 1704 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1705 /* Enable sdma mem light sleep */ 1706 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1707 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1708 if (def != data) 1709 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1710 1711 } else { 1712 /* Disable sdma mem light sleep */ 1713 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1714 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1715 if (def != data) 1716 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1717 1718 } 1719 } 1720 } 1721 1722 static int sdma_v5_0_set_clockgating_state(void *handle, 1723 enum amd_clockgating_state state) 1724 { 1725 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1726 1727 if (amdgpu_sriov_vf(adev)) 1728 return 0; 1729 1730 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1731 case IP_VERSION(5, 0, 0): 1732 case IP_VERSION(5, 0, 2): 1733 case IP_VERSION(5, 0, 5): 1734 sdma_v5_0_update_medium_grain_clock_gating(adev, 1735 state == AMD_CG_STATE_GATE); 1736 sdma_v5_0_update_medium_grain_light_sleep(adev, 1737 state == AMD_CG_STATE_GATE); 1738 break; 1739 default: 1740 break; 1741 } 1742 1743 return 0; 1744 } 1745 1746 static int sdma_v5_0_set_powergating_state(void *handle, 1747 enum amd_powergating_state state) 1748 { 1749 return 0; 1750 } 1751 1752 static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags) 1753 { 1754 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1755 int data; 1756 1757 if (amdgpu_sriov_vf(adev)) 1758 *flags = 0; 1759 1760 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1761 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1762 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1763 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1764 1765 /* AMD_CG_SUPPORT_SDMA_LS */ 1766 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1767 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1768 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1769 } 1770 1771 const struct amd_ip_funcs sdma_v5_0_ip_funcs = { 1772 .name = "sdma_v5_0", 1773 .early_init = sdma_v5_0_early_init, 1774 .late_init = NULL, 1775 .sw_init = sdma_v5_0_sw_init, 1776 .sw_fini = sdma_v5_0_sw_fini, 1777 .hw_init = sdma_v5_0_hw_init, 1778 .hw_fini = sdma_v5_0_hw_fini, 1779 .suspend = sdma_v5_0_suspend, 1780 .resume = sdma_v5_0_resume, 1781 .is_idle = sdma_v5_0_is_idle, 1782 .wait_for_idle = sdma_v5_0_wait_for_idle, 1783 .soft_reset = sdma_v5_0_soft_reset, 1784 .set_clockgating_state = sdma_v5_0_set_clockgating_state, 1785 .set_powergating_state = sdma_v5_0_set_powergating_state, 1786 .get_clockgating_state = sdma_v5_0_get_clockgating_state, 1787 }; 1788 1789 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 1790 .type = AMDGPU_RING_TYPE_SDMA, 1791 .align_mask = 0xf, 1792 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1793 .support_64bit_ptrs = true, 1794 .secure_submission_supported = true, 1795 .vmhub = AMDGPU_GFXHUB_0, 1796 .get_rptr = sdma_v5_0_ring_get_rptr, 1797 .get_wptr = sdma_v5_0_ring_get_wptr, 1798 .set_wptr = sdma_v5_0_ring_set_wptr, 1799 .emit_frame_size = 1800 5 + /* sdma_v5_0_ring_init_cond_exec */ 1801 6 + /* sdma_v5_0_ring_emit_hdp_flush */ 1802 3 + /* hdp_invalidate */ 1803 6 + /* sdma_v5_0_ring_emit_pipeline_sync */ 1804 /* sdma_v5_0_ring_emit_vm_flush */ 1805 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1806 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 + 1807 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ 1808 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */ 1809 .emit_ib = sdma_v5_0_ring_emit_ib, 1810 .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync, 1811 .emit_fence = sdma_v5_0_ring_emit_fence, 1812 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync, 1813 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush, 1814 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush, 1815 .test_ring = sdma_v5_0_ring_test_ring, 1816 .test_ib = sdma_v5_0_ring_test_ib, 1817 .insert_nop = sdma_v5_0_ring_insert_nop, 1818 .pad_ib = sdma_v5_0_ring_pad_ib, 1819 .emit_wreg = sdma_v5_0_ring_emit_wreg, 1820 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait, 1821 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait, 1822 .init_cond_exec = sdma_v5_0_ring_init_cond_exec, 1823 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec, 1824 .preempt_ib = sdma_v5_0_ring_preempt_ib, 1825 }; 1826 1827 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) 1828 { 1829 int i; 1830 1831 for (i = 0; i < adev->sdma.num_instances; i++) { 1832 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; 1833 adev->sdma.instance[i].ring.me = i; 1834 } 1835 } 1836 1837 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = { 1838 .set = sdma_v5_0_set_trap_irq_state, 1839 .process = sdma_v5_0_process_trap_irq, 1840 }; 1841 1842 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = { 1843 .process = sdma_v5_0_process_illegal_inst_irq, 1844 }; 1845 1846 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev) 1847 { 1848 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1849 adev->sdma.num_instances; 1850 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; 1851 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; 1852 } 1853 1854 /** 1855 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine 1856 * 1857 * @ib: indirect buffer to copy to 1858 * @src_offset: src GPU address 1859 * @dst_offset: dst GPU address 1860 * @byte_count: number of bytes to xfer 1861 * @tmz: if a secure copy should be used 1862 * 1863 * Copy GPU buffers using the DMA engine (NAVI10). 1864 * Used by the amdgpu ttm implementation to move pages if 1865 * registered as the asic copy callback. 1866 */ 1867 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib, 1868 uint64_t src_offset, 1869 uint64_t dst_offset, 1870 uint32_t byte_count, 1871 bool tmz) 1872 { 1873 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1874 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1875 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1876 ib->ptr[ib->length_dw++] = byte_count - 1; 1877 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1878 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1879 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1880 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1881 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1882 } 1883 1884 /** 1885 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine 1886 * 1887 * @ib: indirect buffer to fill 1888 * @src_data: value to write to buffer 1889 * @dst_offset: dst GPU address 1890 * @byte_count: number of bytes to xfer 1891 * 1892 * Fill GPU buffers using the DMA engine (NAVI10). 1893 */ 1894 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib, 1895 uint32_t src_data, 1896 uint64_t dst_offset, 1897 uint32_t byte_count) 1898 { 1899 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1900 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1901 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1902 ib->ptr[ib->length_dw++] = src_data; 1903 ib->ptr[ib->length_dw++] = byte_count - 1; 1904 } 1905 1906 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { 1907 .copy_max_bytes = 0x400000, 1908 .copy_num_dw = 7, 1909 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer, 1910 1911 .fill_max_bytes = 0x400000, 1912 .fill_num_dw = 5, 1913 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer, 1914 }; 1915 1916 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) 1917 { 1918 if (adev->mman.buffer_funcs == NULL) { 1919 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; 1920 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1921 } 1922 } 1923 1924 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 1925 .copy_pte_num_dw = 7, 1926 .copy_pte = sdma_v5_0_vm_copy_pte, 1927 .write_pte = sdma_v5_0_vm_write_pte, 1928 .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 1929 }; 1930 1931 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1932 { 1933 unsigned i; 1934 1935 if (adev->vm_manager.vm_pte_funcs == NULL) { 1936 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; 1937 for (i = 0; i < adev->sdma.num_instances; i++) { 1938 adev->vm_manager.vm_pte_scheds[i] = 1939 &adev->sdma.instance[i].ring.sched; 1940 } 1941 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1942 } 1943 } 1944 1945 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { 1946 .type = AMD_IP_BLOCK_TYPE_SDMA, 1947 .major = 5, 1948 .minor = 0, 1949 .rev = 0, 1950 .funcs = &sdma_v5_0_ip_funcs, 1951 }; 1952