1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_1_0_offset.h" 34 #include "gc/gc_10_1_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "navi10_sdma_pkt_open.h" 41 #include "nbio_v2_3.h" 42 #include "sdma_common.h" 43 #include "sdma_v5_0.h" 44 45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); 47 48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); 50 51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin"); 53 54 #define SDMA1_REG_OFFSET 0x600 55 #define SDMA0_HYP_DEC_REG_START 0x5880 56 #define SDMA0_HYP_DEC_REG_END 0x5893 57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 58 59 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); 60 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); 61 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); 62 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); 63 64 static const struct soc15_reg_golden golden_settings_sdma_5[] = { 65 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00), 77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00) 89 }; 90 91 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = { 92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 112 }; 113 114 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { 115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 117 }; 118 119 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = { 120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 122 }; 123 124 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = { 125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 127 }; 128 129 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 130 { 131 u32 base; 132 133 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 134 internal_offset <= SDMA0_HYP_DEC_REG_END) { 135 base = adev->reg_offset[GC_HWIP][0][1]; 136 if (instance == 1) 137 internal_offset += SDMA1_HYP_DEC_REG_OFFSET; 138 } else { 139 base = adev->reg_offset[GC_HWIP][0][0]; 140 if (instance == 1) 141 internal_offset += SDMA1_REG_OFFSET; 142 } 143 144 return base + internal_offset; 145 } 146 147 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) 148 { 149 switch (adev->asic_type) { 150 case CHIP_NAVI10: 151 soc15_program_register_sequence(adev, 152 golden_settings_sdma_5, 153 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 154 soc15_program_register_sequence(adev, 155 golden_settings_sdma_nv10, 156 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); 157 break; 158 case CHIP_NAVI14: 159 soc15_program_register_sequence(adev, 160 golden_settings_sdma_5, 161 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 162 soc15_program_register_sequence(adev, 163 golden_settings_sdma_nv14, 164 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14)); 165 break; 166 case CHIP_NAVI12: 167 if (amdgpu_sriov_vf(adev)) 168 soc15_program_register_sequence(adev, 169 golden_settings_sdma_5_sriov, 170 (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov)); 171 else 172 soc15_program_register_sequence(adev, 173 golden_settings_sdma_5, 174 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 175 soc15_program_register_sequence(adev, 176 golden_settings_sdma_nv12, 177 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12)); 178 break; 179 default: 180 break; 181 } 182 } 183 184 /** 185 * sdma_v5_0_init_microcode - load ucode images from disk 186 * 187 * @adev: amdgpu_device pointer 188 * 189 * Use the firmware interface to load the ucode images into 190 * the driver (not loaded into hw). 191 * Returns 0 on success, error on failure. 192 */ 193 194 // emulation only, won't work on real chip 195 // navi10 real chip need to use PSP to load firmware 196 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) 197 { 198 const char *chip_name; 199 char fw_name[30]; 200 int err = 0, i; 201 struct amdgpu_firmware_info *info = NULL; 202 const struct common_firmware_header *header = NULL; 203 const struct sdma_firmware_header_v1_0 *hdr; 204 205 if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_NAVI12)) 206 return 0; 207 208 DRM_DEBUG("\n"); 209 210 switch (adev->asic_type) { 211 case CHIP_NAVI10: 212 chip_name = "navi10"; 213 break; 214 case CHIP_NAVI14: 215 chip_name = "navi14"; 216 break; 217 case CHIP_NAVI12: 218 chip_name = "navi12"; 219 break; 220 default: 221 BUG(); 222 } 223 224 for (i = 0; i < adev->sdma.num_instances; i++) { 225 if (i == 0) 226 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 227 else 228 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 229 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 230 if (err) 231 goto out; 232 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 233 if (err) 234 goto out; 235 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 236 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 237 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 238 if (adev->sdma.instance[i].feature_version >= 20) 239 adev->sdma.instance[i].burst_nop = true; 240 DRM_DEBUG("psp_load == '%s'\n", 241 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 242 243 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 244 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 245 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 246 info->fw = adev->sdma.instance[i].fw; 247 header = (const struct common_firmware_header *)info->fw->data; 248 adev->firmware.fw_size += 249 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 250 } 251 } 252 out: 253 if (err) { 254 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name); 255 for (i = 0; i < adev->sdma.num_instances; i++) { 256 release_firmware(adev->sdma.instance[i].fw); 257 adev->sdma.instance[i].fw = NULL; 258 } 259 } 260 return err; 261 } 262 263 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring) 264 { 265 unsigned ret; 266 267 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 268 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 269 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 270 amdgpu_ring_write(ring, 1); 271 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 272 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 273 274 return ret; 275 } 276 277 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 278 unsigned offset) 279 { 280 unsigned cur; 281 282 BUG_ON(offset > ring->buf_mask); 283 BUG_ON(ring->ring[offset] != 0x55aa55aa); 284 285 cur = (ring->wptr - 1) & ring->buf_mask; 286 if (cur > offset) 287 ring->ring[offset] = cur - offset; 288 else 289 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 290 } 291 292 /** 293 * sdma_v5_0_ring_get_rptr - get the current read pointer 294 * 295 * @ring: amdgpu ring pointer 296 * 297 * Get the current rptr from the hardware (NAVI10+). 298 */ 299 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 300 { 301 u64 *rptr; 302 303 /* XXX check if swapping is necessary on BE */ 304 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 305 306 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 307 return ((*rptr) >> 2); 308 } 309 310 /** 311 * sdma_v5_0_ring_get_wptr - get the current write pointer 312 * 313 * @ring: amdgpu ring pointer 314 * 315 * Get the current wptr from the hardware (NAVI10+). 316 */ 317 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 318 { 319 struct amdgpu_device *adev = ring->adev; 320 u64 wptr; 321 322 if (ring->use_doorbell) { 323 /* XXX check if swapping is necessary on BE */ 324 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 325 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 326 } else { 327 wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 328 wptr = wptr << 32; 329 wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 330 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 331 } 332 333 return wptr >> 2; 334 } 335 336 /** 337 * sdma_v5_0_ring_set_wptr - commit the write pointer 338 * 339 * @ring: amdgpu ring pointer 340 * 341 * Write the wptr back to the hardware (NAVI10+). 342 */ 343 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 344 { 345 struct amdgpu_device *adev = ring->adev; 346 347 DRM_DEBUG("Setting write pointer\n"); 348 if (ring->use_doorbell) { 349 DRM_DEBUG("Using doorbell -- " 350 "wptr_offs == 0x%08x " 351 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 352 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 353 ring->wptr_offs, 354 lower_32_bits(ring->wptr << 2), 355 upper_32_bits(ring->wptr << 2)); 356 /* XXX check if swapping is necessary on BE */ 357 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 358 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 359 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 360 ring->doorbell_index, ring->wptr << 2); 361 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 362 } else { 363 DRM_DEBUG("Not using doorbell -- " 364 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 365 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 366 ring->me, 367 lower_32_bits(ring->wptr << 2), 368 ring->me, 369 upper_32_bits(ring->wptr << 2)); 370 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 371 lower_32_bits(ring->wptr << 2)); 372 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 373 upper_32_bits(ring->wptr << 2)); 374 } 375 } 376 377 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 378 { 379 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 380 int i; 381 382 for (i = 0; i < count; i++) 383 if (sdma && sdma->burst_nop && (i == 0)) 384 amdgpu_ring_write(ring, ring->funcs->nop | 385 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 386 else 387 amdgpu_ring_write(ring, ring->funcs->nop); 388 } 389 390 /** 391 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine 392 * 393 * @ring: amdgpu ring pointer 394 * @job: job to retrieve vmid from 395 * @ib: IB object to schedule 396 * @flags: unused 397 * 398 * Schedule an IB in the DMA ring (NAVI10). 399 */ 400 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 401 struct amdgpu_job *job, 402 struct amdgpu_ib *ib, 403 uint32_t flags) 404 { 405 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 406 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 407 408 /* Invalidate L2, because if we don't do it, we might get stale cache 409 * lines from previous IBs. 410 */ 411 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 412 amdgpu_ring_write(ring, 0); 413 amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV | 414 SDMA_GCR_GL2_WB | 415 SDMA_GCR_GLM_INV | 416 SDMA_GCR_GLM_WB) << 16); 417 amdgpu_ring_write(ring, 0xffffff80); 418 amdgpu_ring_write(ring, 0xffff); 419 420 /* An IB packet must end on a 8 DW boundary--the next dword 421 * must be on a 8-dword boundary. Our IB packet below is 6 422 * dwords long, thus add x number of NOPs, such that, in 423 * modular arithmetic, 424 * wptr + 6 + x = 8k, k >= 0, which in C is, 425 * (wptr + 6 + x) % 8 = 0. 426 * The expression below, is a solution of x. 427 */ 428 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 429 430 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 431 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 432 /* base must be 32 byte aligned */ 433 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 434 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 435 amdgpu_ring_write(ring, ib->length_dw); 436 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 437 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 438 } 439 440 /** 441 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 442 * 443 * @ring: amdgpu ring pointer 444 * 445 * Emit an hdp flush packet on the requested DMA ring. 446 */ 447 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 448 { 449 struct amdgpu_device *adev = ring->adev; 450 u32 ref_and_mask = 0; 451 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 452 453 if (ring->me == 0) 454 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 455 else 456 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 457 458 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 459 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 460 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 461 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 462 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 463 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 464 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 465 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 466 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 467 } 468 469 /** 470 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring 471 * 472 * @ring: amdgpu ring pointer 473 * @addr: address 474 * @seq: sequence number 475 * @flags: fence related flags 476 * 477 * Add a DMA fence packet to the ring to write 478 * the fence seq number and DMA trap packet to generate 479 * an interrupt if needed (NAVI10). 480 */ 481 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 482 unsigned flags) 483 { 484 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 485 /* write the fence */ 486 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 487 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 488 /* zero in first two bits */ 489 BUG_ON(addr & 0x3); 490 amdgpu_ring_write(ring, lower_32_bits(addr)); 491 amdgpu_ring_write(ring, upper_32_bits(addr)); 492 amdgpu_ring_write(ring, lower_32_bits(seq)); 493 494 /* optionally write high bits as well */ 495 if (write64bit) { 496 addr += 4; 497 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 498 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 499 /* zero in first two bits */ 500 BUG_ON(addr & 0x3); 501 amdgpu_ring_write(ring, lower_32_bits(addr)); 502 amdgpu_ring_write(ring, upper_32_bits(addr)); 503 amdgpu_ring_write(ring, upper_32_bits(seq)); 504 } 505 506 if (flags & AMDGPU_FENCE_FLAG_INT) { 507 /* generate an interrupt */ 508 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 509 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 510 } 511 } 512 513 514 /** 515 * sdma_v5_0_gfx_stop - stop the gfx async dma engines 516 * 517 * @adev: amdgpu_device pointer 518 * 519 * Stop the gfx async dma ring buffers (NAVI10). 520 */ 521 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev) 522 { 523 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 524 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 525 u32 rb_cntl, ib_cntl; 526 int i; 527 528 if ((adev->mman.buffer_funcs_ring == sdma0) || 529 (adev->mman.buffer_funcs_ring == sdma1)) 530 amdgpu_ttm_set_buffer_funcs_status(adev, false); 531 532 for (i = 0; i < adev->sdma.num_instances; i++) { 533 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 534 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 535 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 536 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 537 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 538 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 539 } 540 } 541 542 /** 543 * sdma_v5_0_rlc_stop - stop the compute async dma engines 544 * 545 * @adev: amdgpu_device pointer 546 * 547 * Stop the compute async dma queues (NAVI10). 548 */ 549 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) 550 { 551 /* XXX todo */ 552 } 553 554 /** 555 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 556 * 557 * @adev: amdgpu_device pointer 558 * @enable: enable/disable the DMA MEs context switch. 559 * 560 * Halt or unhalt the async dma engines context switch (NAVI10). 561 */ 562 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 563 { 564 u32 f32_cntl = 0, phase_quantum = 0; 565 int i; 566 567 if (amdgpu_sdma_phase_quantum) { 568 unsigned value = amdgpu_sdma_phase_quantum; 569 unsigned unit = 0; 570 571 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 572 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 573 value = (value + 1) >> 1; 574 unit++; 575 } 576 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 577 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 578 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 579 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 580 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 581 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 582 WARN_ONCE(1, 583 "clamping sdma_phase_quantum to %uK clock cycles\n", 584 value << unit); 585 } 586 phase_quantum = 587 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 588 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 589 } 590 591 for (i = 0; i < adev->sdma.num_instances; i++) { 592 if (!amdgpu_sriov_vf(adev)) { 593 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 595 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 596 } 597 598 if (enable && amdgpu_sdma_phase_quantum) { 599 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 600 phase_quantum); 601 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 602 phase_quantum); 603 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 604 phase_quantum); 605 } 606 if (!amdgpu_sriov_vf(adev)) 607 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 608 } 609 610 } 611 612 /** 613 * sdma_v5_0_enable - stop the async dma engines 614 * 615 * @adev: amdgpu_device pointer 616 * @enable: enable/disable the DMA MEs. 617 * 618 * Halt or unhalt the async dma engines (NAVI10). 619 */ 620 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) 621 { 622 u32 f32_cntl; 623 int i; 624 625 if (!enable) { 626 sdma_v5_0_gfx_stop(adev); 627 sdma_v5_0_rlc_stop(adev); 628 } 629 630 if (amdgpu_sriov_vf(adev)) 631 return; 632 633 for (i = 0; i < adev->sdma.num_instances; i++) { 634 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 635 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 636 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 637 } 638 } 639 640 /** 641 * sdma_v5_0_gfx_resume - setup and start the async dma engines 642 * 643 * @adev: amdgpu_device pointer 644 * 645 * Set up the gfx DMA ring buffers and enable them (NAVI10). 646 * Returns 0 for success, error for failure. 647 */ 648 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) 649 { 650 struct amdgpu_ring *ring; 651 u32 rb_cntl, ib_cntl; 652 u32 rb_bufsz; 653 u32 wb_offset; 654 u32 doorbell; 655 u32 doorbell_offset; 656 u32 temp; 657 u32 wptr_poll_cntl; 658 u64 wptr_gpu_addr; 659 int i, r; 660 661 for (i = 0; i < adev->sdma.num_instances; i++) { 662 ring = &adev->sdma.instance[i].ring; 663 wb_offset = (ring->rptr_offs * 4); 664 665 if (!amdgpu_sriov_vf(adev)) 666 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 667 668 /* Set ring buffer size in dwords */ 669 rb_bufsz = order_base_2(ring->ring_size / 4); 670 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 671 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 672 #ifdef __BIG_ENDIAN 673 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 674 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 675 RPTR_WRITEBACK_SWAP_ENABLE, 1); 676 #endif 677 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 678 679 /* Initialize the ring buffer's read and write pointers */ 680 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 681 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 682 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 683 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 684 685 /* setup the wptr shadow polling */ 686 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 687 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 688 lower_32_bits(wptr_gpu_addr)); 689 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 690 upper_32_bits(wptr_gpu_addr)); 691 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, 692 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 693 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 694 SDMA0_GFX_RB_WPTR_POLL_CNTL, 695 F32_POLL_ENABLE, 1); 696 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 697 wptr_poll_cntl); 698 699 /* set the wb address whether it's enabled or not */ 700 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 701 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 702 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 703 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 704 705 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 706 707 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 708 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 709 710 ring->wptr = 0; 711 712 /* before programing wptr to a less value, need set minor_ptr_update first */ 713 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 714 715 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 716 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 717 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 718 } 719 720 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 721 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 722 723 if (ring->use_doorbell) { 724 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 725 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 726 OFFSET, ring->doorbell_index); 727 } else { 728 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 729 } 730 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 731 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 732 733 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 734 ring->doorbell_index, 20); 735 736 if (amdgpu_sriov_vf(adev)) 737 sdma_v5_0_ring_set_wptr(ring); 738 739 /* set minor_ptr_update to 0 after wptr programed */ 740 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 741 742 if (!amdgpu_sriov_vf(adev)) { 743 /* set utc l1 enable flag always to 1 */ 744 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 745 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 746 747 /* enable MCBP */ 748 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 749 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 750 751 /* Set up RESP_MODE to non-copy addresses */ 752 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 753 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 754 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 755 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 756 757 /* program default cache read and write policy */ 758 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 759 /* clean read policy and write policy bits */ 760 temp &= 0xFF0FFF; 761 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 762 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 763 } 764 765 if (!amdgpu_sriov_vf(adev)) { 766 /* unhalt engine */ 767 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 768 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 769 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 770 } 771 772 /* enable DMA RB */ 773 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 774 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 775 776 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 777 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 778 #ifdef __BIG_ENDIAN 779 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 780 #endif 781 /* enable DMA IBs */ 782 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 783 784 ring->sched.ready = true; 785 786 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 787 sdma_v5_0_ctx_switch_enable(adev, true); 788 sdma_v5_0_enable(adev, true); 789 } 790 791 r = amdgpu_ring_test_helper(ring); 792 if (r) 793 return r; 794 795 if (adev->mman.buffer_funcs_ring == ring) 796 amdgpu_ttm_set_buffer_funcs_status(adev, true); 797 } 798 799 return 0; 800 } 801 802 /** 803 * sdma_v5_0_rlc_resume - setup and start the async dma engines 804 * 805 * @adev: amdgpu_device pointer 806 * 807 * Set up the compute DMA queues and enable them (NAVI10). 808 * Returns 0 for success, error for failure. 809 */ 810 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev) 811 { 812 return 0; 813 } 814 815 /** 816 * sdma_v5_0_load_microcode - load the sDMA ME ucode 817 * 818 * @adev: amdgpu_device pointer 819 * 820 * Loads the sDMA0/1 ucode. 821 * Returns 0 for success, -EINVAL if the ucode is not available. 822 */ 823 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev) 824 { 825 const struct sdma_firmware_header_v1_0 *hdr; 826 const __le32 *fw_data; 827 u32 fw_size; 828 int i, j; 829 830 /* halt the MEs */ 831 sdma_v5_0_enable(adev, false); 832 833 for (i = 0; i < adev->sdma.num_instances; i++) { 834 if (!adev->sdma.instance[i].fw) 835 return -EINVAL; 836 837 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 838 amdgpu_ucode_print_sdma_hdr(&hdr->header); 839 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 840 841 fw_data = (const __le32 *) 842 (adev->sdma.instance[i].fw->data + 843 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 844 845 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 846 847 for (j = 0; j < fw_size; j++) { 848 if (amdgpu_emu_mode == 1 && j % 500 == 0) 849 msleep(1); 850 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 851 } 852 853 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 854 } 855 856 return 0; 857 } 858 859 /** 860 * sdma_v5_0_start - setup and start the async dma engines 861 * 862 * @adev: amdgpu_device pointer 863 * 864 * Set up the DMA engines and enable them (NAVI10). 865 * Returns 0 for success, error for failure. 866 */ 867 static int sdma_v5_0_start(struct amdgpu_device *adev) 868 { 869 int r = 0; 870 871 if (amdgpu_sriov_vf(adev)) { 872 sdma_v5_0_ctx_switch_enable(adev, false); 873 sdma_v5_0_enable(adev, false); 874 875 /* set RB registers */ 876 r = sdma_v5_0_gfx_resume(adev); 877 return r; 878 } 879 880 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 881 r = sdma_v5_0_load_microcode(adev); 882 if (r) 883 return r; 884 } 885 886 /* unhalt the MEs */ 887 sdma_v5_0_enable(adev, true); 888 /* enable sdma ring preemption */ 889 sdma_v5_0_ctx_switch_enable(adev, true); 890 891 /* start the gfx rings and rlc compute queues */ 892 r = sdma_v5_0_gfx_resume(adev); 893 if (r) 894 return r; 895 r = sdma_v5_0_rlc_resume(adev); 896 897 return r; 898 } 899 900 /** 901 * sdma_v5_0_ring_test_ring - simple async dma engine test 902 * 903 * @ring: amdgpu_ring structure holding ring information 904 * 905 * Test the DMA engine by writing using it to write an 906 * value to memory. (NAVI10). 907 * Returns 0 for success, error for failure. 908 */ 909 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) 910 { 911 struct amdgpu_device *adev = ring->adev; 912 unsigned i; 913 unsigned index; 914 int r; 915 u32 tmp; 916 u64 gpu_addr; 917 918 r = amdgpu_device_wb_get(adev, &index); 919 if (r) { 920 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 921 return r; 922 } 923 924 gpu_addr = adev->wb.gpu_addr + (index * 4); 925 tmp = 0xCAFEDEAD; 926 adev->wb.wb[index] = cpu_to_le32(tmp); 927 928 r = amdgpu_ring_alloc(ring, 5); 929 if (r) { 930 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 931 amdgpu_device_wb_free(adev, index); 932 return r; 933 } 934 935 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 936 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 937 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 938 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 939 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 940 amdgpu_ring_write(ring, 0xDEADBEEF); 941 amdgpu_ring_commit(ring); 942 943 for (i = 0; i < adev->usec_timeout; i++) { 944 tmp = le32_to_cpu(adev->wb.wb[index]); 945 if (tmp == 0xDEADBEEF) 946 break; 947 if (amdgpu_emu_mode == 1) 948 msleep(1); 949 else 950 udelay(1); 951 } 952 953 if (i >= adev->usec_timeout) 954 r = -ETIMEDOUT; 955 956 amdgpu_device_wb_free(adev, index); 957 958 return r; 959 } 960 961 /** 962 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine 963 * 964 * @ring: amdgpu_ring structure holding ring information 965 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 966 * 967 * Test a simple IB in the DMA ring (NAVI10). 968 * Returns 0 on success, error on failure. 969 */ 970 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 971 { 972 struct amdgpu_device *adev = ring->adev; 973 struct amdgpu_ib ib; 974 struct dma_fence *f = NULL; 975 unsigned index; 976 long r; 977 u32 tmp = 0; 978 u64 gpu_addr; 979 980 r = amdgpu_device_wb_get(adev, &index); 981 if (r) { 982 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 983 return r; 984 } 985 986 gpu_addr = adev->wb.gpu_addr + (index * 4); 987 tmp = 0xCAFEDEAD; 988 adev->wb.wb[index] = cpu_to_le32(tmp); 989 memset(&ib, 0, sizeof(ib)); 990 r = amdgpu_ib_get(adev, NULL, 256, 991 AMDGPU_IB_POOL_DIRECT, &ib); 992 if (r) { 993 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 994 goto err0; 995 } 996 997 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 998 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 999 ib.ptr[1] = lower_32_bits(gpu_addr); 1000 ib.ptr[2] = upper_32_bits(gpu_addr); 1001 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1002 ib.ptr[4] = 0xDEADBEEF; 1003 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1004 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1005 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1006 ib.length_dw = 8; 1007 1008 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1009 if (r) 1010 goto err1; 1011 1012 r = dma_fence_wait_timeout(f, false, timeout); 1013 if (r == 0) { 1014 DRM_ERROR("amdgpu: IB test timed out\n"); 1015 r = -ETIMEDOUT; 1016 goto err1; 1017 } else if (r < 0) { 1018 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1019 goto err1; 1020 } 1021 tmp = le32_to_cpu(adev->wb.wb[index]); 1022 if (tmp == 0xDEADBEEF) 1023 r = 0; 1024 else 1025 r = -EINVAL; 1026 1027 err1: 1028 amdgpu_ib_free(adev, &ib, NULL); 1029 dma_fence_put(f); 1030 err0: 1031 amdgpu_device_wb_free(adev, index); 1032 return r; 1033 } 1034 1035 1036 /** 1037 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART 1038 * 1039 * @ib: indirect buffer to fill with commands 1040 * @pe: addr of the page entry 1041 * @src: src addr to copy from 1042 * @count: number of page entries to update 1043 * 1044 * Update PTEs by copying them from the GART using sDMA (NAVI10). 1045 */ 1046 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib, 1047 uint64_t pe, uint64_t src, 1048 unsigned count) 1049 { 1050 unsigned bytes = count * 8; 1051 1052 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1053 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1054 ib->ptr[ib->length_dw++] = bytes - 1; 1055 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1056 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1057 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1058 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1059 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1060 1061 } 1062 1063 /** 1064 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually 1065 * 1066 * @ib: indirect buffer to fill with commands 1067 * @pe: addr of the page entry 1068 * @value: dst addr to write into pe 1069 * @count: number of page entries to update 1070 * @incr: increase next addr by incr bytes 1071 * 1072 * Update PTEs by writing them manually using sDMA (NAVI10). 1073 */ 1074 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1075 uint64_t value, unsigned count, 1076 uint32_t incr) 1077 { 1078 unsigned ndw = count * 2; 1079 1080 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1081 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1082 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1083 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1084 ib->ptr[ib->length_dw++] = ndw - 1; 1085 for (; ndw > 0; ndw -= 2) { 1086 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1087 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1088 value += incr; 1089 } 1090 } 1091 1092 /** 1093 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA 1094 * 1095 * @ib: indirect buffer to fill with commands 1096 * @pe: addr of the page entry 1097 * @addr: dst addr to write into pe 1098 * @count: number of page entries to update 1099 * @incr: increase next addr by incr bytes 1100 * @flags: access flags 1101 * 1102 * Update the page tables using sDMA (NAVI10). 1103 */ 1104 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1105 uint64_t pe, 1106 uint64_t addr, unsigned count, 1107 uint32_t incr, uint64_t flags) 1108 { 1109 /* for physically contiguous pages (vram) */ 1110 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1111 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1112 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1113 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1114 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1115 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1116 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1117 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1118 ib->ptr[ib->length_dw++] = 0; 1119 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1120 } 1121 1122 /** 1123 * sdma_v5_0_ring_pad_ib - pad the IB 1124 * @ring: amdgpu_ring structure holding ring information 1125 * @ib: indirect buffer to fill with padding 1126 * 1127 * Pad the IB with NOPs to a boundary multiple of 8. 1128 */ 1129 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1130 { 1131 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1132 u32 pad_count; 1133 int i; 1134 1135 pad_count = (-ib->length_dw) & 0x7; 1136 for (i = 0; i < pad_count; i++) 1137 if (sdma && sdma->burst_nop && (i == 0)) 1138 ib->ptr[ib->length_dw++] = 1139 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1140 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1141 else 1142 ib->ptr[ib->length_dw++] = 1143 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1144 } 1145 1146 1147 /** 1148 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline 1149 * 1150 * @ring: amdgpu_ring pointer 1151 * 1152 * Make sure all previous operations are completed (CIK). 1153 */ 1154 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1155 { 1156 uint32_t seq = ring->fence_drv.sync_seq; 1157 uint64_t addr = ring->fence_drv.gpu_addr; 1158 1159 /* wait for idle */ 1160 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1161 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1162 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1163 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1164 amdgpu_ring_write(ring, addr & 0xfffffffc); 1165 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1166 amdgpu_ring_write(ring, seq); /* reference */ 1167 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1168 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1169 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1170 } 1171 1172 1173 /** 1174 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA 1175 * 1176 * @ring: amdgpu_ring pointer 1177 * @vmid: vmid number to use 1178 * @pd_addr: address 1179 * 1180 * Update the page table base and flush the VM TLB 1181 * using sDMA (NAVI10). 1182 */ 1183 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1184 unsigned vmid, uint64_t pd_addr) 1185 { 1186 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1187 } 1188 1189 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring, 1190 uint32_t reg, uint32_t val) 1191 { 1192 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1193 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1194 amdgpu_ring_write(ring, reg); 1195 amdgpu_ring_write(ring, val); 1196 } 1197 1198 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1199 uint32_t val, uint32_t mask) 1200 { 1201 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1202 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1203 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1204 amdgpu_ring_write(ring, reg << 2); 1205 amdgpu_ring_write(ring, 0); 1206 amdgpu_ring_write(ring, val); /* reference */ 1207 amdgpu_ring_write(ring, mask); /* mask */ 1208 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1209 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1210 } 1211 1212 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1213 uint32_t reg0, uint32_t reg1, 1214 uint32_t ref, uint32_t mask) 1215 { 1216 amdgpu_ring_emit_wreg(ring, reg0, ref); 1217 /* wait for a cycle to reset vm_inv_eng*_ack */ 1218 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1219 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1220 } 1221 1222 static int sdma_v5_0_early_init(void *handle) 1223 { 1224 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1225 1226 adev->sdma.num_instances = 2; 1227 1228 sdma_v5_0_set_ring_funcs(adev); 1229 sdma_v5_0_set_buffer_funcs(adev); 1230 sdma_v5_0_set_vm_pte_funcs(adev); 1231 sdma_v5_0_set_irq_funcs(adev); 1232 1233 return 0; 1234 } 1235 1236 1237 static int sdma_v5_0_sw_init(void *handle) 1238 { 1239 struct amdgpu_ring *ring; 1240 int r, i; 1241 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1242 1243 /* SDMA trap event */ 1244 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 1245 SDMA0_5_0__SRCID__SDMA_TRAP, 1246 &adev->sdma.trap_irq); 1247 if (r) 1248 return r; 1249 1250 /* SDMA trap event */ 1251 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 1252 SDMA1_5_0__SRCID__SDMA_TRAP, 1253 &adev->sdma.trap_irq); 1254 if (r) 1255 return r; 1256 1257 r = sdma_v5_0_init_microcode(adev); 1258 if (r) { 1259 DRM_ERROR("Failed to load sdma firmware!\n"); 1260 return r; 1261 } 1262 1263 for (i = 0; i < adev->sdma.num_instances; i++) { 1264 ring = &adev->sdma.instance[i].ring; 1265 ring->ring_obj = NULL; 1266 ring->use_doorbell = true; 1267 1268 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1269 ring->use_doorbell?"true":"false"); 1270 1271 ring->doorbell_index = (i == 0) ? 1272 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset 1273 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset 1274 1275 sprintf(ring->name, "sdma%d", i); 1276 r = amdgpu_ring_init(adev, ring, 1024, 1277 &adev->sdma.trap_irq, 1278 (i == 0) ? 1279 AMDGPU_SDMA_IRQ_INSTANCE0 : 1280 AMDGPU_SDMA_IRQ_INSTANCE1, 1281 AMDGPU_RING_PRIO_DEFAULT); 1282 if (r) 1283 return r; 1284 } 1285 1286 return r; 1287 } 1288 1289 static int sdma_v5_0_sw_fini(void *handle) 1290 { 1291 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1292 int i; 1293 1294 for (i = 0; i < adev->sdma.num_instances; i++) { 1295 release_firmware(adev->sdma.instance[i].fw); 1296 adev->sdma.instance[i].fw = NULL; 1297 1298 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1299 } 1300 1301 return 0; 1302 } 1303 1304 static int sdma_v5_0_hw_init(void *handle) 1305 { 1306 int r; 1307 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1308 1309 sdma_v5_0_init_golden_registers(adev); 1310 1311 r = sdma_v5_0_start(adev); 1312 1313 return r; 1314 } 1315 1316 static int sdma_v5_0_hw_fini(void *handle) 1317 { 1318 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1319 1320 if (amdgpu_sriov_vf(adev)) 1321 return 0; 1322 1323 sdma_v5_0_ctx_switch_enable(adev, false); 1324 sdma_v5_0_enable(adev, false); 1325 1326 return 0; 1327 } 1328 1329 static int sdma_v5_0_suspend(void *handle) 1330 { 1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1332 1333 return sdma_v5_0_hw_fini(adev); 1334 } 1335 1336 static int sdma_v5_0_resume(void *handle) 1337 { 1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1339 1340 return sdma_v5_0_hw_init(adev); 1341 } 1342 1343 static bool sdma_v5_0_is_idle(void *handle) 1344 { 1345 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1346 u32 i; 1347 1348 for (i = 0; i < adev->sdma.num_instances; i++) { 1349 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1350 1351 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1352 return false; 1353 } 1354 1355 return true; 1356 } 1357 1358 static int sdma_v5_0_wait_for_idle(void *handle) 1359 { 1360 unsigned i; 1361 u32 sdma0, sdma1; 1362 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1363 1364 for (i = 0; i < adev->usec_timeout; i++) { 1365 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1366 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1367 1368 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1369 return 0; 1370 udelay(1); 1371 } 1372 return -ETIMEDOUT; 1373 } 1374 1375 static int sdma_v5_0_soft_reset(void *handle) 1376 { 1377 /* todo */ 1378 1379 return 0; 1380 } 1381 1382 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring) 1383 { 1384 int i, r = 0; 1385 struct amdgpu_device *adev = ring->adev; 1386 u32 index = 0; 1387 u64 sdma_gfx_preempt; 1388 1389 amdgpu_sdma_get_index_from_ring(ring, &index); 1390 if (index == 0) 1391 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT; 1392 else 1393 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT; 1394 1395 /* assert preemption condition */ 1396 amdgpu_ring_set_preempt_cond_exec(ring, false); 1397 1398 /* emit the trailing fence */ 1399 ring->trail_seq += 1; 1400 amdgpu_ring_alloc(ring, 10); 1401 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1402 ring->trail_seq, 0); 1403 amdgpu_ring_commit(ring); 1404 1405 /* assert IB preemption */ 1406 WREG32(sdma_gfx_preempt, 1); 1407 1408 /* poll the trailing fence */ 1409 for (i = 0; i < adev->usec_timeout; i++) { 1410 if (ring->trail_seq == 1411 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1412 break; 1413 udelay(1); 1414 } 1415 1416 if (i >= adev->usec_timeout) { 1417 r = -EINVAL; 1418 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1419 } 1420 1421 /* deassert IB preemption */ 1422 WREG32(sdma_gfx_preempt, 0); 1423 1424 /* deassert the preemption condition */ 1425 amdgpu_ring_set_preempt_cond_exec(ring, true); 1426 return r; 1427 } 1428 1429 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev, 1430 struct amdgpu_irq_src *source, 1431 unsigned type, 1432 enum amdgpu_interrupt_state state) 1433 { 1434 u32 sdma_cntl; 1435 1436 if (!amdgpu_sriov_vf(adev)) { 1437 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? 1438 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1439 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1440 1441 sdma_cntl = RREG32(reg_offset); 1442 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1443 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1444 WREG32(reg_offset, sdma_cntl); 1445 } 1446 1447 return 0; 1448 } 1449 1450 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, 1451 struct amdgpu_irq_src *source, 1452 struct amdgpu_iv_entry *entry) 1453 { 1454 DRM_DEBUG("IH: SDMA trap\n"); 1455 switch (entry->client_id) { 1456 case SOC15_IH_CLIENTID_SDMA0: 1457 switch (entry->ring_id) { 1458 case 0: 1459 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1460 break; 1461 case 1: 1462 /* XXX compute */ 1463 break; 1464 case 2: 1465 /* XXX compute */ 1466 break; 1467 case 3: 1468 /* XXX page queue*/ 1469 break; 1470 } 1471 break; 1472 case SOC15_IH_CLIENTID_SDMA1: 1473 switch (entry->ring_id) { 1474 case 0: 1475 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1476 break; 1477 case 1: 1478 /* XXX compute */ 1479 break; 1480 case 2: 1481 /* XXX compute */ 1482 break; 1483 case 3: 1484 /* XXX page queue*/ 1485 break; 1486 } 1487 break; 1488 } 1489 return 0; 1490 } 1491 1492 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1493 struct amdgpu_irq_src *source, 1494 struct amdgpu_iv_entry *entry) 1495 { 1496 return 0; 1497 } 1498 1499 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1500 bool enable) 1501 { 1502 uint32_t data, def; 1503 int i; 1504 1505 for (i = 0; i < adev->sdma.num_instances; i++) { 1506 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1507 /* Enable sdma clock gating */ 1508 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1509 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1510 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1511 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1512 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1513 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1514 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1515 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1516 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1517 if (def != data) 1518 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1519 } else { 1520 /* Disable sdma clock gating */ 1521 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1522 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1523 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1524 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1525 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1526 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1527 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1528 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1529 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1530 if (def != data) 1531 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1532 } 1533 } 1534 } 1535 1536 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1537 bool enable) 1538 { 1539 uint32_t data, def; 1540 int i; 1541 1542 for (i = 0; i < adev->sdma.num_instances; i++) { 1543 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1544 /* Enable sdma mem light sleep */ 1545 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1546 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1547 if (def != data) 1548 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1549 1550 } else { 1551 /* Disable sdma mem light sleep */ 1552 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1553 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1554 if (def != data) 1555 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1556 1557 } 1558 } 1559 } 1560 1561 static int sdma_v5_0_set_clockgating_state(void *handle, 1562 enum amd_clockgating_state state) 1563 { 1564 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1565 1566 if (amdgpu_sriov_vf(adev)) 1567 return 0; 1568 1569 switch (adev->asic_type) { 1570 case CHIP_NAVI10: 1571 case CHIP_NAVI14: 1572 case CHIP_NAVI12: 1573 sdma_v5_0_update_medium_grain_clock_gating(adev, 1574 state == AMD_CG_STATE_GATE); 1575 sdma_v5_0_update_medium_grain_light_sleep(adev, 1576 state == AMD_CG_STATE_GATE); 1577 break; 1578 default: 1579 break; 1580 } 1581 1582 return 0; 1583 } 1584 1585 static int sdma_v5_0_set_powergating_state(void *handle, 1586 enum amd_powergating_state state) 1587 { 1588 return 0; 1589 } 1590 1591 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags) 1592 { 1593 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1594 int data; 1595 1596 if (amdgpu_sriov_vf(adev)) 1597 *flags = 0; 1598 1599 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1600 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1601 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1602 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1603 1604 /* AMD_CG_SUPPORT_SDMA_LS */ 1605 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1606 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1607 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1608 } 1609 1610 const struct amd_ip_funcs sdma_v5_0_ip_funcs = { 1611 .name = "sdma_v5_0", 1612 .early_init = sdma_v5_0_early_init, 1613 .late_init = NULL, 1614 .sw_init = sdma_v5_0_sw_init, 1615 .sw_fini = sdma_v5_0_sw_fini, 1616 .hw_init = sdma_v5_0_hw_init, 1617 .hw_fini = sdma_v5_0_hw_fini, 1618 .suspend = sdma_v5_0_suspend, 1619 .resume = sdma_v5_0_resume, 1620 .is_idle = sdma_v5_0_is_idle, 1621 .wait_for_idle = sdma_v5_0_wait_for_idle, 1622 .soft_reset = sdma_v5_0_soft_reset, 1623 .set_clockgating_state = sdma_v5_0_set_clockgating_state, 1624 .set_powergating_state = sdma_v5_0_set_powergating_state, 1625 .get_clockgating_state = sdma_v5_0_get_clockgating_state, 1626 }; 1627 1628 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 1629 .type = AMDGPU_RING_TYPE_SDMA, 1630 .align_mask = 0xf, 1631 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1632 .support_64bit_ptrs = true, 1633 .vmhub = AMDGPU_GFXHUB_0, 1634 .get_rptr = sdma_v5_0_ring_get_rptr, 1635 .get_wptr = sdma_v5_0_ring_get_wptr, 1636 .set_wptr = sdma_v5_0_ring_set_wptr, 1637 .emit_frame_size = 1638 5 + /* sdma_v5_0_ring_init_cond_exec */ 1639 6 + /* sdma_v5_0_ring_emit_hdp_flush */ 1640 3 + /* hdp_invalidate */ 1641 6 + /* sdma_v5_0_ring_emit_pipeline_sync */ 1642 /* sdma_v5_0_ring_emit_vm_flush */ 1643 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1644 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 + 1645 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ 1646 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */ 1647 .emit_ib = sdma_v5_0_ring_emit_ib, 1648 .emit_fence = sdma_v5_0_ring_emit_fence, 1649 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync, 1650 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush, 1651 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush, 1652 .test_ring = sdma_v5_0_ring_test_ring, 1653 .test_ib = sdma_v5_0_ring_test_ib, 1654 .insert_nop = sdma_v5_0_ring_insert_nop, 1655 .pad_ib = sdma_v5_0_ring_pad_ib, 1656 .emit_wreg = sdma_v5_0_ring_emit_wreg, 1657 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait, 1658 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait, 1659 .init_cond_exec = sdma_v5_0_ring_init_cond_exec, 1660 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec, 1661 .preempt_ib = sdma_v5_0_ring_preempt_ib, 1662 }; 1663 1664 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) 1665 { 1666 int i; 1667 1668 for (i = 0; i < adev->sdma.num_instances; i++) { 1669 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; 1670 adev->sdma.instance[i].ring.me = i; 1671 } 1672 } 1673 1674 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = { 1675 .set = sdma_v5_0_set_trap_irq_state, 1676 .process = sdma_v5_0_process_trap_irq, 1677 }; 1678 1679 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = { 1680 .process = sdma_v5_0_process_illegal_inst_irq, 1681 }; 1682 1683 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev) 1684 { 1685 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1686 adev->sdma.num_instances; 1687 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; 1688 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; 1689 } 1690 1691 /** 1692 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine 1693 * 1694 * @ib: indirect buffer to copy to 1695 * @src_offset: src GPU address 1696 * @dst_offset: dst GPU address 1697 * @byte_count: number of bytes to xfer 1698 * @tmz: if a secure copy should be used 1699 * 1700 * Copy GPU buffers using the DMA engine (NAVI10). 1701 * Used by the amdgpu ttm implementation to move pages if 1702 * registered as the asic copy callback. 1703 */ 1704 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib, 1705 uint64_t src_offset, 1706 uint64_t dst_offset, 1707 uint32_t byte_count, 1708 bool tmz) 1709 { 1710 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1711 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1712 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1713 ib->ptr[ib->length_dw++] = byte_count - 1; 1714 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1715 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1716 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1717 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1718 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1719 } 1720 1721 /** 1722 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine 1723 * 1724 * @ib: indirect buffer to fill 1725 * @src_data: value to write to buffer 1726 * @dst_offset: dst GPU address 1727 * @byte_count: number of bytes to xfer 1728 * 1729 * Fill GPU buffers using the DMA engine (NAVI10). 1730 */ 1731 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib, 1732 uint32_t src_data, 1733 uint64_t dst_offset, 1734 uint32_t byte_count) 1735 { 1736 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1737 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1738 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1739 ib->ptr[ib->length_dw++] = src_data; 1740 ib->ptr[ib->length_dw++] = byte_count - 1; 1741 } 1742 1743 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { 1744 .copy_max_bytes = 0x400000, 1745 .copy_num_dw = 7, 1746 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer, 1747 1748 .fill_max_bytes = 0x400000, 1749 .fill_num_dw = 5, 1750 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer, 1751 }; 1752 1753 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) 1754 { 1755 if (adev->mman.buffer_funcs == NULL) { 1756 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; 1757 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1758 } 1759 } 1760 1761 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 1762 .copy_pte_num_dw = 7, 1763 .copy_pte = sdma_v5_0_vm_copy_pte, 1764 .write_pte = sdma_v5_0_vm_write_pte, 1765 .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 1766 }; 1767 1768 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1769 { 1770 unsigned i; 1771 1772 if (adev->vm_manager.vm_pte_funcs == NULL) { 1773 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; 1774 for (i = 0; i < adev->sdma.num_instances; i++) { 1775 adev->vm_manager.vm_pte_scheds[i] = 1776 &adev->sdma.instance[i].ring.sched; 1777 } 1778 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1779 } 1780 } 1781 1782 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { 1783 .type = AMD_IP_BLOCK_TYPE_SDMA, 1784 .major = 5, 1785 .minor = 0, 1786 .rev = 0, 1787 .funcs = &sdma_v5_0_ip_funcs, 1788 }; 1789