1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_1_0_offset.h" 34 #include "gc/gc_10_1_0_sh_mask.h" 35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 37 38 #include "soc15_common.h" 39 #include "soc15.h" 40 #include "navi10_sdma_pkt_open.h" 41 #include "nbio_v2_3.h" 42 #include "sdma_common.h" 43 #include "sdma_v5_0.h" 44 45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); 47 48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); 50 51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin"); 53 54 MODULE_FIRMWARE("amdgpu/cyan_skillfish_sdma.bin"); 55 MODULE_FIRMWARE("amdgpu/cyan_skillfish_sdma1.bin"); 56 57 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma.bin"); 58 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_sdma1.bin"); 59 60 #define SDMA1_REG_OFFSET 0x600 61 #define SDMA0_HYP_DEC_REG_START 0x5880 62 #define SDMA0_HYP_DEC_REG_END 0x5893 63 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 64 65 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); 66 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); 67 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); 68 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); 69 70 static const struct soc15_reg_golden golden_settings_sdma_5[] = { 71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00), 83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00) 95 }; 96 97 static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = { 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 118 }; 119 120 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { 121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 123 }; 124 125 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = { 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 128 }; 129 130 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = { 131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 137 }; 138 139 static const struct soc15_reg_golden golden_settings_sdma_cyan_skillfish[] = { 140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x007fffff, 0x004c5c00), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), 156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), 157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x007fffff, 0x004c5c00) 168 }; 169 170 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 171 { 172 u32 base; 173 174 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 175 internal_offset <= SDMA0_HYP_DEC_REG_END) { 176 base = adev->reg_offset[GC_HWIP][0][1]; 177 if (instance == 1) 178 internal_offset += SDMA1_HYP_DEC_REG_OFFSET; 179 } else { 180 base = adev->reg_offset[GC_HWIP][0][0]; 181 if (instance == 1) 182 internal_offset += SDMA1_REG_OFFSET; 183 } 184 185 return base + internal_offset; 186 } 187 188 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) 189 { 190 switch (adev->ip_versions[SDMA0_HWIP][0]) { 191 case IP_VERSION(5, 0, 0): 192 soc15_program_register_sequence(adev, 193 golden_settings_sdma_5, 194 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 195 soc15_program_register_sequence(adev, 196 golden_settings_sdma_nv10, 197 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); 198 break; 199 case IP_VERSION(5, 0, 2): 200 soc15_program_register_sequence(adev, 201 golden_settings_sdma_5, 202 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 203 soc15_program_register_sequence(adev, 204 golden_settings_sdma_nv14, 205 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14)); 206 break; 207 case IP_VERSION(5, 0, 5): 208 if (amdgpu_sriov_vf(adev)) 209 soc15_program_register_sequence(adev, 210 golden_settings_sdma_5_sriov, 211 (const u32)ARRAY_SIZE(golden_settings_sdma_5_sriov)); 212 else 213 soc15_program_register_sequence(adev, 214 golden_settings_sdma_5, 215 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 216 soc15_program_register_sequence(adev, 217 golden_settings_sdma_nv12, 218 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12)); 219 break; 220 case IP_VERSION(5, 0, 1): 221 soc15_program_register_sequence(adev, 222 golden_settings_sdma_cyan_skillfish, 223 (const u32)ARRAY_SIZE(golden_settings_sdma_cyan_skillfish)); 224 break; 225 default: 226 break; 227 } 228 } 229 230 /** 231 * sdma_v5_0_init_microcode - load ucode images from disk 232 * 233 * @adev: amdgpu_device pointer 234 * 235 * Use the firmware interface to load the ucode images into 236 * the driver (not loaded into hw). 237 * Returns 0 on success, error on failure. 238 */ 239 240 // emulation only, won't work on real chip 241 // navi10 real chip need to use PSP to load firmware 242 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) 243 { 244 const char *chip_name; 245 char fw_name[40]; 246 int err = 0, i; 247 struct amdgpu_firmware_info *info = NULL; 248 const struct common_firmware_header *header = NULL; 249 const struct sdma_firmware_header_v1_0 *hdr; 250 251 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5))) 252 return 0; 253 254 DRM_DEBUG("\n"); 255 256 switch (adev->ip_versions[SDMA0_HWIP][0]) { 257 case IP_VERSION(5, 0, 0): 258 chip_name = "navi10"; 259 break; 260 case IP_VERSION(5, 0, 2): 261 chip_name = "navi14"; 262 break; 263 case IP_VERSION(5, 0, 5): 264 chip_name = "navi12"; 265 break; 266 case IP_VERSION(5, 0, 1): 267 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 268 chip_name = "cyan_skillfish2"; 269 else 270 chip_name = "cyan_skillfish"; 271 break; 272 default: 273 BUG(); 274 } 275 276 for (i = 0; i < adev->sdma.num_instances; i++) { 277 if (i == 0) 278 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 279 else 280 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 281 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 282 if (err) 283 goto out; 284 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 285 if (err) 286 goto out; 287 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 288 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 289 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 290 if (adev->sdma.instance[i].feature_version >= 20) 291 adev->sdma.instance[i].burst_nop = true; 292 DRM_DEBUG("psp_load == '%s'\n", 293 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 294 295 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 296 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 297 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 298 info->fw = adev->sdma.instance[i].fw; 299 header = (const struct common_firmware_header *)info->fw->data; 300 adev->firmware.fw_size += 301 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 302 } 303 } 304 out: 305 if (err) { 306 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name); 307 for (i = 0; i < adev->sdma.num_instances; i++) { 308 release_firmware(adev->sdma.instance[i].fw); 309 adev->sdma.instance[i].fw = NULL; 310 } 311 } 312 return err; 313 } 314 315 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring) 316 { 317 unsigned ret; 318 319 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 320 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 321 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 322 amdgpu_ring_write(ring, 1); 323 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 324 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 325 326 return ret; 327 } 328 329 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 330 unsigned offset) 331 { 332 unsigned cur; 333 334 BUG_ON(offset > ring->buf_mask); 335 BUG_ON(ring->ring[offset] != 0x55aa55aa); 336 337 cur = (ring->wptr - 1) & ring->buf_mask; 338 if (cur > offset) 339 ring->ring[offset] = cur - offset; 340 else 341 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 342 } 343 344 /** 345 * sdma_v5_0_ring_get_rptr - get the current read pointer 346 * 347 * @ring: amdgpu ring pointer 348 * 349 * Get the current rptr from the hardware (NAVI10+). 350 */ 351 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 352 { 353 u64 *rptr; 354 355 /* XXX check if swapping is necessary on BE */ 356 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 357 358 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 359 return ((*rptr) >> 2); 360 } 361 362 /** 363 * sdma_v5_0_ring_get_wptr - get the current write pointer 364 * 365 * @ring: amdgpu ring pointer 366 * 367 * Get the current wptr from the hardware (NAVI10+). 368 */ 369 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 370 { 371 struct amdgpu_device *adev = ring->adev; 372 u64 wptr; 373 374 if (ring->use_doorbell) { 375 /* XXX check if swapping is necessary on BE */ 376 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 377 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 378 } else { 379 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 380 wptr = wptr << 32; 381 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 382 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 383 } 384 385 return wptr >> 2; 386 } 387 388 /** 389 * sdma_v5_0_ring_set_wptr - commit the write pointer 390 * 391 * @ring: amdgpu ring pointer 392 * 393 * Write the wptr back to the hardware (NAVI10+). 394 */ 395 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 396 { 397 struct amdgpu_device *adev = ring->adev; 398 399 DRM_DEBUG("Setting write pointer\n"); 400 if (ring->use_doorbell) { 401 DRM_DEBUG("Using doorbell -- " 402 "wptr_offs == 0x%08x " 403 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 404 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 405 ring->wptr_offs, 406 lower_32_bits(ring->wptr << 2), 407 upper_32_bits(ring->wptr << 2)); 408 /* XXX check if swapping is necessary on BE */ 409 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 410 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 411 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 412 ring->doorbell_index, ring->wptr << 2); 413 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 414 } else { 415 DRM_DEBUG("Not using doorbell -- " 416 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 417 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 418 ring->me, 419 lower_32_bits(ring->wptr << 2), 420 ring->me, 421 upper_32_bits(ring->wptr << 2)); 422 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 423 lower_32_bits(ring->wptr << 2)); 424 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 425 upper_32_bits(ring->wptr << 2)); 426 } 427 } 428 429 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 430 { 431 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 432 int i; 433 434 for (i = 0; i < count; i++) 435 if (sdma && sdma->burst_nop && (i == 0)) 436 amdgpu_ring_write(ring, ring->funcs->nop | 437 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 438 else 439 amdgpu_ring_write(ring, ring->funcs->nop); 440 } 441 442 /** 443 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine 444 * 445 * @ring: amdgpu ring pointer 446 * @job: job to retrieve vmid from 447 * @ib: IB object to schedule 448 * @flags: unused 449 * 450 * Schedule an IB in the DMA ring (NAVI10). 451 */ 452 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 453 struct amdgpu_job *job, 454 struct amdgpu_ib *ib, 455 uint32_t flags) 456 { 457 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 458 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 459 460 /* An IB packet must end on a 8 DW boundary--the next dword 461 * must be on a 8-dword boundary. Our IB packet below is 6 462 * dwords long, thus add x number of NOPs, such that, in 463 * modular arithmetic, 464 * wptr + 6 + x = 8k, k >= 0, which in C is, 465 * (wptr + 6 + x) % 8 = 0. 466 * The expression below, is a solution of x. 467 */ 468 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 469 470 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 471 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 472 /* base must be 32 byte aligned */ 473 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 474 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 475 amdgpu_ring_write(ring, ib->length_dw); 476 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 477 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 478 } 479 480 /** 481 * sdma_v5_0_ring_emit_mem_sync - flush the IB by graphics cache rinse 482 * 483 * @ring: amdgpu ring pointer 484 * @job: job to retrieve vmid from 485 * @ib: IB object to schedule 486 * 487 * flush the IB by graphics cache rinse. 488 */ 489 static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring) 490 { 491 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | 492 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | 493 SDMA_GCR_GLI_INV(1); 494 495 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ 496 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 497 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); 498 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | 499 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); 500 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | 501 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); 502 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | 503 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); 504 } 505 506 /** 507 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 508 * 509 * @ring: amdgpu ring pointer 510 * 511 * Emit an hdp flush packet on the requested DMA ring. 512 */ 513 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 514 { 515 struct amdgpu_device *adev = ring->adev; 516 u32 ref_and_mask = 0; 517 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 518 519 if (ring->me == 0) 520 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 521 else 522 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 523 524 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 525 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 526 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 527 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 528 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 529 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 530 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 531 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 532 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 533 } 534 535 /** 536 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring 537 * 538 * @ring: amdgpu ring pointer 539 * @addr: address 540 * @seq: sequence number 541 * @flags: fence related flags 542 * 543 * Add a DMA fence packet to the ring to write 544 * the fence seq number and DMA trap packet to generate 545 * an interrupt if needed (NAVI10). 546 */ 547 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 548 unsigned flags) 549 { 550 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 551 /* write the fence */ 552 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 553 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 554 /* zero in first two bits */ 555 BUG_ON(addr & 0x3); 556 amdgpu_ring_write(ring, lower_32_bits(addr)); 557 amdgpu_ring_write(ring, upper_32_bits(addr)); 558 amdgpu_ring_write(ring, lower_32_bits(seq)); 559 560 /* optionally write high bits as well */ 561 if (write64bit) { 562 addr += 4; 563 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 564 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 565 /* zero in first two bits */ 566 BUG_ON(addr & 0x3); 567 amdgpu_ring_write(ring, lower_32_bits(addr)); 568 amdgpu_ring_write(ring, upper_32_bits(addr)); 569 amdgpu_ring_write(ring, upper_32_bits(seq)); 570 } 571 572 if (flags & AMDGPU_FENCE_FLAG_INT) { 573 /* generate an interrupt */ 574 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 575 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 576 } 577 } 578 579 580 /** 581 * sdma_v5_0_gfx_stop - stop the gfx async dma engines 582 * 583 * @adev: amdgpu_device pointer 584 * 585 * Stop the gfx async dma ring buffers (NAVI10). 586 */ 587 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev) 588 { 589 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 590 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 591 u32 rb_cntl, ib_cntl; 592 int i; 593 594 if ((adev->mman.buffer_funcs_ring == sdma0) || 595 (adev->mman.buffer_funcs_ring == sdma1)) 596 amdgpu_ttm_set_buffer_funcs_status(adev, false); 597 598 for (i = 0; i < adev->sdma.num_instances; i++) { 599 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 600 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 601 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 602 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 603 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 604 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 605 } 606 } 607 608 /** 609 * sdma_v5_0_rlc_stop - stop the compute async dma engines 610 * 611 * @adev: amdgpu_device pointer 612 * 613 * Stop the compute async dma queues (NAVI10). 614 */ 615 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) 616 { 617 /* XXX todo */ 618 } 619 620 /** 621 * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch 622 * 623 * @adev: amdgpu_device pointer 624 * @enable: enable/disable the DMA MEs context switch. 625 * 626 * Halt or unhalt the async dma engines context switch (NAVI10). 627 */ 628 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 629 { 630 u32 f32_cntl = 0, phase_quantum = 0; 631 int i; 632 633 if (amdgpu_sdma_phase_quantum) { 634 unsigned value = amdgpu_sdma_phase_quantum; 635 unsigned unit = 0; 636 637 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 638 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 639 value = (value + 1) >> 1; 640 unit++; 641 } 642 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 643 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 644 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 645 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 646 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 647 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 648 WARN_ONCE(1, 649 "clamping sdma_phase_quantum to %uK clock cycles\n", 650 value << unit); 651 } 652 phase_quantum = 653 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 654 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 655 } 656 657 for (i = 0; i < adev->sdma.num_instances; i++) { 658 if (!amdgpu_sriov_vf(adev)) { 659 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 660 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 661 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 662 } 663 664 if (enable && amdgpu_sdma_phase_quantum) { 665 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 666 phase_quantum); 667 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 668 phase_quantum); 669 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 670 phase_quantum); 671 } 672 if (!amdgpu_sriov_vf(adev)) 673 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 674 } 675 676 } 677 678 /** 679 * sdma_v5_0_enable - stop the async dma engines 680 * 681 * @adev: amdgpu_device pointer 682 * @enable: enable/disable the DMA MEs. 683 * 684 * Halt or unhalt the async dma engines (NAVI10). 685 */ 686 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) 687 { 688 u32 f32_cntl; 689 int i; 690 691 if (!enable) { 692 sdma_v5_0_gfx_stop(adev); 693 sdma_v5_0_rlc_stop(adev); 694 } 695 696 if (amdgpu_sriov_vf(adev)) 697 return; 698 699 for (i = 0; i < adev->sdma.num_instances; i++) { 700 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 701 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 702 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 703 } 704 } 705 706 /** 707 * sdma_v5_0_gfx_resume - setup and start the async dma engines 708 * 709 * @adev: amdgpu_device pointer 710 * 711 * Set up the gfx DMA ring buffers and enable them (NAVI10). 712 * Returns 0 for success, error for failure. 713 */ 714 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) 715 { 716 struct amdgpu_ring *ring; 717 u32 rb_cntl, ib_cntl; 718 u32 rb_bufsz; 719 u32 wb_offset; 720 u32 doorbell; 721 u32 doorbell_offset; 722 u32 temp; 723 u32 wptr_poll_cntl; 724 u64 wptr_gpu_addr; 725 int i, r; 726 727 for (i = 0; i < adev->sdma.num_instances; i++) { 728 ring = &adev->sdma.instance[i].ring; 729 wb_offset = (ring->rptr_offs * 4); 730 731 if (!amdgpu_sriov_vf(adev)) 732 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 733 734 /* Set ring buffer size in dwords */ 735 rb_bufsz = order_base_2(ring->ring_size / 4); 736 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 737 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 738 #ifdef __BIG_ENDIAN 739 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 740 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 741 RPTR_WRITEBACK_SWAP_ENABLE, 1); 742 #endif 743 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 744 745 /* Initialize the ring buffer's read and write pointers */ 746 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 747 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 748 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 749 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 750 751 /* setup the wptr shadow polling */ 752 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 753 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 754 lower_32_bits(wptr_gpu_addr)); 755 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 756 upper_32_bits(wptr_gpu_addr)); 757 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 758 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 759 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 760 SDMA0_GFX_RB_WPTR_POLL_CNTL, 761 F32_POLL_ENABLE, 1); 762 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 763 wptr_poll_cntl); 764 765 /* set the wb address whether it's enabled or not */ 766 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 767 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 768 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 769 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 770 771 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 772 773 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), 774 ring->gpu_addr >> 8); 775 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), 776 ring->gpu_addr >> 40); 777 778 ring->wptr = 0; 779 780 /* before programing wptr to a less value, need set minor_ptr_update first */ 781 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 782 783 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 784 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 785 lower_32_bits(ring->wptr) << 2); 786 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 787 upper_32_bits(ring->wptr) << 2); 788 } 789 790 doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 791 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, 792 mmSDMA0_GFX_DOORBELL_OFFSET)); 793 794 if (ring->use_doorbell) { 795 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 796 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 797 OFFSET, ring->doorbell_index); 798 } else { 799 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 800 } 801 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 802 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), 803 doorbell_offset); 804 805 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 806 ring->doorbell_index, 20); 807 808 if (amdgpu_sriov_vf(adev)) 809 sdma_v5_0_ring_set_wptr(ring); 810 811 /* set minor_ptr_update to 0 after wptr programed */ 812 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 813 814 if (!amdgpu_sriov_vf(adev)) { 815 /* set utc l1 enable flag always to 1 */ 816 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 817 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 818 819 /* enable MCBP */ 820 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 821 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 822 823 /* Set up RESP_MODE to non-copy addresses */ 824 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 825 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 826 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 827 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 828 829 /* program default cache read and write policy */ 830 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 831 /* clean read policy and write policy bits */ 832 temp &= 0xFF0FFF; 833 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 834 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 835 } 836 837 if (!amdgpu_sriov_vf(adev)) { 838 /* unhalt engine */ 839 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 840 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 841 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 842 } 843 844 /* enable DMA RB */ 845 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 846 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 847 848 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 849 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 850 #ifdef __BIG_ENDIAN 851 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 852 #endif 853 /* enable DMA IBs */ 854 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 855 856 ring->sched.ready = true; 857 858 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 859 sdma_v5_0_ctx_switch_enable(adev, true); 860 sdma_v5_0_enable(adev, true); 861 } 862 863 r = amdgpu_ring_test_helper(ring); 864 if (r) 865 return r; 866 867 if (adev->mman.buffer_funcs_ring == ring) 868 amdgpu_ttm_set_buffer_funcs_status(adev, true); 869 } 870 871 return 0; 872 } 873 874 /** 875 * sdma_v5_0_rlc_resume - setup and start the async dma engines 876 * 877 * @adev: amdgpu_device pointer 878 * 879 * Set up the compute DMA queues and enable them (NAVI10). 880 * Returns 0 for success, error for failure. 881 */ 882 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev) 883 { 884 return 0; 885 } 886 887 /** 888 * sdma_v5_0_load_microcode - load the sDMA ME ucode 889 * 890 * @adev: amdgpu_device pointer 891 * 892 * Loads the sDMA0/1 ucode. 893 * Returns 0 for success, -EINVAL if the ucode is not available. 894 */ 895 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev) 896 { 897 const struct sdma_firmware_header_v1_0 *hdr; 898 const __le32 *fw_data; 899 u32 fw_size; 900 int i, j; 901 902 /* halt the MEs */ 903 sdma_v5_0_enable(adev, false); 904 905 for (i = 0; i < adev->sdma.num_instances; i++) { 906 if (!adev->sdma.instance[i].fw) 907 return -EINVAL; 908 909 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 910 amdgpu_ucode_print_sdma_hdr(&hdr->header); 911 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 912 913 fw_data = (const __le32 *) 914 (adev->sdma.instance[i].fw->data + 915 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 916 917 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 918 919 for (j = 0; j < fw_size; j++) { 920 if (amdgpu_emu_mode == 1 && j % 500 == 0) 921 msleep(1); 922 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 923 } 924 925 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 926 } 927 928 return 0; 929 } 930 931 /** 932 * sdma_v5_0_start - setup and start the async dma engines 933 * 934 * @adev: amdgpu_device pointer 935 * 936 * Set up the DMA engines and enable them (NAVI10). 937 * Returns 0 for success, error for failure. 938 */ 939 static int sdma_v5_0_start(struct amdgpu_device *adev) 940 { 941 int r = 0; 942 943 if (amdgpu_sriov_vf(adev)) { 944 sdma_v5_0_ctx_switch_enable(adev, false); 945 sdma_v5_0_enable(adev, false); 946 947 /* set RB registers */ 948 r = sdma_v5_0_gfx_resume(adev); 949 return r; 950 } 951 952 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 953 r = sdma_v5_0_load_microcode(adev); 954 if (r) 955 return r; 956 } 957 958 /* unhalt the MEs */ 959 sdma_v5_0_enable(adev, true); 960 /* enable sdma ring preemption */ 961 sdma_v5_0_ctx_switch_enable(adev, true); 962 963 /* start the gfx rings and rlc compute queues */ 964 r = sdma_v5_0_gfx_resume(adev); 965 if (r) 966 return r; 967 r = sdma_v5_0_rlc_resume(adev); 968 969 return r; 970 } 971 972 /** 973 * sdma_v5_0_ring_test_ring - simple async dma engine test 974 * 975 * @ring: amdgpu_ring structure holding ring information 976 * 977 * Test the DMA engine by writing using it to write an 978 * value to memory. (NAVI10). 979 * Returns 0 for success, error for failure. 980 */ 981 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) 982 { 983 struct amdgpu_device *adev = ring->adev; 984 unsigned i; 985 unsigned index; 986 int r; 987 u32 tmp; 988 u64 gpu_addr; 989 990 r = amdgpu_device_wb_get(adev, &index); 991 if (r) { 992 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 993 return r; 994 } 995 996 gpu_addr = adev->wb.gpu_addr + (index * 4); 997 tmp = 0xCAFEDEAD; 998 adev->wb.wb[index] = cpu_to_le32(tmp); 999 1000 r = amdgpu_ring_alloc(ring, 5); 1001 if (r) { 1002 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 1003 amdgpu_device_wb_free(adev, index); 1004 return r; 1005 } 1006 1007 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1008 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1009 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1010 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1011 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1012 amdgpu_ring_write(ring, 0xDEADBEEF); 1013 amdgpu_ring_commit(ring); 1014 1015 for (i = 0; i < adev->usec_timeout; i++) { 1016 tmp = le32_to_cpu(adev->wb.wb[index]); 1017 if (tmp == 0xDEADBEEF) 1018 break; 1019 if (amdgpu_emu_mode == 1) 1020 msleep(1); 1021 else 1022 udelay(1); 1023 } 1024 1025 if (i >= adev->usec_timeout) 1026 r = -ETIMEDOUT; 1027 1028 amdgpu_device_wb_free(adev, index); 1029 1030 return r; 1031 } 1032 1033 /** 1034 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine 1035 * 1036 * @ring: amdgpu_ring structure holding ring information 1037 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 1038 * 1039 * Test a simple IB in the DMA ring (NAVI10). 1040 * Returns 0 on success, error on failure. 1041 */ 1042 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1043 { 1044 struct amdgpu_device *adev = ring->adev; 1045 struct amdgpu_ib ib; 1046 struct dma_fence *f = NULL; 1047 unsigned index; 1048 long r; 1049 u32 tmp = 0; 1050 u64 gpu_addr; 1051 1052 r = amdgpu_device_wb_get(adev, &index); 1053 if (r) { 1054 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1055 return r; 1056 } 1057 1058 gpu_addr = adev->wb.gpu_addr + (index * 4); 1059 tmp = 0xCAFEDEAD; 1060 adev->wb.wb[index] = cpu_to_le32(tmp); 1061 memset(&ib, 0, sizeof(ib)); 1062 r = amdgpu_ib_get(adev, NULL, 256, 1063 AMDGPU_IB_POOL_DIRECT, &ib); 1064 if (r) { 1065 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1066 goto err0; 1067 } 1068 1069 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1070 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1071 ib.ptr[1] = lower_32_bits(gpu_addr); 1072 ib.ptr[2] = upper_32_bits(gpu_addr); 1073 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1074 ib.ptr[4] = 0xDEADBEEF; 1075 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1076 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1077 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1078 ib.length_dw = 8; 1079 1080 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1081 if (r) 1082 goto err1; 1083 1084 r = dma_fence_wait_timeout(f, false, timeout); 1085 if (r == 0) { 1086 DRM_ERROR("amdgpu: IB test timed out\n"); 1087 r = -ETIMEDOUT; 1088 goto err1; 1089 } else if (r < 0) { 1090 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1091 goto err1; 1092 } 1093 tmp = le32_to_cpu(adev->wb.wb[index]); 1094 if (tmp == 0xDEADBEEF) 1095 r = 0; 1096 else 1097 r = -EINVAL; 1098 1099 err1: 1100 amdgpu_ib_free(adev, &ib, NULL); 1101 dma_fence_put(f); 1102 err0: 1103 amdgpu_device_wb_free(adev, index); 1104 return r; 1105 } 1106 1107 1108 /** 1109 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART 1110 * 1111 * @ib: indirect buffer to fill with commands 1112 * @pe: addr of the page entry 1113 * @src: src addr to copy from 1114 * @count: number of page entries to update 1115 * 1116 * Update PTEs by copying them from the GART using sDMA (NAVI10). 1117 */ 1118 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib, 1119 uint64_t pe, uint64_t src, 1120 unsigned count) 1121 { 1122 unsigned bytes = count * 8; 1123 1124 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1125 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1126 ib->ptr[ib->length_dw++] = bytes - 1; 1127 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1128 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1129 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1130 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1131 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1132 1133 } 1134 1135 /** 1136 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually 1137 * 1138 * @ib: indirect buffer to fill with commands 1139 * @pe: addr of the page entry 1140 * @value: dst addr to write into pe 1141 * @count: number of page entries to update 1142 * @incr: increase next addr by incr bytes 1143 * 1144 * Update PTEs by writing them manually using sDMA (NAVI10). 1145 */ 1146 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1147 uint64_t value, unsigned count, 1148 uint32_t incr) 1149 { 1150 unsigned ndw = count * 2; 1151 1152 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1153 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1154 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1155 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1156 ib->ptr[ib->length_dw++] = ndw - 1; 1157 for (; ndw > 0; ndw -= 2) { 1158 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1159 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1160 value += incr; 1161 } 1162 } 1163 1164 /** 1165 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA 1166 * 1167 * @ib: indirect buffer to fill with commands 1168 * @pe: addr of the page entry 1169 * @addr: dst addr to write into pe 1170 * @count: number of page entries to update 1171 * @incr: increase next addr by incr bytes 1172 * @flags: access flags 1173 * 1174 * Update the page tables using sDMA (NAVI10). 1175 */ 1176 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1177 uint64_t pe, 1178 uint64_t addr, unsigned count, 1179 uint32_t incr, uint64_t flags) 1180 { 1181 /* for physically contiguous pages (vram) */ 1182 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1183 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1184 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1185 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1186 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1187 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1188 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1189 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1190 ib->ptr[ib->length_dw++] = 0; 1191 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1192 } 1193 1194 /** 1195 * sdma_v5_0_ring_pad_ib - pad the IB 1196 * @ring: amdgpu_ring structure holding ring information 1197 * @ib: indirect buffer to fill with padding 1198 * 1199 * Pad the IB with NOPs to a boundary multiple of 8. 1200 */ 1201 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1202 { 1203 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1204 u32 pad_count; 1205 int i; 1206 1207 pad_count = (-ib->length_dw) & 0x7; 1208 for (i = 0; i < pad_count; i++) 1209 if (sdma && sdma->burst_nop && (i == 0)) 1210 ib->ptr[ib->length_dw++] = 1211 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1212 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1213 else 1214 ib->ptr[ib->length_dw++] = 1215 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1216 } 1217 1218 1219 /** 1220 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline 1221 * 1222 * @ring: amdgpu_ring pointer 1223 * 1224 * Make sure all previous operations are completed (CIK). 1225 */ 1226 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1227 { 1228 uint32_t seq = ring->fence_drv.sync_seq; 1229 uint64_t addr = ring->fence_drv.gpu_addr; 1230 1231 /* wait for idle */ 1232 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1233 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1234 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1235 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1236 amdgpu_ring_write(ring, addr & 0xfffffffc); 1237 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1238 amdgpu_ring_write(ring, seq); /* reference */ 1239 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1240 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1241 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1242 } 1243 1244 1245 /** 1246 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA 1247 * 1248 * @ring: amdgpu_ring pointer 1249 * @vmid: vmid number to use 1250 * @pd_addr: address 1251 * 1252 * Update the page table base and flush the VM TLB 1253 * using sDMA (NAVI10). 1254 */ 1255 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1256 unsigned vmid, uint64_t pd_addr) 1257 { 1258 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1259 } 1260 1261 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring, 1262 uint32_t reg, uint32_t val) 1263 { 1264 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1265 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1266 amdgpu_ring_write(ring, reg); 1267 amdgpu_ring_write(ring, val); 1268 } 1269 1270 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1271 uint32_t val, uint32_t mask) 1272 { 1273 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1274 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1275 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1276 amdgpu_ring_write(ring, reg << 2); 1277 amdgpu_ring_write(ring, 0); 1278 amdgpu_ring_write(ring, val); /* reference */ 1279 amdgpu_ring_write(ring, mask); /* mask */ 1280 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1281 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1282 } 1283 1284 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1285 uint32_t reg0, uint32_t reg1, 1286 uint32_t ref, uint32_t mask) 1287 { 1288 amdgpu_ring_emit_wreg(ring, reg0, ref); 1289 /* wait for a cycle to reset vm_inv_eng*_ack */ 1290 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1291 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1292 } 1293 1294 static int sdma_v5_0_early_init(void *handle) 1295 { 1296 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1297 1298 sdma_v5_0_set_ring_funcs(adev); 1299 sdma_v5_0_set_buffer_funcs(adev); 1300 sdma_v5_0_set_vm_pte_funcs(adev); 1301 sdma_v5_0_set_irq_funcs(adev); 1302 1303 return 0; 1304 } 1305 1306 1307 static int sdma_v5_0_sw_init(void *handle) 1308 { 1309 struct amdgpu_ring *ring; 1310 int r, i; 1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1312 1313 /* SDMA trap event */ 1314 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 1315 SDMA0_5_0__SRCID__SDMA_TRAP, 1316 &adev->sdma.trap_irq); 1317 if (r) 1318 return r; 1319 1320 /* SDMA trap event */ 1321 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 1322 SDMA1_5_0__SRCID__SDMA_TRAP, 1323 &adev->sdma.trap_irq); 1324 if (r) 1325 return r; 1326 1327 r = sdma_v5_0_init_microcode(adev); 1328 if (r) { 1329 DRM_ERROR("Failed to load sdma firmware!\n"); 1330 return r; 1331 } 1332 1333 for (i = 0; i < adev->sdma.num_instances; i++) { 1334 ring = &adev->sdma.instance[i].ring; 1335 ring->ring_obj = NULL; 1336 ring->use_doorbell = true; 1337 1338 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i, 1339 ring->use_doorbell?"true":"false"); 1340 1341 ring->doorbell_index = (i == 0) ? 1342 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset 1343 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset 1344 1345 sprintf(ring->name, "sdma%d", i); 1346 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 1347 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 1348 AMDGPU_SDMA_IRQ_INSTANCE1, 1349 AMDGPU_RING_PRIO_DEFAULT, NULL); 1350 if (r) 1351 return r; 1352 } 1353 1354 return r; 1355 } 1356 1357 static int sdma_v5_0_sw_fini(void *handle) 1358 { 1359 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1360 int i; 1361 1362 for (i = 0; i < adev->sdma.num_instances; i++) { 1363 release_firmware(adev->sdma.instance[i].fw); 1364 adev->sdma.instance[i].fw = NULL; 1365 1366 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1367 } 1368 1369 return 0; 1370 } 1371 1372 static int sdma_v5_0_hw_init(void *handle) 1373 { 1374 int r; 1375 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1376 1377 sdma_v5_0_init_golden_registers(adev); 1378 1379 r = sdma_v5_0_start(adev); 1380 1381 return r; 1382 } 1383 1384 static int sdma_v5_0_hw_fini(void *handle) 1385 { 1386 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1387 1388 if (amdgpu_sriov_vf(adev)) 1389 return 0; 1390 1391 sdma_v5_0_ctx_switch_enable(adev, false); 1392 sdma_v5_0_enable(adev, false); 1393 1394 return 0; 1395 } 1396 1397 static int sdma_v5_0_suspend(void *handle) 1398 { 1399 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1400 1401 return sdma_v5_0_hw_fini(adev); 1402 } 1403 1404 static int sdma_v5_0_resume(void *handle) 1405 { 1406 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1407 1408 return sdma_v5_0_hw_init(adev); 1409 } 1410 1411 static bool sdma_v5_0_is_idle(void *handle) 1412 { 1413 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1414 u32 i; 1415 1416 for (i = 0; i < adev->sdma.num_instances; i++) { 1417 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1418 1419 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1420 return false; 1421 } 1422 1423 return true; 1424 } 1425 1426 static int sdma_v5_0_wait_for_idle(void *handle) 1427 { 1428 unsigned i; 1429 u32 sdma0, sdma1; 1430 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1431 1432 for (i = 0; i < adev->usec_timeout; i++) { 1433 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1434 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1435 1436 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1437 return 0; 1438 udelay(1); 1439 } 1440 return -ETIMEDOUT; 1441 } 1442 1443 static int sdma_v5_0_soft_reset(void *handle) 1444 { 1445 /* todo */ 1446 1447 return 0; 1448 } 1449 1450 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring) 1451 { 1452 int i, r = 0; 1453 struct amdgpu_device *adev = ring->adev; 1454 u32 index = 0; 1455 u64 sdma_gfx_preempt; 1456 1457 amdgpu_sdma_get_index_from_ring(ring, &index); 1458 if (index == 0) 1459 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT; 1460 else 1461 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT; 1462 1463 /* assert preemption condition */ 1464 amdgpu_ring_set_preempt_cond_exec(ring, false); 1465 1466 /* emit the trailing fence */ 1467 ring->trail_seq += 1; 1468 amdgpu_ring_alloc(ring, 10); 1469 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1470 ring->trail_seq, 0); 1471 amdgpu_ring_commit(ring); 1472 1473 /* assert IB preemption */ 1474 WREG32(sdma_gfx_preempt, 1); 1475 1476 /* poll the trailing fence */ 1477 for (i = 0; i < adev->usec_timeout; i++) { 1478 if (ring->trail_seq == 1479 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1480 break; 1481 udelay(1); 1482 } 1483 1484 if (i >= adev->usec_timeout) { 1485 r = -EINVAL; 1486 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1487 } 1488 1489 /* deassert IB preemption */ 1490 WREG32(sdma_gfx_preempt, 0); 1491 1492 /* deassert the preemption condition */ 1493 amdgpu_ring_set_preempt_cond_exec(ring, true); 1494 return r; 1495 } 1496 1497 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev, 1498 struct amdgpu_irq_src *source, 1499 unsigned type, 1500 enum amdgpu_interrupt_state state) 1501 { 1502 u32 sdma_cntl; 1503 1504 if (!amdgpu_sriov_vf(adev)) { 1505 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? 1506 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1507 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1508 1509 sdma_cntl = RREG32(reg_offset); 1510 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1511 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1512 WREG32(reg_offset, sdma_cntl); 1513 } 1514 1515 return 0; 1516 } 1517 1518 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, 1519 struct amdgpu_irq_src *source, 1520 struct amdgpu_iv_entry *entry) 1521 { 1522 DRM_DEBUG("IH: SDMA trap\n"); 1523 switch (entry->client_id) { 1524 case SOC15_IH_CLIENTID_SDMA0: 1525 switch (entry->ring_id) { 1526 case 0: 1527 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1528 break; 1529 case 1: 1530 /* XXX compute */ 1531 break; 1532 case 2: 1533 /* XXX compute */ 1534 break; 1535 case 3: 1536 /* XXX page queue*/ 1537 break; 1538 } 1539 break; 1540 case SOC15_IH_CLIENTID_SDMA1: 1541 switch (entry->ring_id) { 1542 case 0: 1543 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1544 break; 1545 case 1: 1546 /* XXX compute */ 1547 break; 1548 case 2: 1549 /* XXX compute */ 1550 break; 1551 case 3: 1552 /* XXX page queue*/ 1553 break; 1554 } 1555 break; 1556 } 1557 return 0; 1558 } 1559 1560 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1561 struct amdgpu_irq_src *source, 1562 struct amdgpu_iv_entry *entry) 1563 { 1564 return 0; 1565 } 1566 1567 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1568 bool enable) 1569 { 1570 uint32_t data, def; 1571 int i; 1572 1573 for (i = 0; i < adev->sdma.num_instances; i++) { 1574 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1575 /* Enable sdma clock gating */ 1576 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1577 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1578 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1579 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1580 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1581 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1582 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1583 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1584 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1585 if (def != data) 1586 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1587 } else { 1588 /* Disable sdma clock gating */ 1589 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1590 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1591 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1592 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1593 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1594 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1595 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1596 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1597 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1598 if (def != data) 1599 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1600 } 1601 } 1602 } 1603 1604 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1605 bool enable) 1606 { 1607 uint32_t data, def; 1608 int i; 1609 1610 for (i = 0; i < adev->sdma.num_instances; i++) { 1611 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1612 /* Enable sdma mem light sleep */ 1613 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1614 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1615 if (def != data) 1616 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1617 1618 } else { 1619 /* Disable sdma mem light sleep */ 1620 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1621 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1622 if (def != data) 1623 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1624 1625 } 1626 } 1627 } 1628 1629 static int sdma_v5_0_set_clockgating_state(void *handle, 1630 enum amd_clockgating_state state) 1631 { 1632 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1633 1634 if (amdgpu_sriov_vf(adev)) 1635 return 0; 1636 1637 switch (adev->ip_versions[SDMA0_HWIP][0]) { 1638 case IP_VERSION(5, 0, 0): 1639 case IP_VERSION(5, 0, 2): 1640 case IP_VERSION(5, 0, 5): 1641 sdma_v5_0_update_medium_grain_clock_gating(adev, 1642 state == AMD_CG_STATE_GATE); 1643 sdma_v5_0_update_medium_grain_light_sleep(adev, 1644 state == AMD_CG_STATE_GATE); 1645 break; 1646 default: 1647 break; 1648 } 1649 1650 return 0; 1651 } 1652 1653 static int sdma_v5_0_set_powergating_state(void *handle, 1654 enum amd_powergating_state state) 1655 { 1656 return 0; 1657 } 1658 1659 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags) 1660 { 1661 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1662 int data; 1663 1664 if (amdgpu_sriov_vf(adev)) 1665 *flags = 0; 1666 1667 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1668 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1669 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1670 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1671 1672 /* AMD_CG_SUPPORT_SDMA_LS */ 1673 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1674 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1675 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1676 } 1677 1678 const struct amd_ip_funcs sdma_v5_0_ip_funcs = { 1679 .name = "sdma_v5_0", 1680 .early_init = sdma_v5_0_early_init, 1681 .late_init = NULL, 1682 .sw_init = sdma_v5_0_sw_init, 1683 .sw_fini = sdma_v5_0_sw_fini, 1684 .hw_init = sdma_v5_0_hw_init, 1685 .hw_fini = sdma_v5_0_hw_fini, 1686 .suspend = sdma_v5_0_suspend, 1687 .resume = sdma_v5_0_resume, 1688 .is_idle = sdma_v5_0_is_idle, 1689 .wait_for_idle = sdma_v5_0_wait_for_idle, 1690 .soft_reset = sdma_v5_0_soft_reset, 1691 .set_clockgating_state = sdma_v5_0_set_clockgating_state, 1692 .set_powergating_state = sdma_v5_0_set_powergating_state, 1693 .get_clockgating_state = sdma_v5_0_get_clockgating_state, 1694 }; 1695 1696 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 1697 .type = AMDGPU_RING_TYPE_SDMA, 1698 .align_mask = 0xf, 1699 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1700 .support_64bit_ptrs = true, 1701 .vmhub = AMDGPU_GFXHUB_0, 1702 .get_rptr = sdma_v5_0_ring_get_rptr, 1703 .get_wptr = sdma_v5_0_ring_get_wptr, 1704 .set_wptr = sdma_v5_0_ring_set_wptr, 1705 .emit_frame_size = 1706 5 + /* sdma_v5_0_ring_init_cond_exec */ 1707 6 + /* sdma_v5_0_ring_emit_hdp_flush */ 1708 3 + /* hdp_invalidate */ 1709 6 + /* sdma_v5_0_ring_emit_pipeline_sync */ 1710 /* sdma_v5_0_ring_emit_vm_flush */ 1711 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1712 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 + 1713 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ 1714 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */ 1715 .emit_ib = sdma_v5_0_ring_emit_ib, 1716 .emit_mem_sync = sdma_v5_0_ring_emit_mem_sync, 1717 .emit_fence = sdma_v5_0_ring_emit_fence, 1718 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync, 1719 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush, 1720 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush, 1721 .test_ring = sdma_v5_0_ring_test_ring, 1722 .test_ib = sdma_v5_0_ring_test_ib, 1723 .insert_nop = sdma_v5_0_ring_insert_nop, 1724 .pad_ib = sdma_v5_0_ring_pad_ib, 1725 .emit_wreg = sdma_v5_0_ring_emit_wreg, 1726 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait, 1727 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait, 1728 .init_cond_exec = sdma_v5_0_ring_init_cond_exec, 1729 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec, 1730 .preempt_ib = sdma_v5_0_ring_preempt_ib, 1731 }; 1732 1733 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) 1734 { 1735 int i; 1736 1737 for (i = 0; i < adev->sdma.num_instances; i++) { 1738 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; 1739 adev->sdma.instance[i].ring.me = i; 1740 } 1741 } 1742 1743 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = { 1744 .set = sdma_v5_0_set_trap_irq_state, 1745 .process = sdma_v5_0_process_trap_irq, 1746 }; 1747 1748 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = { 1749 .process = sdma_v5_0_process_illegal_inst_irq, 1750 }; 1751 1752 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev) 1753 { 1754 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1755 adev->sdma.num_instances; 1756 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; 1757 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; 1758 } 1759 1760 /** 1761 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine 1762 * 1763 * @ib: indirect buffer to copy to 1764 * @src_offset: src GPU address 1765 * @dst_offset: dst GPU address 1766 * @byte_count: number of bytes to xfer 1767 * @tmz: if a secure copy should be used 1768 * 1769 * Copy GPU buffers using the DMA engine (NAVI10). 1770 * Used by the amdgpu ttm implementation to move pages if 1771 * registered as the asic copy callback. 1772 */ 1773 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib, 1774 uint64_t src_offset, 1775 uint64_t dst_offset, 1776 uint32_t byte_count, 1777 bool tmz) 1778 { 1779 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1780 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | 1781 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0); 1782 ib->ptr[ib->length_dw++] = byte_count - 1; 1783 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1784 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1785 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1786 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1787 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1788 } 1789 1790 /** 1791 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine 1792 * 1793 * @ib: indirect buffer to fill 1794 * @src_data: value to write to buffer 1795 * @dst_offset: dst GPU address 1796 * @byte_count: number of bytes to xfer 1797 * 1798 * Fill GPU buffers using the DMA engine (NAVI10). 1799 */ 1800 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib, 1801 uint32_t src_data, 1802 uint64_t dst_offset, 1803 uint32_t byte_count) 1804 { 1805 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1806 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1807 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1808 ib->ptr[ib->length_dw++] = src_data; 1809 ib->ptr[ib->length_dw++] = byte_count - 1; 1810 } 1811 1812 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { 1813 .copy_max_bytes = 0x400000, 1814 .copy_num_dw = 7, 1815 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer, 1816 1817 .fill_max_bytes = 0x400000, 1818 .fill_num_dw = 5, 1819 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer, 1820 }; 1821 1822 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) 1823 { 1824 if (adev->mman.buffer_funcs == NULL) { 1825 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; 1826 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1827 } 1828 } 1829 1830 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 1831 .copy_pte_num_dw = 7, 1832 .copy_pte = sdma_v5_0_vm_copy_pte, 1833 .write_pte = sdma_v5_0_vm_write_pte, 1834 .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 1835 }; 1836 1837 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1838 { 1839 unsigned i; 1840 1841 if (adev->vm_manager.vm_pte_funcs == NULL) { 1842 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; 1843 for (i = 0; i < adev->sdma.num_instances; i++) { 1844 adev->vm_manager.vm_pte_scheds[i] = 1845 &adev->sdma.instance[i].ring.sched; 1846 } 1847 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1848 } 1849 } 1850 1851 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { 1852 .type = AMD_IP_BLOCK_TYPE_SDMA, 1853 .major = 5, 1854 .minor = 0, 1855 .rev = 0, 1856 .funcs = &sdma_v5_0_ip_funcs, 1857 }; 1858