1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "sdma0/sdma0_4_2_offset.h" 31 #include "sdma0/sdma0_4_2_sh_mask.h" 32 #include "sdma1/sdma1_4_2_offset.h" 33 #include "sdma1/sdma1_4_2_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "sdma0/sdma0_4_1_default.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 45 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 46 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 47 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 48 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 50 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 51 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin"); 53 54 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 55 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 56 57 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 58 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 59 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 60 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 61 62 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 63 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 64 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 65 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 66 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 68 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 69 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 70 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 71 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 73 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 75 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 76 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 77 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 78 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 79 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 80 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 81 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 82 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 83 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 84 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 85 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 86 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 87 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 88 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 89 }; 90 91 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 94 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 95 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 96 }; 97 98 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) 103 }; 104 105 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = { 106 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 107 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 108 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 109 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 110 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 111 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 112 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 113 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 114 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 117 }; 118 119 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = { 120 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 121 }; 122 123 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] = 124 { 125 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 126 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 127 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 131 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 132 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 133 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003), 134 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 135 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 147 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 149 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 151 }; 152 153 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 154 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 155 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 156 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 157 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 158 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 159 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 160 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 161 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 162 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003), 163 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 164 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 165 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 166 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 167 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 168 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 169 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 170 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 171 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 172 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 173 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 174 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 175 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 176 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 177 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 178 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 180 }; 181 182 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 183 { 184 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 185 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 186 }; 187 188 static const struct soc15_reg_golden golden_settings_sdma_rv2[] = 189 { 190 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001), 191 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001) 192 }; 193 194 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 195 u32 instance, u32 offset) 196 { 197 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : 198 (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); 199 } 200 201 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 202 { 203 switch (adev->asic_type) { 204 case CHIP_VEGA10: 205 soc15_program_register_sequence(adev, 206 golden_settings_sdma_4, 207 ARRAY_SIZE(golden_settings_sdma_4)); 208 soc15_program_register_sequence(adev, 209 golden_settings_sdma_vg10, 210 ARRAY_SIZE(golden_settings_sdma_vg10)); 211 break; 212 case CHIP_VEGA12: 213 soc15_program_register_sequence(adev, 214 golden_settings_sdma_4, 215 ARRAY_SIZE(golden_settings_sdma_4)); 216 soc15_program_register_sequence(adev, 217 golden_settings_sdma_vg12, 218 ARRAY_SIZE(golden_settings_sdma_vg12)); 219 break; 220 case CHIP_VEGA20: 221 soc15_program_register_sequence(adev, 222 golden_settings_sdma0_4_2_init, 223 ARRAY_SIZE(golden_settings_sdma0_4_2_init)); 224 soc15_program_register_sequence(adev, 225 golden_settings_sdma0_4_2, 226 ARRAY_SIZE(golden_settings_sdma0_4_2)); 227 soc15_program_register_sequence(adev, 228 golden_settings_sdma1_4_2, 229 ARRAY_SIZE(golden_settings_sdma1_4_2)); 230 break; 231 case CHIP_RAVEN: 232 soc15_program_register_sequence(adev, 233 golden_settings_sdma_4_1, 234 ARRAY_SIZE(golden_settings_sdma_4_1)); 235 if (adev->rev_id >= 8) 236 soc15_program_register_sequence(adev, 237 golden_settings_sdma_rv2, 238 ARRAY_SIZE(golden_settings_sdma_rv2)); 239 else 240 soc15_program_register_sequence(adev, 241 golden_settings_sdma_rv1, 242 ARRAY_SIZE(golden_settings_sdma_rv1)); 243 break; 244 default: 245 break; 246 } 247 } 248 249 /** 250 * sdma_v4_0_init_microcode - load ucode images from disk 251 * 252 * @adev: amdgpu_device pointer 253 * 254 * Use the firmware interface to load the ucode images into 255 * the driver (not loaded into hw). 256 * Returns 0 on success, error on failure. 257 */ 258 259 // emulation only, won't work on real chip 260 // vega10 real chip need to use PSP to load firmware 261 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 262 { 263 const char *chip_name; 264 char fw_name[30]; 265 int err = 0, i; 266 struct amdgpu_firmware_info *info = NULL; 267 const struct common_firmware_header *header = NULL; 268 const struct sdma_firmware_header_v1_0 *hdr; 269 270 DRM_DEBUG("\n"); 271 272 switch (adev->asic_type) { 273 case CHIP_VEGA10: 274 chip_name = "vega10"; 275 break; 276 case CHIP_VEGA12: 277 chip_name = "vega12"; 278 break; 279 case CHIP_VEGA20: 280 chip_name = "vega20"; 281 break; 282 case CHIP_RAVEN: 283 if (adev->rev_id >= 8) 284 chip_name = "raven2"; 285 else if (adev->pdev->device == 0x15d8) 286 chip_name = "picasso"; 287 else 288 chip_name = "raven"; 289 break; 290 default: 291 BUG(); 292 } 293 294 for (i = 0; i < adev->sdma.num_instances; i++) { 295 if (i == 0) 296 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 297 else 298 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 299 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 300 if (err) 301 goto out; 302 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 303 if (err) 304 goto out; 305 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 306 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 307 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 308 if (adev->sdma.instance[i].feature_version >= 20) 309 adev->sdma.instance[i].burst_nop = true; 310 DRM_DEBUG("psp_load == '%s'\n", 311 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 312 313 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 314 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 315 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 316 info->fw = adev->sdma.instance[i].fw; 317 header = (const struct common_firmware_header *)info->fw->data; 318 adev->firmware.fw_size += 319 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 320 } 321 } 322 out: 323 if (err) { 324 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 325 for (i = 0; i < adev->sdma.num_instances; i++) { 326 release_firmware(adev->sdma.instance[i].fw); 327 adev->sdma.instance[i].fw = NULL; 328 } 329 } 330 return err; 331 } 332 333 /** 334 * sdma_v4_0_ring_get_rptr - get the current read pointer 335 * 336 * @ring: amdgpu ring pointer 337 * 338 * Get the current rptr from the hardware (VEGA10+). 339 */ 340 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 341 { 342 u64 *rptr; 343 344 /* XXX check if swapping is necessary on BE */ 345 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 346 347 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 348 return ((*rptr) >> 2); 349 } 350 351 /** 352 * sdma_v4_0_ring_get_wptr - get the current write pointer 353 * 354 * @ring: amdgpu ring pointer 355 * 356 * Get the current wptr from the hardware (VEGA10+). 357 */ 358 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 359 { 360 struct amdgpu_device *adev = ring->adev; 361 u64 wptr; 362 363 if (ring->use_doorbell) { 364 /* XXX check if swapping is necessary on BE */ 365 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 366 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 367 } else { 368 u32 lowbit, highbit; 369 370 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2; 371 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 372 373 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 374 ring->me, highbit, lowbit); 375 wptr = highbit; 376 wptr = wptr << 32; 377 wptr |= lowbit; 378 } 379 380 return wptr >> 2; 381 } 382 383 /** 384 * sdma_v4_0_ring_set_wptr - commit the write pointer 385 * 386 * @ring: amdgpu ring pointer 387 * 388 * Write the wptr back to the hardware (VEGA10+). 389 */ 390 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 391 { 392 struct amdgpu_device *adev = ring->adev; 393 394 DRM_DEBUG("Setting write pointer\n"); 395 if (ring->use_doorbell) { 396 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 397 398 DRM_DEBUG("Using doorbell -- " 399 "wptr_offs == 0x%08x " 400 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 401 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 402 ring->wptr_offs, 403 lower_32_bits(ring->wptr << 2), 404 upper_32_bits(ring->wptr << 2)); 405 /* XXX check if swapping is necessary on BE */ 406 WRITE_ONCE(*wb, (ring->wptr << 2)); 407 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 408 ring->doorbell_index, ring->wptr << 2); 409 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 410 } else { 411 DRM_DEBUG("Not using doorbell -- " 412 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 413 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 414 ring->me, 415 lower_32_bits(ring->wptr << 2), 416 ring->me, 417 upper_32_bits(ring->wptr << 2)); 418 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 419 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 420 } 421 } 422 423 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 424 { 425 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 426 int i; 427 428 for (i = 0; i < count; i++) 429 if (sdma && sdma->burst_nop && (i == 0)) 430 amdgpu_ring_write(ring, ring->funcs->nop | 431 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 432 else 433 amdgpu_ring_write(ring, ring->funcs->nop); 434 } 435 436 /** 437 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 438 * 439 * @ring: amdgpu ring pointer 440 * @ib: IB object to schedule 441 * 442 * Schedule an IB in the DMA ring (VEGA10). 443 */ 444 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 445 struct amdgpu_ib *ib, 446 unsigned vmid, bool ctx_switch) 447 { 448 /* IB packet must end on a 8 DW boundary */ 449 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 450 451 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 452 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 453 /* base must be 32 byte aligned */ 454 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 455 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 456 amdgpu_ring_write(ring, ib->length_dw); 457 amdgpu_ring_write(ring, 0); 458 amdgpu_ring_write(ring, 0); 459 460 } 461 462 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 463 int mem_space, int hdp, 464 uint32_t addr0, uint32_t addr1, 465 uint32_t ref, uint32_t mask, 466 uint32_t inv) 467 { 468 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 469 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 470 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 471 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 472 if (mem_space) { 473 /* memory */ 474 amdgpu_ring_write(ring, addr0); 475 amdgpu_ring_write(ring, addr1); 476 } else { 477 /* registers */ 478 amdgpu_ring_write(ring, addr0 << 2); 479 amdgpu_ring_write(ring, addr1 << 2); 480 } 481 amdgpu_ring_write(ring, ref); /* reference */ 482 amdgpu_ring_write(ring, mask); /* mask */ 483 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 484 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 485 } 486 487 /** 488 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 489 * 490 * @ring: amdgpu ring pointer 491 * 492 * Emit an hdp flush packet on the requested DMA ring. 493 */ 494 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 495 { 496 struct amdgpu_device *adev = ring->adev; 497 u32 ref_and_mask = 0; 498 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 499 500 if (ring->me == 0) 501 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 502 else 503 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 504 505 sdma_v4_0_wait_reg_mem(ring, 0, 1, 506 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 507 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 508 ref_and_mask, ref_and_mask, 10); 509 } 510 511 /** 512 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 513 * 514 * @ring: amdgpu ring pointer 515 * @fence: amdgpu fence object 516 * 517 * Add a DMA fence packet to the ring to write 518 * the fence seq number and DMA trap packet to generate 519 * an interrupt if needed (VEGA10). 520 */ 521 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 522 unsigned flags) 523 { 524 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 525 /* write the fence */ 526 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 527 /* zero in first two bits */ 528 BUG_ON(addr & 0x3); 529 amdgpu_ring_write(ring, lower_32_bits(addr)); 530 amdgpu_ring_write(ring, upper_32_bits(addr)); 531 amdgpu_ring_write(ring, lower_32_bits(seq)); 532 533 /* optionally write high bits as well */ 534 if (write64bit) { 535 addr += 4; 536 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 537 /* zero in first two bits */ 538 BUG_ON(addr & 0x3); 539 amdgpu_ring_write(ring, lower_32_bits(addr)); 540 amdgpu_ring_write(ring, upper_32_bits(addr)); 541 amdgpu_ring_write(ring, upper_32_bits(seq)); 542 } 543 544 /* generate an interrupt */ 545 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 546 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 547 } 548 549 550 /** 551 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 552 * 553 * @adev: amdgpu_device pointer 554 * 555 * Stop the gfx async dma ring buffers (VEGA10). 556 */ 557 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 558 { 559 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 560 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 561 u32 rb_cntl, ib_cntl; 562 int i; 563 564 if ((adev->mman.buffer_funcs_ring == sdma0) || 565 (adev->mman.buffer_funcs_ring == sdma1)) 566 amdgpu_ttm_set_buffer_funcs_status(adev, false); 567 568 for (i = 0; i < adev->sdma.num_instances; i++) { 569 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 570 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 571 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 572 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 573 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 574 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 575 } 576 577 sdma0->ready = false; 578 sdma1->ready = false; 579 } 580 581 /** 582 * sdma_v4_0_rlc_stop - stop the compute async dma engines 583 * 584 * @adev: amdgpu_device pointer 585 * 586 * Stop the compute async dma queues (VEGA10). 587 */ 588 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 589 { 590 /* XXX todo */ 591 } 592 593 /** 594 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 595 * 596 * @adev: amdgpu_device pointer 597 * @enable: enable/disable the DMA MEs context switch. 598 * 599 * Halt or unhalt the async dma engines context switch (VEGA10). 600 */ 601 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 602 { 603 u32 f32_cntl, phase_quantum = 0; 604 int i; 605 606 if (amdgpu_sdma_phase_quantum) { 607 unsigned value = amdgpu_sdma_phase_quantum; 608 unsigned unit = 0; 609 610 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 611 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 612 value = (value + 1) >> 1; 613 unit++; 614 } 615 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 616 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 617 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 618 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 619 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 620 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 621 WARN_ONCE(1, 622 "clamping sdma_phase_quantum to %uK clock cycles\n", 623 value << unit); 624 } 625 phase_quantum = 626 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 627 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 628 } 629 630 for (i = 0; i < adev->sdma.num_instances; i++) { 631 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 632 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 633 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 634 if (enable && amdgpu_sdma_phase_quantum) { 635 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 636 phase_quantum); 637 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 638 phase_quantum); 639 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 640 phase_quantum); 641 } 642 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 643 } 644 645 } 646 647 /** 648 * sdma_v4_0_enable - stop the async dma engines 649 * 650 * @adev: amdgpu_device pointer 651 * @enable: enable/disable the DMA MEs. 652 * 653 * Halt or unhalt the async dma engines (VEGA10). 654 */ 655 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 656 { 657 u32 f32_cntl; 658 int i; 659 660 if (enable == false) { 661 sdma_v4_0_gfx_stop(adev); 662 sdma_v4_0_rlc_stop(adev); 663 } 664 665 for (i = 0; i < adev->sdma.num_instances; i++) { 666 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 667 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 668 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 669 } 670 } 671 672 /** 673 * sdma_v4_0_gfx_resume - setup and start the async dma engines 674 * 675 * @adev: amdgpu_device pointer 676 * 677 * Set up the gfx DMA ring buffers and enable them (VEGA10). 678 * Returns 0 for success, error for failure. 679 */ 680 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) 681 { 682 struct amdgpu_ring *ring; 683 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 684 u32 rb_bufsz; 685 u32 wb_offset; 686 u32 doorbell; 687 u32 doorbell_offset; 688 u32 temp; 689 u64 wptr_gpu_addr; 690 int i, r; 691 692 for (i = 0; i < adev->sdma.num_instances; i++) { 693 ring = &adev->sdma.instance[i].ring; 694 wb_offset = (ring->rptr_offs * 4); 695 696 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 697 698 /* Set ring buffer size in dwords */ 699 rb_bufsz = order_base_2(ring->ring_size / 4); 700 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 701 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 702 #ifdef __BIG_ENDIAN 703 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 704 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 705 RPTR_WRITEBACK_SWAP_ENABLE, 1); 706 #endif 707 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 708 709 /* Initialize the ring buffer's read and write pointers */ 710 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 711 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 712 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 713 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 714 715 /* set the wb address whether it's enabled or not */ 716 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 717 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 718 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 719 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 720 721 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 722 723 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 724 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 725 726 ring->wptr = 0; 727 728 /* before programing wptr to a less value, need set minor_ptr_update first */ 729 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 730 731 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 732 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 733 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 734 } 735 736 doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 737 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 738 739 if (ring->use_doorbell) { 740 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 741 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 742 OFFSET, ring->doorbell_index); 743 } else { 744 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 745 } 746 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 747 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 748 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 749 ring->doorbell_index); 750 751 if (amdgpu_sriov_vf(adev)) 752 sdma_v4_0_ring_set_wptr(ring); 753 754 /* set minor_ptr_update to 0 after wptr programed */ 755 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 756 757 /* set utc l1 enable flag always to 1 */ 758 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 759 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 760 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 761 762 if (!amdgpu_sriov_vf(adev)) { 763 /* unhalt engine */ 764 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 765 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 766 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 767 } 768 769 /* setup the wptr shadow polling */ 770 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 771 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 772 lower_32_bits(wptr_gpu_addr)); 773 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 774 upper_32_bits(wptr_gpu_addr)); 775 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 776 if (amdgpu_sriov_vf(adev)) 777 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); 778 else 779 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0); 780 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl); 781 782 /* enable DMA RB */ 783 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 784 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 785 786 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 787 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 788 #ifdef __BIG_ENDIAN 789 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 790 #endif 791 /* enable DMA IBs */ 792 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 793 794 ring->ready = true; 795 796 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 797 sdma_v4_0_ctx_switch_enable(adev, true); 798 sdma_v4_0_enable(adev, true); 799 } 800 801 r = amdgpu_ring_test_ring(ring); 802 if (r) { 803 ring->ready = false; 804 return r; 805 } 806 807 if (adev->mman.buffer_funcs_ring == ring) 808 amdgpu_ttm_set_buffer_funcs_status(adev, true); 809 810 } 811 812 return 0; 813 } 814 815 static void 816 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 817 { 818 uint32_t def, data; 819 820 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 821 /* disable idle interrupt */ 822 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 823 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 824 825 if (data != def) 826 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 827 } else { 828 /* disable idle interrupt */ 829 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 830 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 831 if (data != def) 832 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 833 } 834 } 835 836 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 837 { 838 uint32_t def, data; 839 840 /* Enable HW based PG. */ 841 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 842 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 843 if (data != def) 844 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 845 846 /* enable interrupt */ 847 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 848 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 849 if (data != def) 850 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 851 852 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 853 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 854 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 855 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 856 /* Configure switch time for hysteresis purpose. Use default right now */ 857 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 858 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 859 if(data != def) 860 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 861 } 862 863 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 864 { 865 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 866 return; 867 868 switch (adev->asic_type) { 869 case CHIP_RAVEN: 870 sdma_v4_1_init_power_gating(adev); 871 sdma_v4_1_update_power_gating(adev, true); 872 break; 873 default: 874 break; 875 } 876 } 877 878 /** 879 * sdma_v4_0_rlc_resume - setup and start the async dma engines 880 * 881 * @adev: amdgpu_device pointer 882 * 883 * Set up the compute DMA queues and enable them (VEGA10). 884 * Returns 0 for success, error for failure. 885 */ 886 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 887 { 888 sdma_v4_0_init_pg(adev); 889 890 return 0; 891 } 892 893 /** 894 * sdma_v4_0_load_microcode - load the sDMA ME ucode 895 * 896 * @adev: amdgpu_device pointer 897 * 898 * Loads the sDMA0/1 ucode. 899 * Returns 0 for success, -EINVAL if the ucode is not available. 900 */ 901 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 902 { 903 const struct sdma_firmware_header_v1_0 *hdr; 904 const __le32 *fw_data; 905 u32 fw_size; 906 int i, j; 907 908 /* halt the MEs */ 909 sdma_v4_0_enable(adev, false); 910 911 for (i = 0; i < adev->sdma.num_instances; i++) { 912 if (!adev->sdma.instance[i].fw) 913 return -EINVAL; 914 915 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 916 amdgpu_ucode_print_sdma_hdr(&hdr->header); 917 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 918 919 fw_data = (const __le32 *) 920 (adev->sdma.instance[i].fw->data + 921 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 922 923 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 924 925 for (j = 0; j < fw_size; j++) 926 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 927 928 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 929 } 930 931 return 0; 932 } 933 934 /** 935 * sdma_v4_0_start - setup and start the async dma engines 936 * 937 * @adev: amdgpu_device pointer 938 * 939 * Set up the DMA engines and enable them (VEGA10). 940 * Returns 0 for success, error for failure. 941 */ 942 static int sdma_v4_0_start(struct amdgpu_device *adev) 943 { 944 int r = 0; 945 946 if (amdgpu_sriov_vf(adev)) { 947 sdma_v4_0_ctx_switch_enable(adev, false); 948 sdma_v4_0_enable(adev, false); 949 950 /* set RB registers */ 951 r = sdma_v4_0_gfx_resume(adev); 952 return r; 953 } 954 955 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 956 r = sdma_v4_0_load_microcode(adev); 957 if (r) 958 return r; 959 } 960 961 /* unhalt the MEs */ 962 sdma_v4_0_enable(adev, true); 963 /* enable sdma ring preemption */ 964 sdma_v4_0_ctx_switch_enable(adev, true); 965 966 /* start the gfx rings and rlc compute queues */ 967 r = sdma_v4_0_gfx_resume(adev); 968 if (r) 969 return r; 970 r = sdma_v4_0_rlc_resume(adev); 971 972 return r; 973 } 974 975 /** 976 * sdma_v4_0_ring_test_ring - simple async dma engine test 977 * 978 * @ring: amdgpu_ring structure holding ring information 979 * 980 * Test the DMA engine by writing using it to write an 981 * value to memory. (VEGA10). 982 * Returns 0 for success, error for failure. 983 */ 984 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 985 { 986 struct amdgpu_device *adev = ring->adev; 987 unsigned i; 988 unsigned index; 989 int r; 990 u32 tmp; 991 u64 gpu_addr; 992 993 r = amdgpu_device_wb_get(adev, &index); 994 if (r) { 995 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 996 return r; 997 } 998 999 gpu_addr = adev->wb.gpu_addr + (index * 4); 1000 tmp = 0xCAFEDEAD; 1001 adev->wb.wb[index] = cpu_to_le32(tmp); 1002 1003 r = amdgpu_ring_alloc(ring, 5); 1004 if (r) { 1005 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 1006 amdgpu_device_wb_free(adev, index); 1007 return r; 1008 } 1009 1010 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1011 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 1012 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 1013 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 1014 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 1015 amdgpu_ring_write(ring, 0xDEADBEEF); 1016 amdgpu_ring_commit(ring); 1017 1018 for (i = 0; i < adev->usec_timeout; i++) { 1019 tmp = le32_to_cpu(adev->wb.wb[index]); 1020 if (tmp == 0xDEADBEEF) 1021 break; 1022 DRM_UDELAY(1); 1023 } 1024 1025 if (i < adev->usec_timeout) { 1026 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 1027 } else { 1028 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 1029 ring->idx, tmp); 1030 r = -EINVAL; 1031 } 1032 amdgpu_device_wb_free(adev, index); 1033 1034 return r; 1035 } 1036 1037 /** 1038 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 1039 * 1040 * @ring: amdgpu_ring structure holding ring information 1041 * 1042 * Test a simple IB in the DMA ring (VEGA10). 1043 * Returns 0 on success, error on failure. 1044 */ 1045 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1046 { 1047 struct amdgpu_device *adev = ring->adev; 1048 struct amdgpu_ib ib; 1049 struct dma_fence *f = NULL; 1050 unsigned index; 1051 long r; 1052 u32 tmp = 0; 1053 u64 gpu_addr; 1054 1055 r = amdgpu_device_wb_get(adev, &index); 1056 if (r) { 1057 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 1058 return r; 1059 } 1060 1061 gpu_addr = adev->wb.gpu_addr + (index * 4); 1062 tmp = 0xCAFEDEAD; 1063 adev->wb.wb[index] = cpu_to_le32(tmp); 1064 memset(&ib, 0, sizeof(ib)); 1065 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1066 if (r) { 1067 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1068 goto err0; 1069 } 1070 1071 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1072 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1073 ib.ptr[1] = lower_32_bits(gpu_addr); 1074 ib.ptr[2] = upper_32_bits(gpu_addr); 1075 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1076 ib.ptr[4] = 0xDEADBEEF; 1077 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1078 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1079 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1080 ib.length_dw = 8; 1081 1082 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1083 if (r) 1084 goto err1; 1085 1086 r = dma_fence_wait_timeout(f, false, timeout); 1087 if (r == 0) { 1088 DRM_ERROR("amdgpu: IB test timed out\n"); 1089 r = -ETIMEDOUT; 1090 goto err1; 1091 } else if (r < 0) { 1092 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1093 goto err1; 1094 } 1095 tmp = le32_to_cpu(adev->wb.wb[index]); 1096 if (tmp == 0xDEADBEEF) { 1097 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 1098 r = 0; 1099 } else { 1100 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 1101 r = -EINVAL; 1102 } 1103 err1: 1104 amdgpu_ib_free(adev, &ib, NULL); 1105 dma_fence_put(f); 1106 err0: 1107 amdgpu_device_wb_free(adev, index); 1108 return r; 1109 } 1110 1111 1112 /** 1113 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1114 * 1115 * @ib: indirect buffer to fill with commands 1116 * @pe: addr of the page entry 1117 * @src: src addr to copy from 1118 * @count: number of page entries to update 1119 * 1120 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1121 */ 1122 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1123 uint64_t pe, uint64_t src, 1124 unsigned count) 1125 { 1126 unsigned bytes = count * 8; 1127 1128 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1129 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1130 ib->ptr[ib->length_dw++] = bytes - 1; 1131 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1132 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1133 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1134 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1135 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1136 1137 } 1138 1139 /** 1140 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1141 * 1142 * @ib: indirect buffer to fill with commands 1143 * @pe: addr of the page entry 1144 * @addr: dst addr to write into pe 1145 * @count: number of page entries to update 1146 * @incr: increase next addr by incr bytes 1147 * @flags: access flags 1148 * 1149 * Update PTEs by writing them manually using sDMA (VEGA10). 1150 */ 1151 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1152 uint64_t value, unsigned count, 1153 uint32_t incr) 1154 { 1155 unsigned ndw = count * 2; 1156 1157 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1158 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1159 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1160 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1161 ib->ptr[ib->length_dw++] = ndw - 1; 1162 for (; ndw > 0; ndw -= 2) { 1163 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1164 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1165 value += incr; 1166 } 1167 } 1168 1169 /** 1170 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1171 * 1172 * @ib: indirect buffer to fill with commands 1173 * @pe: addr of the page entry 1174 * @addr: dst addr to write into pe 1175 * @count: number of page entries to update 1176 * @incr: increase next addr by incr bytes 1177 * @flags: access flags 1178 * 1179 * Update the page tables using sDMA (VEGA10). 1180 */ 1181 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1182 uint64_t pe, 1183 uint64_t addr, unsigned count, 1184 uint32_t incr, uint64_t flags) 1185 { 1186 /* for physically contiguous pages (vram) */ 1187 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1188 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1189 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1190 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1191 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1192 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1193 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1194 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1195 ib->ptr[ib->length_dw++] = 0; 1196 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1197 } 1198 1199 /** 1200 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1201 * 1202 * @ib: indirect buffer to fill with padding 1203 * 1204 */ 1205 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1206 { 1207 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1208 u32 pad_count; 1209 int i; 1210 1211 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1212 for (i = 0; i < pad_count; i++) 1213 if (sdma && sdma->burst_nop && (i == 0)) 1214 ib->ptr[ib->length_dw++] = 1215 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1216 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1217 else 1218 ib->ptr[ib->length_dw++] = 1219 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1220 } 1221 1222 1223 /** 1224 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1225 * 1226 * @ring: amdgpu_ring pointer 1227 * 1228 * Make sure all previous operations are completed (CIK). 1229 */ 1230 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1231 { 1232 uint32_t seq = ring->fence_drv.sync_seq; 1233 uint64_t addr = ring->fence_drv.gpu_addr; 1234 1235 /* wait for idle */ 1236 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1237 addr & 0xfffffffc, 1238 upper_32_bits(addr) & 0xffffffff, 1239 seq, 0xffffffff, 4); 1240 } 1241 1242 1243 /** 1244 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1245 * 1246 * @ring: amdgpu_ring pointer 1247 * @vm: amdgpu_vm pointer 1248 * 1249 * Update the page table base and flush the VM TLB 1250 * using sDMA (VEGA10). 1251 */ 1252 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1253 unsigned vmid, uint64_t pd_addr) 1254 { 1255 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1256 } 1257 1258 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1259 uint32_t reg, uint32_t val) 1260 { 1261 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1262 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1263 amdgpu_ring_write(ring, reg); 1264 amdgpu_ring_write(ring, val); 1265 } 1266 1267 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1268 uint32_t val, uint32_t mask) 1269 { 1270 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1271 } 1272 1273 static int sdma_v4_0_early_init(void *handle) 1274 { 1275 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1276 1277 if (adev->asic_type == CHIP_RAVEN) 1278 adev->sdma.num_instances = 1; 1279 else 1280 adev->sdma.num_instances = 2; 1281 1282 sdma_v4_0_set_ring_funcs(adev); 1283 sdma_v4_0_set_buffer_funcs(adev); 1284 sdma_v4_0_set_vm_pte_funcs(adev); 1285 sdma_v4_0_set_irq_funcs(adev); 1286 1287 return 0; 1288 } 1289 1290 1291 static int sdma_v4_0_sw_init(void *handle) 1292 { 1293 struct amdgpu_ring *ring; 1294 int r, i; 1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1296 1297 /* SDMA trap event */ 1298 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP, 1299 &adev->sdma.trap_irq); 1300 if (r) 1301 return r; 1302 1303 /* SDMA trap event */ 1304 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP, 1305 &adev->sdma.trap_irq); 1306 if (r) 1307 return r; 1308 1309 r = sdma_v4_0_init_microcode(adev); 1310 if (r) { 1311 DRM_ERROR("Failed to load sdma firmware!\n"); 1312 return r; 1313 } 1314 1315 for (i = 0; i < adev->sdma.num_instances; i++) { 1316 ring = &adev->sdma.instance[i].ring; 1317 ring->ring_obj = NULL; 1318 ring->use_doorbell = true; 1319 1320 DRM_INFO("use_doorbell being set to: [%s]\n", 1321 ring->use_doorbell?"true":"false"); 1322 1323 ring->doorbell_index = (i == 0) ? 1324 (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset 1325 : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset 1326 1327 sprintf(ring->name, "sdma%d", i); 1328 r = amdgpu_ring_init(adev, ring, 1024, 1329 &adev->sdma.trap_irq, 1330 (i == 0) ? 1331 AMDGPU_SDMA_IRQ_TRAP0 : 1332 AMDGPU_SDMA_IRQ_TRAP1); 1333 if (r) 1334 return r; 1335 } 1336 1337 return r; 1338 } 1339 1340 static int sdma_v4_0_sw_fini(void *handle) 1341 { 1342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1343 int i; 1344 1345 for (i = 0; i < adev->sdma.num_instances; i++) 1346 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1347 1348 for (i = 0; i < adev->sdma.num_instances; i++) { 1349 release_firmware(adev->sdma.instance[i].fw); 1350 adev->sdma.instance[i].fw = NULL; 1351 } 1352 1353 return 0; 1354 } 1355 1356 static int sdma_v4_0_hw_init(void *handle) 1357 { 1358 int r; 1359 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1360 1361 sdma_v4_0_init_golden_registers(adev); 1362 1363 r = sdma_v4_0_start(adev); 1364 1365 return r; 1366 } 1367 1368 static int sdma_v4_0_hw_fini(void *handle) 1369 { 1370 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1371 1372 if (amdgpu_sriov_vf(adev)) 1373 return 0; 1374 1375 sdma_v4_0_ctx_switch_enable(adev, false); 1376 sdma_v4_0_enable(adev, false); 1377 1378 return 0; 1379 } 1380 1381 static int sdma_v4_0_suspend(void *handle) 1382 { 1383 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1384 1385 return sdma_v4_0_hw_fini(adev); 1386 } 1387 1388 static int sdma_v4_0_resume(void *handle) 1389 { 1390 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1391 1392 return sdma_v4_0_hw_init(adev); 1393 } 1394 1395 static bool sdma_v4_0_is_idle(void *handle) 1396 { 1397 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1398 u32 i; 1399 1400 for (i = 0; i < adev->sdma.num_instances; i++) { 1401 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1402 1403 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1404 return false; 1405 } 1406 1407 return true; 1408 } 1409 1410 static int sdma_v4_0_wait_for_idle(void *handle) 1411 { 1412 unsigned i; 1413 u32 sdma0, sdma1; 1414 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1415 1416 for (i = 0; i < adev->usec_timeout; i++) { 1417 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1418 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1419 1420 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1421 return 0; 1422 udelay(1); 1423 } 1424 return -ETIMEDOUT; 1425 } 1426 1427 static int sdma_v4_0_soft_reset(void *handle) 1428 { 1429 /* todo */ 1430 1431 return 0; 1432 } 1433 1434 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1435 struct amdgpu_irq_src *source, 1436 unsigned type, 1437 enum amdgpu_interrupt_state state) 1438 { 1439 u32 sdma_cntl; 1440 1441 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 1442 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1443 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1444 1445 sdma_cntl = RREG32(reg_offset); 1446 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1447 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1448 WREG32(reg_offset, sdma_cntl); 1449 1450 return 0; 1451 } 1452 1453 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1454 struct amdgpu_irq_src *source, 1455 struct amdgpu_iv_entry *entry) 1456 { 1457 DRM_DEBUG("IH: SDMA trap\n"); 1458 switch (entry->client_id) { 1459 case SOC15_IH_CLIENTID_SDMA0: 1460 switch (entry->ring_id) { 1461 case 0: 1462 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1463 break; 1464 case 1: 1465 /* XXX compute */ 1466 break; 1467 case 2: 1468 /* XXX compute */ 1469 break; 1470 case 3: 1471 /* XXX page queue*/ 1472 break; 1473 } 1474 break; 1475 case SOC15_IH_CLIENTID_SDMA1: 1476 switch (entry->ring_id) { 1477 case 0: 1478 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1479 break; 1480 case 1: 1481 /* XXX compute */ 1482 break; 1483 case 2: 1484 /* XXX compute */ 1485 break; 1486 case 3: 1487 /* XXX page queue*/ 1488 break; 1489 } 1490 break; 1491 } 1492 return 0; 1493 } 1494 1495 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1496 struct amdgpu_irq_src *source, 1497 struct amdgpu_iv_entry *entry) 1498 { 1499 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1500 schedule_work(&adev->reset_work); 1501 return 0; 1502 } 1503 1504 1505 static void sdma_v4_0_update_medium_grain_clock_gating( 1506 struct amdgpu_device *adev, 1507 bool enable) 1508 { 1509 uint32_t data, def; 1510 1511 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1512 /* enable sdma0 clock gating */ 1513 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1514 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1515 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1516 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1517 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1518 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1519 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1520 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1521 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1522 if (def != data) 1523 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1524 1525 if (adev->sdma.num_instances > 1) { 1526 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1527 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1528 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1529 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1530 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1531 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1532 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1533 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1534 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1535 if (def != data) 1536 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1537 } 1538 } else { 1539 /* disable sdma0 clock gating */ 1540 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1541 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1542 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1543 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1544 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1545 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1546 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1547 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1548 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1549 1550 if (def != data) 1551 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1552 1553 if (adev->sdma.num_instances > 1) { 1554 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1555 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1556 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1557 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1558 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1559 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1560 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1561 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1562 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1563 if (def != data) 1564 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1565 } 1566 } 1567 } 1568 1569 1570 static void sdma_v4_0_update_medium_grain_light_sleep( 1571 struct amdgpu_device *adev, 1572 bool enable) 1573 { 1574 uint32_t data, def; 1575 1576 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1577 /* 1-not override: enable sdma0 mem light sleep */ 1578 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1579 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1580 if (def != data) 1581 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1582 1583 /* 1-not override: enable sdma1 mem light sleep */ 1584 if (adev->sdma.num_instances > 1) { 1585 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1586 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1587 if (def != data) 1588 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1589 } 1590 } else { 1591 /* 0-override:disable sdma0 mem light sleep */ 1592 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1593 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1594 if (def != data) 1595 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1596 1597 /* 0-override:disable sdma1 mem light sleep */ 1598 if (adev->sdma.num_instances > 1) { 1599 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1600 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1601 if (def != data) 1602 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1603 } 1604 } 1605 } 1606 1607 static int sdma_v4_0_set_clockgating_state(void *handle, 1608 enum amd_clockgating_state state) 1609 { 1610 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1611 1612 if (amdgpu_sriov_vf(adev)) 1613 return 0; 1614 1615 switch (adev->asic_type) { 1616 case CHIP_VEGA10: 1617 case CHIP_VEGA12: 1618 case CHIP_VEGA20: 1619 case CHIP_RAVEN: 1620 sdma_v4_0_update_medium_grain_clock_gating(adev, 1621 state == AMD_CG_STATE_GATE ? true : false); 1622 sdma_v4_0_update_medium_grain_light_sleep(adev, 1623 state == AMD_CG_STATE_GATE ? true : false); 1624 break; 1625 default: 1626 break; 1627 } 1628 return 0; 1629 } 1630 1631 static int sdma_v4_0_set_powergating_state(void *handle, 1632 enum amd_powergating_state state) 1633 { 1634 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1635 1636 switch (adev->asic_type) { 1637 case CHIP_RAVEN: 1638 sdma_v4_1_update_power_gating(adev, 1639 state == AMD_PG_STATE_GATE ? true : false); 1640 break; 1641 default: 1642 break; 1643 } 1644 1645 return 0; 1646 } 1647 1648 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 1649 { 1650 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1651 int data; 1652 1653 if (amdgpu_sriov_vf(adev)) 1654 *flags = 0; 1655 1656 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1657 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1658 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1659 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1660 1661 /* AMD_CG_SUPPORT_SDMA_LS */ 1662 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1663 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1664 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1665 } 1666 1667 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 1668 .name = "sdma_v4_0", 1669 .early_init = sdma_v4_0_early_init, 1670 .late_init = NULL, 1671 .sw_init = sdma_v4_0_sw_init, 1672 .sw_fini = sdma_v4_0_sw_fini, 1673 .hw_init = sdma_v4_0_hw_init, 1674 .hw_fini = sdma_v4_0_hw_fini, 1675 .suspend = sdma_v4_0_suspend, 1676 .resume = sdma_v4_0_resume, 1677 .is_idle = sdma_v4_0_is_idle, 1678 .wait_for_idle = sdma_v4_0_wait_for_idle, 1679 .soft_reset = sdma_v4_0_soft_reset, 1680 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 1681 .set_powergating_state = sdma_v4_0_set_powergating_state, 1682 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 1683 }; 1684 1685 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 1686 .type = AMDGPU_RING_TYPE_SDMA, 1687 .align_mask = 0xf, 1688 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1689 .support_64bit_ptrs = true, 1690 .vmhub = AMDGPU_MMHUB, 1691 .get_rptr = sdma_v4_0_ring_get_rptr, 1692 .get_wptr = sdma_v4_0_ring_get_wptr, 1693 .set_wptr = sdma_v4_0_ring_set_wptr, 1694 .emit_frame_size = 1695 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1696 3 + /* hdp invalidate */ 1697 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1698 /* sdma_v4_0_ring_emit_vm_flush */ 1699 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1700 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1701 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1702 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1703 .emit_ib = sdma_v4_0_ring_emit_ib, 1704 .emit_fence = sdma_v4_0_ring_emit_fence, 1705 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1706 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1707 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1708 .test_ring = sdma_v4_0_ring_test_ring, 1709 .test_ib = sdma_v4_0_ring_test_ib, 1710 .insert_nop = sdma_v4_0_ring_insert_nop, 1711 .pad_ib = sdma_v4_0_ring_pad_ib, 1712 .emit_wreg = sdma_v4_0_ring_emit_wreg, 1713 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 1714 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1715 }; 1716 1717 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 1718 { 1719 int i; 1720 1721 for (i = 0; i < adev->sdma.num_instances; i++) { 1722 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 1723 adev->sdma.instance[i].ring.me = i; 1724 } 1725 } 1726 1727 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 1728 .set = sdma_v4_0_set_trap_irq_state, 1729 .process = sdma_v4_0_process_trap_irq, 1730 }; 1731 1732 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 1733 .process = sdma_v4_0_process_illegal_inst_irq, 1734 }; 1735 1736 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 1737 { 1738 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1739 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 1740 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 1741 } 1742 1743 /** 1744 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 1745 * 1746 * @ring: amdgpu_ring structure holding ring information 1747 * @src_offset: src GPU address 1748 * @dst_offset: dst GPU address 1749 * @byte_count: number of bytes to xfer 1750 * 1751 * Copy GPU buffers using the DMA engine (VEGA10/12). 1752 * Used by the amdgpu ttm implementation to move pages if 1753 * registered as the asic copy callback. 1754 */ 1755 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 1756 uint64_t src_offset, 1757 uint64_t dst_offset, 1758 uint32_t byte_count) 1759 { 1760 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1761 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1762 ib->ptr[ib->length_dw++] = byte_count - 1; 1763 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1764 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1765 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1766 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1767 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1768 } 1769 1770 /** 1771 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 1772 * 1773 * @ring: amdgpu_ring structure holding ring information 1774 * @src_data: value to write to buffer 1775 * @dst_offset: dst GPU address 1776 * @byte_count: number of bytes to xfer 1777 * 1778 * Fill GPU buffers using the DMA engine (VEGA10/12). 1779 */ 1780 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 1781 uint32_t src_data, 1782 uint64_t dst_offset, 1783 uint32_t byte_count) 1784 { 1785 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1786 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1787 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1788 ib->ptr[ib->length_dw++] = src_data; 1789 ib->ptr[ib->length_dw++] = byte_count - 1; 1790 } 1791 1792 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 1793 .copy_max_bytes = 0x400000, 1794 .copy_num_dw = 7, 1795 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 1796 1797 .fill_max_bytes = 0x400000, 1798 .fill_num_dw = 5, 1799 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 1800 }; 1801 1802 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 1803 { 1804 if (adev->mman.buffer_funcs == NULL) { 1805 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 1806 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1807 } 1808 } 1809 1810 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 1811 .copy_pte_num_dw = 7, 1812 .copy_pte = sdma_v4_0_vm_copy_pte, 1813 1814 .write_pte = sdma_v4_0_vm_write_pte, 1815 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 1816 }; 1817 1818 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1819 { 1820 struct drm_gpu_scheduler *sched; 1821 unsigned i; 1822 1823 if (adev->vm_manager.vm_pte_funcs == NULL) { 1824 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 1825 for (i = 0; i < adev->sdma.num_instances; i++) { 1826 sched = &adev->sdma.instance[i].ring.sched; 1827 adev->vm_manager.vm_pte_rqs[i] = 1828 &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL]; 1829 } 1830 adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances; 1831 } 1832 } 1833 1834 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 1835 .type = AMD_IP_BLOCK_TYPE_SDMA, 1836 .major = 4, 1837 .minor = 0, 1838 .rev = 0, 1839 .funcs = &sdma_v4_0_ip_funcs, 1840 }; 1841