1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "sdma0/sdma0_4_0_offset.h" 31 #include "sdma0/sdma0_4_0_sh_mask.h" 32 #include "sdma1/sdma1_4_0_offset.h" 33 #include "sdma1/sdma1_4_0_sh_mask.h" 34 #include "mmhub/mmhub_1_0_offset.h" 35 #include "mmhub/mmhub_1_0_sh_mask.h" 36 #include "hdp/hdp_4_0_offset.h" 37 #include "sdma0/sdma0_4_1_default.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "vega10_sdma_pkt_open.h" 42 43 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 44 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 45 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 46 47 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 48 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 49 50 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 51 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 52 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 53 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 54 55 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 56 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 57 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 58 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 59 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 60 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 61 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 62 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 63 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 64 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 65 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 66 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 68 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 69 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 70 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 71 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 73 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 75 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 76 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 77 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 78 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0) 80 }; 81 82 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 83 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 84 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 85 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 86 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 87 }; 88 89 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = 90 { 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0) 101 }; 102 103 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 104 { 105 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 106 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 107 }; 108 109 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 110 u32 instance, u32 offset) 111 { 112 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : 113 (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); 114 } 115 116 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 117 { 118 switch (adev->asic_type) { 119 case CHIP_VEGA10: 120 soc15_program_register_sequence(adev, 121 golden_settings_sdma_4, 122 ARRAY_SIZE(golden_settings_sdma_4)); 123 soc15_program_register_sequence(adev, 124 golden_settings_sdma_vg10, 125 ARRAY_SIZE(golden_settings_sdma_vg10)); 126 break; 127 case CHIP_RAVEN: 128 soc15_program_register_sequence(adev, 129 golden_settings_sdma_4_1, 130 ARRAY_SIZE(golden_settings_sdma_4_1)); 131 soc15_program_register_sequence(adev, 132 golden_settings_sdma_rv1, 133 ARRAY_SIZE(golden_settings_sdma_rv1)); 134 break; 135 default: 136 break; 137 } 138 } 139 140 /** 141 * sdma_v4_0_init_microcode - load ucode images from disk 142 * 143 * @adev: amdgpu_device pointer 144 * 145 * Use the firmware interface to load the ucode images into 146 * the driver (not loaded into hw). 147 * Returns 0 on success, error on failure. 148 */ 149 150 // emulation only, won't work on real chip 151 // vega10 real chip need to use PSP to load firmware 152 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 153 { 154 const char *chip_name; 155 char fw_name[30]; 156 int err = 0, i; 157 struct amdgpu_firmware_info *info = NULL; 158 const struct common_firmware_header *header = NULL; 159 const struct sdma_firmware_header_v1_0 *hdr; 160 161 DRM_DEBUG("\n"); 162 163 switch (adev->asic_type) { 164 case CHIP_VEGA10: 165 chip_name = "vega10"; 166 break; 167 case CHIP_RAVEN: 168 chip_name = "raven"; 169 break; 170 default: 171 BUG(); 172 } 173 174 for (i = 0; i < adev->sdma.num_instances; i++) { 175 if (i == 0) 176 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 177 else 178 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 179 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 180 if (err) 181 goto out; 182 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 183 if (err) 184 goto out; 185 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 186 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 187 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 188 if (adev->sdma.instance[i].feature_version >= 20) 189 adev->sdma.instance[i].burst_nop = true; 190 DRM_DEBUG("psp_load == '%s'\n", 191 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 192 193 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 194 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 195 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 196 info->fw = adev->sdma.instance[i].fw; 197 header = (const struct common_firmware_header *)info->fw->data; 198 adev->firmware.fw_size += 199 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 200 } 201 } 202 out: 203 if (err) { 204 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 205 for (i = 0; i < adev->sdma.num_instances; i++) { 206 release_firmware(adev->sdma.instance[i].fw); 207 adev->sdma.instance[i].fw = NULL; 208 } 209 } 210 return err; 211 } 212 213 /** 214 * sdma_v4_0_ring_get_rptr - get the current read pointer 215 * 216 * @ring: amdgpu ring pointer 217 * 218 * Get the current rptr from the hardware (VEGA10+). 219 */ 220 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 221 { 222 u64 *rptr; 223 224 /* XXX check if swapping is necessary on BE */ 225 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 226 227 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 228 return ((*rptr) >> 2); 229 } 230 231 /** 232 * sdma_v4_0_ring_get_wptr - get the current write pointer 233 * 234 * @ring: amdgpu ring pointer 235 * 236 * Get the current wptr from the hardware (VEGA10+). 237 */ 238 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 239 { 240 struct amdgpu_device *adev = ring->adev; 241 u64 wptr; 242 243 if (ring->use_doorbell) { 244 /* XXX check if swapping is necessary on BE */ 245 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 246 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 247 } else { 248 u32 lowbit, highbit; 249 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 250 251 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2; 252 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 253 254 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 255 me, highbit, lowbit); 256 wptr = highbit; 257 wptr = wptr << 32; 258 wptr |= lowbit; 259 } 260 261 return wptr >> 2; 262 } 263 264 /** 265 * sdma_v4_0_ring_set_wptr - commit the write pointer 266 * 267 * @ring: amdgpu ring pointer 268 * 269 * Write the wptr back to the hardware (VEGA10+). 270 */ 271 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 272 { 273 struct amdgpu_device *adev = ring->adev; 274 275 DRM_DEBUG("Setting write pointer\n"); 276 if (ring->use_doorbell) { 277 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 278 279 DRM_DEBUG("Using doorbell -- " 280 "wptr_offs == 0x%08x " 281 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 282 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 283 ring->wptr_offs, 284 lower_32_bits(ring->wptr << 2), 285 upper_32_bits(ring->wptr << 2)); 286 /* XXX check if swapping is necessary on BE */ 287 WRITE_ONCE(*wb, (ring->wptr << 2)); 288 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 289 ring->doorbell_index, ring->wptr << 2); 290 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 291 } else { 292 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 293 294 DRM_DEBUG("Not using doorbell -- " 295 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 296 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 297 me, 298 lower_32_bits(ring->wptr << 2), 299 me, 300 upper_32_bits(ring->wptr << 2)); 301 WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 302 WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 303 } 304 } 305 306 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 307 { 308 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 309 int i; 310 311 for (i = 0; i < count; i++) 312 if (sdma && sdma->burst_nop && (i == 0)) 313 amdgpu_ring_write(ring, ring->funcs->nop | 314 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 315 else 316 amdgpu_ring_write(ring, ring->funcs->nop); 317 } 318 319 /** 320 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 321 * 322 * @ring: amdgpu ring pointer 323 * @ib: IB object to schedule 324 * 325 * Schedule an IB in the DMA ring (VEGA10). 326 */ 327 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 328 struct amdgpu_ib *ib, 329 unsigned vmid, bool ctx_switch) 330 { 331 /* IB packet must end on a 8 DW boundary */ 332 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 333 334 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 335 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 336 /* base must be 32 byte aligned */ 337 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 338 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 339 amdgpu_ring_write(ring, ib->length_dw); 340 amdgpu_ring_write(ring, 0); 341 amdgpu_ring_write(ring, 0); 342 343 } 344 345 /** 346 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 347 * 348 * @ring: amdgpu ring pointer 349 * 350 * Emit an hdp flush packet on the requested DMA ring. 351 */ 352 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 353 { 354 struct amdgpu_device *adev = ring->adev; 355 u32 ref_and_mask = 0; 356 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 357 358 if (ring == &ring->adev->sdma.instance[0].ring) 359 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 360 else 361 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 362 363 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 364 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 365 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 366 amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2); 367 amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2); 368 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 369 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 370 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 371 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 372 } 373 374 static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 375 { 376 struct amdgpu_device *adev = ring->adev; 377 378 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 379 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 380 amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE)); 381 amdgpu_ring_write(ring, 1); 382 } 383 384 /** 385 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 386 * 387 * @ring: amdgpu ring pointer 388 * @fence: amdgpu fence object 389 * 390 * Add a DMA fence packet to the ring to write 391 * the fence seq number and DMA trap packet to generate 392 * an interrupt if needed (VEGA10). 393 */ 394 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 395 unsigned flags) 396 { 397 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 398 /* write the fence */ 399 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 400 /* zero in first two bits */ 401 BUG_ON(addr & 0x3); 402 amdgpu_ring_write(ring, lower_32_bits(addr)); 403 amdgpu_ring_write(ring, upper_32_bits(addr)); 404 amdgpu_ring_write(ring, lower_32_bits(seq)); 405 406 /* optionally write high bits as well */ 407 if (write64bit) { 408 addr += 4; 409 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 410 /* zero in first two bits */ 411 BUG_ON(addr & 0x3); 412 amdgpu_ring_write(ring, lower_32_bits(addr)); 413 amdgpu_ring_write(ring, upper_32_bits(addr)); 414 amdgpu_ring_write(ring, upper_32_bits(seq)); 415 } 416 417 /* generate an interrupt */ 418 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 419 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 420 } 421 422 423 /** 424 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 425 * 426 * @adev: amdgpu_device pointer 427 * 428 * Stop the gfx async dma ring buffers (VEGA10). 429 */ 430 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 431 { 432 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 433 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 434 u32 rb_cntl, ib_cntl; 435 int i; 436 437 if ((adev->mman.buffer_funcs_ring == sdma0) || 438 (adev->mman.buffer_funcs_ring == sdma1)) 439 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 440 441 for (i = 0; i < adev->sdma.num_instances; i++) { 442 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 443 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 444 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 445 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 446 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 447 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 448 } 449 450 sdma0->ready = false; 451 sdma1->ready = false; 452 } 453 454 /** 455 * sdma_v4_0_rlc_stop - stop the compute async dma engines 456 * 457 * @adev: amdgpu_device pointer 458 * 459 * Stop the compute async dma queues (VEGA10). 460 */ 461 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 462 { 463 /* XXX todo */ 464 } 465 466 /** 467 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 468 * 469 * @adev: amdgpu_device pointer 470 * @enable: enable/disable the DMA MEs context switch. 471 * 472 * Halt or unhalt the async dma engines context switch (VEGA10). 473 */ 474 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 475 { 476 u32 f32_cntl, phase_quantum = 0; 477 int i; 478 479 if (amdgpu_sdma_phase_quantum) { 480 unsigned value = amdgpu_sdma_phase_quantum; 481 unsigned unit = 0; 482 483 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 484 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 485 value = (value + 1) >> 1; 486 unit++; 487 } 488 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 489 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 490 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 491 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 492 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 493 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 494 WARN_ONCE(1, 495 "clamping sdma_phase_quantum to %uK clock cycles\n", 496 value << unit); 497 } 498 phase_quantum = 499 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 500 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 501 } 502 503 for (i = 0; i < adev->sdma.num_instances; i++) { 504 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 505 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 506 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 507 if (enable && amdgpu_sdma_phase_quantum) { 508 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 509 phase_quantum); 510 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 511 phase_quantum); 512 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 513 phase_quantum); 514 } 515 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 516 } 517 518 } 519 520 /** 521 * sdma_v4_0_enable - stop the async dma engines 522 * 523 * @adev: amdgpu_device pointer 524 * @enable: enable/disable the DMA MEs. 525 * 526 * Halt or unhalt the async dma engines (VEGA10). 527 */ 528 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 529 { 530 u32 f32_cntl; 531 int i; 532 533 if (enable == false) { 534 sdma_v4_0_gfx_stop(adev); 535 sdma_v4_0_rlc_stop(adev); 536 } 537 538 for (i = 0; i < adev->sdma.num_instances; i++) { 539 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 540 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 541 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 542 } 543 } 544 545 /** 546 * sdma_v4_0_gfx_resume - setup and start the async dma engines 547 * 548 * @adev: amdgpu_device pointer 549 * 550 * Set up the gfx DMA ring buffers and enable them (VEGA10). 551 * Returns 0 for success, error for failure. 552 */ 553 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) 554 { 555 struct amdgpu_ring *ring; 556 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 557 u32 rb_bufsz; 558 u32 wb_offset; 559 u32 doorbell; 560 u32 doorbell_offset; 561 u32 temp; 562 u64 wptr_gpu_addr; 563 int i, r; 564 565 for (i = 0; i < adev->sdma.num_instances; i++) { 566 ring = &adev->sdma.instance[i].ring; 567 wb_offset = (ring->rptr_offs * 4); 568 569 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 570 571 /* Set ring buffer size in dwords */ 572 rb_bufsz = order_base_2(ring->ring_size / 4); 573 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 574 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 575 #ifdef __BIG_ENDIAN 576 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 577 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 578 RPTR_WRITEBACK_SWAP_ENABLE, 1); 579 #endif 580 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 581 582 /* Initialize the ring buffer's read and write pointers */ 583 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 584 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 585 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 586 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 587 588 /* set the wb address whether it's enabled or not */ 589 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 590 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 591 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 592 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 593 594 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 595 596 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 597 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 598 599 ring->wptr = 0; 600 601 /* before programing wptr to a less value, need set minor_ptr_update first */ 602 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 603 604 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 605 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 606 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 607 } 608 609 doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 610 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 611 612 if (ring->use_doorbell) { 613 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 614 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 615 OFFSET, ring->doorbell_index); 616 } else { 617 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 618 } 619 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 620 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 621 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 622 ring->doorbell_index); 623 624 if (amdgpu_sriov_vf(adev)) 625 sdma_v4_0_ring_set_wptr(ring); 626 627 /* set minor_ptr_update to 0 after wptr programed */ 628 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 629 630 /* set utc l1 enable flag always to 1 */ 631 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 632 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 633 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 634 635 if (!amdgpu_sriov_vf(adev)) { 636 /* unhalt engine */ 637 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 638 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 639 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 640 } 641 642 /* setup the wptr shadow polling */ 643 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 644 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 645 lower_32_bits(wptr_gpu_addr)); 646 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 647 upper_32_bits(wptr_gpu_addr)); 648 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 649 if (amdgpu_sriov_vf(adev)) 650 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); 651 else 652 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0); 653 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl); 654 655 /* enable DMA RB */ 656 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 657 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 658 659 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 660 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 661 #ifdef __BIG_ENDIAN 662 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 663 #endif 664 /* enable DMA IBs */ 665 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 666 667 ring->ready = true; 668 669 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 670 sdma_v4_0_ctx_switch_enable(adev, true); 671 sdma_v4_0_enable(adev, true); 672 } 673 674 r = amdgpu_ring_test_ring(ring); 675 if (r) { 676 ring->ready = false; 677 return r; 678 } 679 680 if (adev->mman.buffer_funcs_ring == ring) 681 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 682 683 } 684 685 return 0; 686 } 687 688 static void 689 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 690 { 691 uint32_t def, data; 692 693 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 694 /* disable idle interrupt */ 695 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 696 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 697 698 if (data != def) 699 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 700 } else { 701 /* disable idle interrupt */ 702 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 703 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 704 if (data != def) 705 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 706 } 707 } 708 709 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 710 { 711 uint32_t def, data; 712 713 /* Enable HW based PG. */ 714 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 715 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 716 if (data != def) 717 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 718 719 /* enable interrupt */ 720 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 721 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 722 if (data != def) 723 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 724 725 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 726 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 727 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 728 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 729 /* Configure switch time for hysteresis purpose. Use default right now */ 730 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 731 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 732 if(data != def) 733 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 734 } 735 736 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 737 { 738 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 739 return; 740 741 switch (adev->asic_type) { 742 case CHIP_RAVEN: 743 sdma_v4_1_init_power_gating(adev); 744 sdma_v4_1_update_power_gating(adev, true); 745 break; 746 default: 747 break; 748 } 749 } 750 751 /** 752 * sdma_v4_0_rlc_resume - setup and start the async dma engines 753 * 754 * @adev: amdgpu_device pointer 755 * 756 * Set up the compute DMA queues and enable them (VEGA10). 757 * Returns 0 for success, error for failure. 758 */ 759 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 760 { 761 sdma_v4_0_init_pg(adev); 762 763 return 0; 764 } 765 766 /** 767 * sdma_v4_0_load_microcode - load the sDMA ME ucode 768 * 769 * @adev: amdgpu_device pointer 770 * 771 * Loads the sDMA0/1 ucode. 772 * Returns 0 for success, -EINVAL if the ucode is not available. 773 */ 774 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 775 { 776 const struct sdma_firmware_header_v1_0 *hdr; 777 const __le32 *fw_data; 778 u32 fw_size; 779 int i, j; 780 781 /* halt the MEs */ 782 sdma_v4_0_enable(adev, false); 783 784 for (i = 0; i < adev->sdma.num_instances; i++) { 785 if (!adev->sdma.instance[i].fw) 786 return -EINVAL; 787 788 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 789 amdgpu_ucode_print_sdma_hdr(&hdr->header); 790 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 791 792 fw_data = (const __le32 *) 793 (adev->sdma.instance[i].fw->data + 794 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 795 796 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 797 798 for (j = 0; j < fw_size; j++) 799 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 800 801 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 802 } 803 804 return 0; 805 } 806 807 /** 808 * sdma_v4_0_start - setup and start the async dma engines 809 * 810 * @adev: amdgpu_device pointer 811 * 812 * Set up the DMA engines and enable them (VEGA10). 813 * Returns 0 for success, error for failure. 814 */ 815 static int sdma_v4_0_start(struct amdgpu_device *adev) 816 { 817 int r = 0; 818 819 if (amdgpu_sriov_vf(adev)) { 820 sdma_v4_0_ctx_switch_enable(adev, false); 821 sdma_v4_0_enable(adev, false); 822 823 /* set RB registers */ 824 r = sdma_v4_0_gfx_resume(adev); 825 return r; 826 } 827 828 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 829 r = sdma_v4_0_load_microcode(adev); 830 if (r) 831 return r; 832 } 833 834 /* unhalt the MEs */ 835 sdma_v4_0_enable(adev, true); 836 /* enable sdma ring preemption */ 837 sdma_v4_0_ctx_switch_enable(adev, true); 838 839 /* start the gfx rings and rlc compute queues */ 840 r = sdma_v4_0_gfx_resume(adev); 841 if (r) 842 return r; 843 r = sdma_v4_0_rlc_resume(adev); 844 845 return r; 846 } 847 848 /** 849 * sdma_v4_0_ring_test_ring - simple async dma engine test 850 * 851 * @ring: amdgpu_ring structure holding ring information 852 * 853 * Test the DMA engine by writing using it to write an 854 * value to memory. (VEGA10). 855 * Returns 0 for success, error for failure. 856 */ 857 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 858 { 859 struct amdgpu_device *adev = ring->adev; 860 unsigned i; 861 unsigned index; 862 int r; 863 u32 tmp; 864 u64 gpu_addr; 865 866 r = amdgpu_device_wb_get(adev, &index); 867 if (r) { 868 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 869 return r; 870 } 871 872 gpu_addr = adev->wb.gpu_addr + (index * 4); 873 tmp = 0xCAFEDEAD; 874 adev->wb.wb[index] = cpu_to_le32(tmp); 875 876 r = amdgpu_ring_alloc(ring, 5); 877 if (r) { 878 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 879 amdgpu_device_wb_free(adev, index); 880 return r; 881 } 882 883 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 884 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 885 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 886 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 887 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 888 amdgpu_ring_write(ring, 0xDEADBEEF); 889 amdgpu_ring_commit(ring); 890 891 for (i = 0; i < adev->usec_timeout; i++) { 892 tmp = le32_to_cpu(adev->wb.wb[index]); 893 if (tmp == 0xDEADBEEF) 894 break; 895 DRM_UDELAY(1); 896 } 897 898 if (i < adev->usec_timeout) { 899 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 900 } else { 901 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 902 ring->idx, tmp); 903 r = -EINVAL; 904 } 905 amdgpu_device_wb_free(adev, index); 906 907 return r; 908 } 909 910 /** 911 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 912 * 913 * @ring: amdgpu_ring structure holding ring information 914 * 915 * Test a simple IB in the DMA ring (VEGA10). 916 * Returns 0 on success, error on failure. 917 */ 918 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 919 { 920 struct amdgpu_device *adev = ring->adev; 921 struct amdgpu_ib ib; 922 struct dma_fence *f = NULL; 923 unsigned index; 924 long r; 925 u32 tmp = 0; 926 u64 gpu_addr; 927 928 r = amdgpu_device_wb_get(adev, &index); 929 if (r) { 930 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 931 return r; 932 } 933 934 gpu_addr = adev->wb.gpu_addr + (index * 4); 935 tmp = 0xCAFEDEAD; 936 adev->wb.wb[index] = cpu_to_le32(tmp); 937 memset(&ib, 0, sizeof(ib)); 938 r = amdgpu_ib_get(adev, NULL, 256, &ib); 939 if (r) { 940 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 941 goto err0; 942 } 943 944 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 945 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 946 ib.ptr[1] = lower_32_bits(gpu_addr); 947 ib.ptr[2] = upper_32_bits(gpu_addr); 948 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 949 ib.ptr[4] = 0xDEADBEEF; 950 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 951 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 952 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 953 ib.length_dw = 8; 954 955 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 956 if (r) 957 goto err1; 958 959 r = dma_fence_wait_timeout(f, false, timeout); 960 if (r == 0) { 961 DRM_ERROR("amdgpu: IB test timed out\n"); 962 r = -ETIMEDOUT; 963 goto err1; 964 } else if (r < 0) { 965 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 966 goto err1; 967 } 968 tmp = le32_to_cpu(adev->wb.wb[index]); 969 if (tmp == 0xDEADBEEF) { 970 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 971 r = 0; 972 } else { 973 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 974 r = -EINVAL; 975 } 976 err1: 977 amdgpu_ib_free(adev, &ib, NULL); 978 dma_fence_put(f); 979 err0: 980 amdgpu_device_wb_free(adev, index); 981 return r; 982 } 983 984 985 /** 986 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 987 * 988 * @ib: indirect buffer to fill with commands 989 * @pe: addr of the page entry 990 * @src: src addr to copy from 991 * @count: number of page entries to update 992 * 993 * Update PTEs by copying them from the GART using sDMA (VEGA10). 994 */ 995 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 996 uint64_t pe, uint64_t src, 997 unsigned count) 998 { 999 unsigned bytes = count * 8; 1000 1001 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1002 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1003 ib->ptr[ib->length_dw++] = bytes - 1; 1004 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1005 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1006 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1007 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1008 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1009 1010 } 1011 1012 /** 1013 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1014 * 1015 * @ib: indirect buffer to fill with commands 1016 * @pe: addr of the page entry 1017 * @addr: dst addr to write into pe 1018 * @count: number of page entries to update 1019 * @incr: increase next addr by incr bytes 1020 * @flags: access flags 1021 * 1022 * Update PTEs by writing them manually using sDMA (VEGA10). 1023 */ 1024 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1025 uint64_t value, unsigned count, 1026 uint32_t incr) 1027 { 1028 unsigned ndw = count * 2; 1029 1030 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1031 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1032 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1033 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1034 ib->ptr[ib->length_dw++] = ndw - 1; 1035 for (; ndw > 0; ndw -= 2) { 1036 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1037 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1038 value += incr; 1039 } 1040 } 1041 1042 /** 1043 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1044 * 1045 * @ib: indirect buffer to fill with commands 1046 * @pe: addr of the page entry 1047 * @addr: dst addr to write into pe 1048 * @count: number of page entries to update 1049 * @incr: increase next addr by incr bytes 1050 * @flags: access flags 1051 * 1052 * Update the page tables using sDMA (VEGA10). 1053 */ 1054 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1055 uint64_t pe, 1056 uint64_t addr, unsigned count, 1057 uint32_t incr, uint64_t flags) 1058 { 1059 /* for physically contiguous pages (vram) */ 1060 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1061 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1062 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1063 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1064 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1065 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1066 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1067 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1068 ib->ptr[ib->length_dw++] = 0; 1069 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1070 } 1071 1072 /** 1073 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1074 * 1075 * @ib: indirect buffer to fill with padding 1076 * 1077 */ 1078 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1079 { 1080 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1081 u32 pad_count; 1082 int i; 1083 1084 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1085 for (i = 0; i < pad_count; i++) 1086 if (sdma && sdma->burst_nop && (i == 0)) 1087 ib->ptr[ib->length_dw++] = 1088 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1089 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1090 else 1091 ib->ptr[ib->length_dw++] = 1092 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1093 } 1094 1095 1096 /** 1097 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1098 * 1099 * @ring: amdgpu_ring pointer 1100 * 1101 * Make sure all previous operations are completed (CIK). 1102 */ 1103 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1104 { 1105 uint32_t seq = ring->fence_drv.sync_seq; 1106 uint64_t addr = ring->fence_drv.gpu_addr; 1107 1108 /* wait for idle */ 1109 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1110 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1111 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1112 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1113 amdgpu_ring_write(ring, addr & 0xfffffffc); 1114 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1115 amdgpu_ring_write(ring, seq); /* reference */ 1116 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 1117 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1118 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1119 } 1120 1121 1122 /** 1123 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1124 * 1125 * @ring: amdgpu_ring pointer 1126 * @vm: amdgpu_vm pointer 1127 * 1128 * Update the page table base and flush the VM TLB 1129 * using sDMA (VEGA10). 1130 */ 1131 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1132 unsigned vmid, uint64_t pd_addr) 1133 { 1134 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1135 uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid); 1136 uint64_t flags = AMDGPU_PTE_VALID; 1137 unsigned eng = ring->vm_inv_eng; 1138 1139 amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); 1140 pd_addr |= flags; 1141 1142 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1143 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1144 amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2); 1145 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 1146 1147 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1148 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1149 amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vmid * 2); 1150 amdgpu_ring_write(ring, upper_32_bits(pd_addr)); 1151 1152 /* flush TLB */ 1153 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1154 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1155 amdgpu_ring_write(ring, hub->vm_inv_eng0_req + eng); 1156 amdgpu_ring_write(ring, req); 1157 1158 /* wait for flush */ 1159 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1160 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1161 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1162 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); 1163 amdgpu_ring_write(ring, 0); 1164 amdgpu_ring_write(ring, 1 << vmid); /* reference */ 1165 amdgpu_ring_write(ring, 1 << vmid); /* mask */ 1166 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1167 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1168 } 1169 1170 static int sdma_v4_0_early_init(void *handle) 1171 { 1172 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1173 1174 if (adev->asic_type == CHIP_RAVEN) 1175 adev->sdma.num_instances = 1; 1176 else 1177 adev->sdma.num_instances = 2; 1178 1179 sdma_v4_0_set_ring_funcs(adev); 1180 sdma_v4_0_set_buffer_funcs(adev); 1181 sdma_v4_0_set_vm_pte_funcs(adev); 1182 sdma_v4_0_set_irq_funcs(adev); 1183 1184 return 0; 1185 } 1186 1187 1188 static int sdma_v4_0_sw_init(void *handle) 1189 { 1190 struct amdgpu_ring *ring; 1191 int r, i; 1192 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1193 1194 /* SDMA trap event */ 1195 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224, 1196 &adev->sdma.trap_irq); 1197 if (r) 1198 return r; 1199 1200 /* SDMA trap event */ 1201 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224, 1202 &adev->sdma.trap_irq); 1203 if (r) 1204 return r; 1205 1206 r = sdma_v4_0_init_microcode(adev); 1207 if (r) { 1208 DRM_ERROR("Failed to load sdma firmware!\n"); 1209 return r; 1210 } 1211 1212 for (i = 0; i < adev->sdma.num_instances; i++) { 1213 ring = &adev->sdma.instance[i].ring; 1214 ring->ring_obj = NULL; 1215 ring->use_doorbell = true; 1216 1217 DRM_INFO("use_doorbell being set to: [%s]\n", 1218 ring->use_doorbell?"true":"false"); 1219 1220 ring->doorbell_index = (i == 0) ? 1221 (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset 1222 : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset 1223 1224 sprintf(ring->name, "sdma%d", i); 1225 r = amdgpu_ring_init(adev, ring, 1024, 1226 &adev->sdma.trap_irq, 1227 (i == 0) ? 1228 AMDGPU_SDMA_IRQ_TRAP0 : 1229 AMDGPU_SDMA_IRQ_TRAP1); 1230 if (r) 1231 return r; 1232 } 1233 1234 return r; 1235 } 1236 1237 static int sdma_v4_0_sw_fini(void *handle) 1238 { 1239 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1240 int i; 1241 1242 for (i = 0; i < adev->sdma.num_instances; i++) 1243 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1244 1245 for (i = 0; i < adev->sdma.num_instances; i++) { 1246 release_firmware(adev->sdma.instance[i].fw); 1247 adev->sdma.instance[i].fw = NULL; 1248 } 1249 1250 return 0; 1251 } 1252 1253 static int sdma_v4_0_hw_init(void *handle) 1254 { 1255 int r; 1256 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1257 1258 sdma_v4_0_init_golden_registers(adev); 1259 1260 r = sdma_v4_0_start(adev); 1261 1262 return r; 1263 } 1264 1265 static int sdma_v4_0_hw_fini(void *handle) 1266 { 1267 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1268 1269 if (amdgpu_sriov_vf(adev)) 1270 return 0; 1271 1272 sdma_v4_0_ctx_switch_enable(adev, false); 1273 sdma_v4_0_enable(adev, false); 1274 1275 return 0; 1276 } 1277 1278 static int sdma_v4_0_suspend(void *handle) 1279 { 1280 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1281 1282 return sdma_v4_0_hw_fini(adev); 1283 } 1284 1285 static int sdma_v4_0_resume(void *handle) 1286 { 1287 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1288 1289 return sdma_v4_0_hw_init(adev); 1290 } 1291 1292 static bool sdma_v4_0_is_idle(void *handle) 1293 { 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1295 u32 i; 1296 1297 for (i = 0; i < adev->sdma.num_instances; i++) { 1298 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1299 1300 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1301 return false; 1302 } 1303 1304 return true; 1305 } 1306 1307 static int sdma_v4_0_wait_for_idle(void *handle) 1308 { 1309 unsigned i; 1310 u32 sdma0, sdma1; 1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1312 1313 for (i = 0; i < adev->usec_timeout; i++) { 1314 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1315 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1316 1317 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1318 return 0; 1319 udelay(1); 1320 } 1321 return -ETIMEDOUT; 1322 } 1323 1324 static int sdma_v4_0_soft_reset(void *handle) 1325 { 1326 /* todo */ 1327 1328 return 0; 1329 } 1330 1331 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1332 struct amdgpu_irq_src *source, 1333 unsigned type, 1334 enum amdgpu_interrupt_state state) 1335 { 1336 u32 sdma_cntl; 1337 1338 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 1339 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1340 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1341 1342 sdma_cntl = RREG32(reg_offset); 1343 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1344 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1345 WREG32(reg_offset, sdma_cntl); 1346 1347 return 0; 1348 } 1349 1350 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1351 struct amdgpu_irq_src *source, 1352 struct amdgpu_iv_entry *entry) 1353 { 1354 DRM_DEBUG("IH: SDMA trap\n"); 1355 switch (entry->client_id) { 1356 case AMDGPU_IH_CLIENTID_SDMA0: 1357 switch (entry->ring_id) { 1358 case 0: 1359 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1360 break; 1361 case 1: 1362 /* XXX compute */ 1363 break; 1364 case 2: 1365 /* XXX compute */ 1366 break; 1367 case 3: 1368 /* XXX page queue*/ 1369 break; 1370 } 1371 break; 1372 case AMDGPU_IH_CLIENTID_SDMA1: 1373 switch (entry->ring_id) { 1374 case 0: 1375 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1376 break; 1377 case 1: 1378 /* XXX compute */ 1379 break; 1380 case 2: 1381 /* XXX compute */ 1382 break; 1383 case 3: 1384 /* XXX page queue*/ 1385 break; 1386 } 1387 break; 1388 } 1389 return 0; 1390 } 1391 1392 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1393 struct amdgpu_irq_src *source, 1394 struct amdgpu_iv_entry *entry) 1395 { 1396 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1397 schedule_work(&adev->reset_work); 1398 return 0; 1399 } 1400 1401 1402 static void sdma_v4_0_update_medium_grain_clock_gating( 1403 struct amdgpu_device *adev, 1404 bool enable) 1405 { 1406 uint32_t data, def; 1407 1408 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1409 /* enable sdma0 clock gating */ 1410 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1411 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1412 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1413 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1414 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1415 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1416 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1417 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1418 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1419 if (def != data) 1420 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1421 1422 if (adev->asic_type == CHIP_VEGA10) { 1423 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1424 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1425 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1426 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1427 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1428 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1429 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1430 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1431 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1432 if (def != data) 1433 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1434 } 1435 } else { 1436 /* disable sdma0 clock gating */ 1437 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1438 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1439 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1440 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1441 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1442 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1443 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1444 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1445 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1446 1447 if (def != data) 1448 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1449 1450 if (adev->asic_type == CHIP_VEGA10) { 1451 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1452 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1453 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1454 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1455 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1456 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1457 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1458 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1459 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1460 if (def != data) 1461 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1462 } 1463 } 1464 } 1465 1466 1467 static void sdma_v4_0_update_medium_grain_light_sleep( 1468 struct amdgpu_device *adev, 1469 bool enable) 1470 { 1471 uint32_t data, def; 1472 1473 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1474 /* 1-not override: enable sdma0 mem light sleep */ 1475 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1476 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1477 if (def != data) 1478 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1479 1480 /* 1-not override: enable sdma1 mem light sleep */ 1481 if (adev->asic_type == CHIP_VEGA10) { 1482 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1483 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1484 if (def != data) 1485 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1486 } 1487 } else { 1488 /* 0-override:disable sdma0 mem light sleep */ 1489 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1490 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1491 if (def != data) 1492 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1493 1494 /* 0-override:disable sdma1 mem light sleep */ 1495 if (adev->asic_type == CHIP_VEGA10) { 1496 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1497 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1498 if (def != data) 1499 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1500 } 1501 } 1502 } 1503 1504 static int sdma_v4_0_set_clockgating_state(void *handle, 1505 enum amd_clockgating_state state) 1506 { 1507 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1508 1509 if (amdgpu_sriov_vf(adev)) 1510 return 0; 1511 1512 switch (adev->asic_type) { 1513 case CHIP_VEGA10: 1514 case CHIP_RAVEN: 1515 sdma_v4_0_update_medium_grain_clock_gating(adev, 1516 state == AMD_CG_STATE_GATE ? true : false); 1517 sdma_v4_0_update_medium_grain_light_sleep(adev, 1518 state == AMD_CG_STATE_GATE ? true : false); 1519 break; 1520 default: 1521 break; 1522 } 1523 return 0; 1524 } 1525 1526 static int sdma_v4_0_set_powergating_state(void *handle, 1527 enum amd_powergating_state state) 1528 { 1529 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1530 1531 switch (adev->asic_type) { 1532 case CHIP_RAVEN: 1533 sdma_v4_1_update_power_gating(adev, 1534 state == AMD_PG_STATE_GATE ? true : false); 1535 break; 1536 default: 1537 break; 1538 } 1539 1540 return 0; 1541 } 1542 1543 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 1544 { 1545 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1546 int data; 1547 1548 if (amdgpu_sriov_vf(adev)) 1549 *flags = 0; 1550 1551 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1552 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1553 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1554 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1555 1556 /* AMD_CG_SUPPORT_SDMA_LS */ 1557 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1558 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1559 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1560 } 1561 1562 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 1563 .name = "sdma_v4_0", 1564 .early_init = sdma_v4_0_early_init, 1565 .late_init = NULL, 1566 .sw_init = sdma_v4_0_sw_init, 1567 .sw_fini = sdma_v4_0_sw_fini, 1568 .hw_init = sdma_v4_0_hw_init, 1569 .hw_fini = sdma_v4_0_hw_fini, 1570 .suspend = sdma_v4_0_suspend, 1571 .resume = sdma_v4_0_resume, 1572 .is_idle = sdma_v4_0_is_idle, 1573 .wait_for_idle = sdma_v4_0_wait_for_idle, 1574 .soft_reset = sdma_v4_0_soft_reset, 1575 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 1576 .set_powergating_state = sdma_v4_0_set_powergating_state, 1577 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 1578 }; 1579 1580 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 1581 .type = AMDGPU_RING_TYPE_SDMA, 1582 .align_mask = 0xf, 1583 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1584 .support_64bit_ptrs = true, 1585 .vmhub = AMDGPU_MMHUB, 1586 .get_rptr = sdma_v4_0_ring_get_rptr, 1587 .get_wptr = sdma_v4_0_ring_get_wptr, 1588 .set_wptr = sdma_v4_0_ring_set_wptr, 1589 .emit_frame_size = 1590 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1591 3 + /* sdma_v4_0_ring_emit_hdp_invalidate */ 1592 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1593 18 + /* sdma_v4_0_ring_emit_vm_flush */ 1594 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1595 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1596 .emit_ib = sdma_v4_0_ring_emit_ib, 1597 .emit_fence = sdma_v4_0_ring_emit_fence, 1598 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1599 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1600 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1601 .emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate, 1602 .test_ring = sdma_v4_0_ring_test_ring, 1603 .test_ib = sdma_v4_0_ring_test_ib, 1604 .insert_nop = sdma_v4_0_ring_insert_nop, 1605 .pad_ib = sdma_v4_0_ring_pad_ib, 1606 }; 1607 1608 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 1609 { 1610 int i; 1611 1612 for (i = 0; i < adev->sdma.num_instances; i++) 1613 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 1614 } 1615 1616 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 1617 .set = sdma_v4_0_set_trap_irq_state, 1618 .process = sdma_v4_0_process_trap_irq, 1619 }; 1620 1621 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 1622 .process = sdma_v4_0_process_illegal_inst_irq, 1623 }; 1624 1625 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 1626 { 1627 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1628 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 1629 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 1630 } 1631 1632 /** 1633 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 1634 * 1635 * @ring: amdgpu_ring structure holding ring information 1636 * @src_offset: src GPU address 1637 * @dst_offset: dst GPU address 1638 * @byte_count: number of bytes to xfer 1639 * 1640 * Copy GPU buffers using the DMA engine (VEGA10). 1641 * Used by the amdgpu ttm implementation to move pages if 1642 * registered as the asic copy callback. 1643 */ 1644 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 1645 uint64_t src_offset, 1646 uint64_t dst_offset, 1647 uint32_t byte_count) 1648 { 1649 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1650 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1651 ib->ptr[ib->length_dw++] = byte_count - 1; 1652 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1653 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1654 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1655 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1656 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1657 } 1658 1659 /** 1660 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 1661 * 1662 * @ring: amdgpu_ring structure holding ring information 1663 * @src_data: value to write to buffer 1664 * @dst_offset: dst GPU address 1665 * @byte_count: number of bytes to xfer 1666 * 1667 * Fill GPU buffers using the DMA engine (VEGA10). 1668 */ 1669 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 1670 uint32_t src_data, 1671 uint64_t dst_offset, 1672 uint32_t byte_count) 1673 { 1674 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1675 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1676 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1677 ib->ptr[ib->length_dw++] = src_data; 1678 ib->ptr[ib->length_dw++] = byte_count - 1; 1679 } 1680 1681 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 1682 .copy_max_bytes = 0x400000, 1683 .copy_num_dw = 7, 1684 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 1685 1686 .fill_max_bytes = 0x400000, 1687 .fill_num_dw = 5, 1688 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 1689 }; 1690 1691 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 1692 { 1693 if (adev->mman.buffer_funcs == NULL) { 1694 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 1695 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1696 } 1697 } 1698 1699 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 1700 .copy_pte_num_dw = 7, 1701 .copy_pte = sdma_v4_0_vm_copy_pte, 1702 1703 .write_pte = sdma_v4_0_vm_write_pte, 1704 1705 .set_max_nums_pte_pde = 0x400000 >> 3, 1706 .set_pte_pde_num_dw = 10, 1707 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 1708 }; 1709 1710 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1711 { 1712 unsigned i; 1713 1714 if (adev->vm_manager.vm_pte_funcs == NULL) { 1715 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 1716 for (i = 0; i < adev->sdma.num_instances; i++) 1717 adev->vm_manager.vm_pte_rings[i] = 1718 &adev->sdma.instance[i].ring; 1719 1720 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1721 } 1722 } 1723 1724 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 1725 .type = AMD_IP_BLOCK_TYPE_SDMA, 1726 .major = 4, 1727 .minor = 0, 1728 .rev = 0, 1729 .funcs = &sdma_v4_0_ip_funcs, 1730 }; 1731