1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "vega10/soc15ip.h" 31 #include "vega10/SDMA0/sdma0_4_0_offset.h" 32 #include "vega10/SDMA0/sdma0_4_0_sh_mask.h" 33 #include "vega10/SDMA1/sdma1_4_0_offset.h" 34 #include "vega10/SDMA1/sdma1_4_0_sh_mask.h" 35 #include "vega10/MMHUB/mmhub_1_0_offset.h" 36 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h" 37 #include "vega10/HDP/hdp_4_0_offset.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "vega10_sdma_pkt_open.h" 42 43 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 44 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 45 46 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 47 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 48 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 49 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 50 51 static const u32 golden_settings_sdma_4[] = 52 { 53 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07, 54 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100, 55 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100, 56 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 0xfffffff7, 0x00403000, 57 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL), 0x800f0100, 0x00000100, 58 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 59 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), 0x003ff006, 0x0003c000, 60 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL), 0x800f0100, 0x00000100, 61 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 62 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL), 0x800f0100, 0x00000100, 63 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 64 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UTCL1_PAGE), 0x000003ff, 0x000003c0, 65 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CHICKEN_BITS), 0xfe931f07, 0x02831f07, 66 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), 0xffffffff, 0x3f000100, 67 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_IB_CNTL), 0x800f0100, 0x00000100, 68 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 69 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL), 0x800f0100, 0x00000100, 70 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 71 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), 0x003ff000, 0x0003c000, 72 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL), 0x800f0100, 0x00000100, 73 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 74 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL), 0x800f0100, 0x00000100, 75 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL), 0x0000fff0, 0x00403000, 76 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0 77 }; 78 79 static const u32 golden_settings_sdma_vg10[] = 80 { 81 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002, 82 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002, 83 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002, 84 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002 85 }; 86 87 static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset) 88 { 89 u32 base = 0; 90 switch (instance) { 91 case 0: 92 base = SDMA0_BASE.instance[0].segment[0]; 93 break; 94 case 1: 95 base = SDMA1_BASE.instance[0].segment[0]; 96 break; 97 default: 98 BUG(); 99 break; 100 } 101 102 return base + internal_offset; 103 } 104 105 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 106 { 107 switch (adev->asic_type) { 108 case CHIP_VEGA10: 109 amdgpu_program_register_sequence(adev, 110 golden_settings_sdma_4, 111 (const u32)ARRAY_SIZE(golden_settings_sdma_4)); 112 amdgpu_program_register_sequence(adev, 113 golden_settings_sdma_vg10, 114 (const u32)ARRAY_SIZE(golden_settings_sdma_vg10)); 115 break; 116 default: 117 break; 118 } 119 } 120 121 static void sdma_v4_0_print_ucode_regs(void *handle) 122 { 123 int i; 124 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 125 126 dev_info(adev->dev, "VEGA10 SDMA ucode registers\n"); 127 for (i = 0; i < adev->sdma.num_instances; i++) { 128 dev_info(adev->dev, " SDMA%d_UCODE_ADDR=0x%08X\n", 129 i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR))); 130 dev_info(adev->dev, " SDMA%d_UCODE_CHECKSUM=0x%08X\n", 131 i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_CHECKSUM))); 132 } 133 } 134 135 /** 136 * sdma_v4_0_init_microcode - load ucode images from disk 137 * 138 * @adev: amdgpu_device pointer 139 * 140 * Use the firmware interface to load the ucode images into 141 * the driver (not loaded into hw). 142 * Returns 0 on success, error on failure. 143 */ 144 145 // emulation only, won't work on real chip 146 // vega10 real chip need to use PSP to load firmware 147 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 148 { 149 const char *chip_name; 150 char fw_name[30]; 151 int err = 0, i; 152 struct amdgpu_firmware_info *info = NULL; 153 const struct common_firmware_header *header = NULL; 154 const struct sdma_firmware_header_v1_0 *hdr; 155 156 DRM_DEBUG("\n"); 157 158 switch (adev->asic_type) { 159 case CHIP_VEGA10: 160 chip_name = "vega10"; 161 break; 162 default: BUG(); 163 } 164 165 for (i = 0; i < adev->sdma.num_instances; i++) { 166 if (i == 0) 167 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 168 else 169 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 170 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 171 if (err) 172 goto out; 173 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 174 if (err) 175 goto out; 176 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 177 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 178 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 179 if (adev->sdma.instance[i].feature_version >= 20) 180 adev->sdma.instance[i].burst_nop = true; 181 DRM_DEBUG("psp_load == '%s'\n", 182 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP? "true": "false"); 183 184 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 185 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 186 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 187 info->fw = adev->sdma.instance[i].fw; 188 header = (const struct common_firmware_header *)info->fw->data; 189 adev->firmware.fw_size += 190 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 191 } 192 } 193 out: 194 if (err) { 195 printk(KERN_ERR 196 "sdma_v4_0: Failed to load firmware \"%s\"\n", 197 fw_name); 198 for (i = 0; i < adev->sdma.num_instances; i++) { 199 release_firmware(adev->sdma.instance[i].fw); 200 adev->sdma.instance[i].fw = NULL; 201 } 202 } 203 return err; 204 } 205 206 /** 207 * sdma_v4_0_ring_get_rptr - get the current read pointer 208 * 209 * @ring: amdgpu ring pointer 210 * 211 * Get the current rptr from the hardware (VEGA10+). 212 */ 213 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 214 { 215 u64* rptr; 216 217 /* XXX check if swapping is necessary on BE */ 218 rptr =((u64*)&ring->adev->wb.wb[ring->rptr_offs]); 219 220 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 221 return ((*rptr) >> 2); 222 } 223 224 /** 225 * sdma_v4_0_ring_get_wptr - get the current write pointer 226 * 227 * @ring: amdgpu ring pointer 228 * 229 * Get the current wptr from the hardware (VEGA10+). 230 */ 231 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 232 { 233 struct amdgpu_device *adev = ring->adev; 234 u64* wptr = NULL; 235 uint64_t local_wptr=0; 236 237 if (ring->use_doorbell) { 238 /* XXX check if swapping is necessary on BE */ 239 wptr = ((u64*)&adev->wb.wb[ring->wptr_offs]); 240 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); 241 *wptr = (*wptr) >> 2; 242 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); 243 } else { 244 u32 lowbit, highbit; 245 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 246 wptr=&local_wptr; 247 lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) >> 2; 248 highbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 249 250 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 251 me, highbit, lowbit); 252 *wptr = highbit; 253 *wptr = (*wptr) << 32; 254 *wptr |= lowbit; 255 } 256 257 return *wptr; 258 } 259 260 /** 261 * sdma_v4_0_ring_set_wptr - commit the write pointer 262 * 263 * @ring: amdgpu ring pointer 264 * 265 * Write the wptr back to the hardware (VEGA10+). 266 */ 267 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 268 { 269 struct amdgpu_device *adev = ring->adev; 270 271 DRM_DEBUG("Setting write pointer\n"); 272 if (ring->use_doorbell) { 273 DRM_DEBUG("Using doorbell -- " 274 "wptr_offs == 0x%08x " 275 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 276 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 277 ring->wptr_offs, 278 lower_32_bits(ring->wptr << 2), 279 upper_32_bits(ring->wptr << 2)); 280 /* XXX check if swapping is necessary on BE */ 281 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 282 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 283 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 284 ring->doorbell_index, ring->wptr << 2); 285 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 286 } else { 287 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 288 DRM_DEBUG("Not using doorbell -- " 289 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 290 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x \n", 291 me, 292 me, 293 lower_32_bits(ring->wptr << 2), 294 upper_32_bits(ring->wptr << 2)); 295 WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 296 WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 297 } 298 } 299 300 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 301 { 302 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 303 int i; 304 305 for (i = 0; i < count; i++) 306 if (sdma && sdma->burst_nop && (i == 0)) 307 amdgpu_ring_write(ring, ring->funcs->nop | 308 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 309 else 310 amdgpu_ring_write(ring, ring->funcs->nop); 311 } 312 313 /** 314 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 315 * 316 * @ring: amdgpu ring pointer 317 * @ib: IB object to schedule 318 * 319 * Schedule an IB in the DMA ring (VEGA10). 320 */ 321 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 322 struct amdgpu_ib *ib, 323 unsigned vm_id, bool ctx_switch) 324 { 325 u32 vmid = vm_id & 0xf; 326 327 /* IB packet must end on a 8 DW boundary */ 328 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 329 330 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 331 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 332 /* base must be 32 byte aligned */ 333 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 334 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 335 amdgpu_ring_write(ring, ib->length_dw); 336 amdgpu_ring_write(ring, 0); 337 amdgpu_ring_write(ring, 0); 338 339 } 340 341 /** 342 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 343 * 344 * @ring: amdgpu ring pointer 345 * 346 * Emit an hdp flush packet on the requested DMA ring. 347 */ 348 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 349 { 350 u32 ref_and_mask = 0; 351 struct nbio_hdp_flush_reg *nbio_hf_reg; 352 353 if (ring->adev->asic_type == CHIP_VEGA10) 354 nbio_hf_reg = &nbio_v6_1_hdp_flush_reg; 355 356 if (ring == &ring->adev->sdma.instance[0].ring) 357 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 358 else 359 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 360 361 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 362 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 363 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 364 amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_done_offset << 2); 365 amdgpu_ring_write(ring, nbio_hf_reg->hdp_flush_req_offset << 2); 366 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 367 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 368 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 369 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 370 } 371 372 static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 373 { 374 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 375 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 376 amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0)); 377 amdgpu_ring_write(ring, 1); 378 } 379 380 /** 381 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 382 * 383 * @ring: amdgpu ring pointer 384 * @fence: amdgpu fence object 385 * 386 * Add a DMA fence packet to the ring to write 387 * the fence seq number and DMA trap packet to generate 388 * an interrupt if needed (VEGA10). 389 */ 390 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 391 unsigned flags) 392 { 393 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 394 /* write the fence */ 395 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 396 /* zero in first two bits */ 397 BUG_ON(addr & 0x3); 398 amdgpu_ring_write(ring, lower_32_bits(addr)); 399 amdgpu_ring_write(ring, upper_32_bits(addr)); 400 amdgpu_ring_write(ring, lower_32_bits(seq)); 401 402 /* optionally write high bits as well */ 403 if (write64bit) { 404 addr += 4; 405 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 406 /* zero in first two bits */ 407 BUG_ON(addr & 0x3); 408 amdgpu_ring_write(ring, lower_32_bits(addr)); 409 amdgpu_ring_write(ring, upper_32_bits(addr)); 410 amdgpu_ring_write(ring, upper_32_bits(seq)); 411 } 412 413 /* generate an interrupt */ 414 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 415 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 416 } 417 418 419 /** 420 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 421 * 422 * @adev: amdgpu_device pointer 423 * 424 * Stop the gfx async dma ring buffers (VEGA10). 425 */ 426 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 427 { 428 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 429 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 430 u32 rb_cntl, ib_cntl; 431 int i; 432 433 if ((adev->mman.buffer_funcs_ring == sdma0) || 434 (adev->mman.buffer_funcs_ring == sdma1)) 435 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 436 437 for (i = 0; i < adev->sdma.num_instances; i++) { 438 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL)); 439 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 440 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 441 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL)); 442 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 443 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 444 } 445 446 sdma0->ready = false; 447 sdma1->ready = false; 448 } 449 450 /** 451 * sdma_v4_0_rlc_stop - stop the compute async dma engines 452 * 453 * @adev: amdgpu_device pointer 454 * 455 * Stop the compute async dma queues (VEGA10). 456 */ 457 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 458 { 459 /* XXX todo */ 460 } 461 462 /** 463 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 464 * 465 * @adev: amdgpu_device pointer 466 * @enable: enable/disable the DMA MEs context switch. 467 * 468 * Halt or unhalt the async dma engines context switch (VEGA10). 469 */ 470 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 471 { 472 u32 f32_cntl; 473 int i; 474 475 for (i = 0; i < adev->sdma.num_instances; i++) { 476 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL)); 477 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 478 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 479 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), f32_cntl); 480 } 481 482 } 483 484 /** 485 * sdma_v4_0_enable - stop the async dma engines 486 * 487 * @adev: amdgpu_device pointer 488 * @enable: enable/disable the DMA MEs. 489 * 490 * Halt or unhalt the async dma engines (VEGA10). 491 */ 492 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 493 { 494 u32 f32_cntl; 495 int i; 496 497 if (enable == false) { 498 sdma_v4_0_gfx_stop(adev); 499 sdma_v4_0_rlc_stop(adev); 500 } 501 502 for (i = 0; i < adev->sdma.num_instances; i++) { 503 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL)); 504 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 505 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), f32_cntl); 506 } 507 } 508 509 /** 510 * sdma_v4_0_gfx_resume - setup and start the async dma engines 511 * 512 * @adev: amdgpu_device pointer 513 * 514 * Set up the gfx DMA ring buffers and enable them (VEGA10). 515 * Returns 0 for success, error for failure. 516 */ 517 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) 518 { 519 struct amdgpu_ring *ring; 520 u32 rb_cntl, ib_cntl; 521 u32 rb_bufsz; 522 u32 wb_offset; 523 u32 doorbell; 524 u32 doorbell_offset; 525 u32 temp; 526 int i,r; 527 528 for (i = 0; i < adev->sdma.num_instances; i++) { 529 ring = &adev->sdma.instance[i].ring; 530 wb_offset = (ring->rptr_offs * 4); 531 532 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 533 534 /* Set ring buffer size in dwords */ 535 rb_bufsz = order_base_2(ring->ring_size / 4); 536 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL)); 537 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 538 #ifdef __BIG_ENDIAN 539 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 540 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 541 RPTR_WRITEBACK_SWAP_ENABLE, 1); 542 #endif 543 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 544 545 /* Initialize the ring buffer's read and write pointers */ 546 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR), 0); 547 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_HI), 0); 548 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), 0); 549 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), 0); 550 551 /* set the wb address whether it's enabled or not */ 552 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 553 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 554 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 555 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 556 557 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 558 559 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 560 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 561 562 ring->wptr = 0; 563 564 /* before programing wptr to a less value, need set minor_ptr_update first */ 565 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 566 567 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 568 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 569 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 570 } 571 572 doorbell = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL)); 573 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET)); 574 575 if (ring->use_doorbell){ 576 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 577 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 578 OFFSET, ring->doorbell_index); 579 } else { 580 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 581 } 582 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL), doorbell); 583 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 584 nbio_v6_1_sdma_doorbell_range(adev, i, ring->use_doorbell, ring->doorbell_index); 585 586 if (amdgpu_sriov_vf(adev)) 587 sdma_v4_0_ring_set_wptr(ring); 588 589 /* set minor_ptr_update to 0 after wptr programed */ 590 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 591 592 /* set utc l1 enable flag always to 1 */ 593 temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL)); 594 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 595 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL), temp); 596 597 if (!amdgpu_sriov_vf(adev)) { 598 /* unhalt engine */ 599 temp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL)); 600 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 601 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp); 602 } 603 604 /* enable DMA RB */ 605 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 606 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 607 608 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL)); 609 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 610 #ifdef __BIG_ENDIAN 611 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 612 #endif 613 /* enable DMA IBs */ 614 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 615 616 ring->ready = true; 617 618 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 619 sdma_v4_0_ctx_switch_enable(adev, true); 620 sdma_v4_0_enable(adev, true); 621 } 622 623 r = amdgpu_ring_test_ring(ring); 624 if (r) { 625 ring->ready = false; 626 return r; 627 } 628 629 if (adev->mman.buffer_funcs_ring == ring) 630 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 631 } 632 633 return 0; 634 } 635 636 /** 637 * sdma_v4_0_rlc_resume - setup and start the async dma engines 638 * 639 * @adev: amdgpu_device pointer 640 * 641 * Set up the compute DMA queues and enable them (VEGA10). 642 * Returns 0 for success, error for failure. 643 */ 644 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 645 { 646 /* XXX todo */ 647 return 0; 648 } 649 650 /** 651 * sdma_v4_0_load_microcode - load the sDMA ME ucode 652 * 653 * @adev: amdgpu_device pointer 654 * 655 * Loads the sDMA0/1 ucode. 656 * Returns 0 for success, -EINVAL if the ucode is not available. 657 */ 658 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 659 { 660 const struct sdma_firmware_header_v1_0 *hdr; 661 const __le32 *fw_data; 662 u32 fw_size; 663 u32 digest_size = 0; 664 int i, j; 665 666 /* halt the MEs */ 667 sdma_v4_0_enable(adev, false); 668 669 for (i = 0; i < adev->sdma.num_instances; i++) { 670 uint16_t version_major; 671 uint16_t version_minor; 672 if (!adev->sdma.instance[i].fw) 673 return -EINVAL; 674 675 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 676 amdgpu_ucode_print_sdma_hdr(&hdr->header); 677 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 678 679 version_major = le16_to_cpu(hdr->header.header_version_major); 680 version_minor = le16_to_cpu(hdr->header.header_version_minor); 681 682 if (version_major == 1 && version_minor >= 1) { 683 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = (const struct sdma_firmware_header_v1_1 *) hdr; 684 digest_size = le32_to_cpu(sdma_v1_1_hdr->digest_size); 685 } 686 687 fw_size -= digest_size; 688 689 fw_data = (const __le32 *) 690 (adev->sdma.instance[i].fw->data + 691 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 692 693 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), 0); 694 695 696 for (j = 0; j < fw_size; j++) 697 { 698 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 699 } 700 701 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 702 } 703 704 sdma_v4_0_print_ucode_regs(adev); 705 706 return 0; 707 } 708 709 /** 710 * sdma_v4_0_start - setup and start the async dma engines 711 * 712 * @adev: amdgpu_device pointer 713 * 714 * Set up the DMA engines and enable them (VEGA10). 715 * Returns 0 for success, error for failure. 716 */ 717 static int sdma_v4_0_start(struct amdgpu_device *adev) 718 { 719 int r = 0; 720 721 if (amdgpu_sriov_vf(adev)) { 722 sdma_v4_0_ctx_switch_enable(adev, false); 723 sdma_v4_0_enable(adev, false); 724 725 /* set RB registers */ 726 r = sdma_v4_0_gfx_resume(adev); 727 return r; 728 } 729 730 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 731 DRM_INFO("Loading via direct write\n"); 732 r = sdma_v4_0_load_microcode(adev); 733 if (r) 734 return r; 735 } 736 737 /* unhalt the MEs */ 738 sdma_v4_0_enable(adev, true); 739 /* enable sdma ring preemption */ 740 sdma_v4_0_ctx_switch_enable(adev, true); 741 742 /* start the gfx rings and rlc compute queues */ 743 r = sdma_v4_0_gfx_resume(adev); 744 if (r) 745 return r; 746 r = sdma_v4_0_rlc_resume(adev); 747 if (r) 748 return r; 749 750 return 0; 751 } 752 753 /** 754 * sdma_v4_0_ring_test_ring - simple async dma engine test 755 * 756 * @ring: amdgpu_ring structure holding ring information 757 * 758 * Test the DMA engine by writing using it to write an 759 * value to memory. (VEGA10). 760 * Returns 0 for success, error for failure. 761 */ 762 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 763 { 764 struct amdgpu_device *adev = ring->adev; 765 unsigned i; 766 unsigned index; 767 int r; 768 u32 tmp; 769 u64 gpu_addr; 770 771 DRM_INFO("In Ring test func\n"); 772 773 r = amdgpu_wb_get(adev, &index); 774 if (r) { 775 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 776 return r; 777 } 778 779 gpu_addr = adev->wb.gpu_addr + (index * 4); 780 tmp = 0xCAFEDEAD; 781 adev->wb.wb[index] = cpu_to_le32(tmp); 782 783 r = amdgpu_ring_alloc(ring, 5); 784 if (r) { 785 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 786 amdgpu_wb_free(adev, index); 787 return r; 788 } 789 790 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 791 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 792 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 793 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 794 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 795 amdgpu_ring_write(ring, 0xDEADBEEF); 796 amdgpu_ring_commit(ring); 797 798 for (i = 0; i < adev->usec_timeout; i++) { 799 tmp = le32_to_cpu(adev->wb.wb[index]); 800 if (tmp == 0xDEADBEEF) { 801 break; 802 } 803 DRM_UDELAY(1); 804 } 805 806 if (i < adev->usec_timeout) { 807 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 808 } else { 809 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 810 ring->idx, tmp); 811 r = -EINVAL; 812 } 813 amdgpu_wb_free(adev, index); 814 815 return r; 816 } 817 818 /** 819 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 820 * 821 * @ring: amdgpu_ring structure holding ring information 822 * 823 * Test a simple IB in the DMA ring (VEGA10). 824 * Returns 0 on success, error on failure. 825 */ 826 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 827 { 828 struct amdgpu_device *adev = ring->adev; 829 struct amdgpu_ib ib; 830 struct dma_fence *f = NULL; 831 unsigned index; 832 long r; 833 u32 tmp = 0; 834 u64 gpu_addr; 835 836 r = amdgpu_wb_get(adev, &index); 837 if (r) { 838 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 839 return r; 840 } 841 842 gpu_addr = adev->wb.gpu_addr + (index * 4); 843 tmp = 0xCAFEDEAD; 844 adev->wb.wb[index] = cpu_to_le32(tmp); 845 memset(&ib, 0, sizeof(ib)); 846 r = amdgpu_ib_get(adev, NULL, 256, &ib); 847 if (r) { 848 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 849 goto err0; 850 } 851 852 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 853 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 854 ib.ptr[1] = lower_32_bits(gpu_addr); 855 ib.ptr[2] = upper_32_bits(gpu_addr); 856 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 857 ib.ptr[4] = 0xDEADBEEF; 858 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 859 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 860 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 861 ib.length_dw = 8; 862 863 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 864 if (r) 865 goto err1; 866 867 r = dma_fence_wait_timeout(f, false, timeout); 868 if (r == 0) { 869 DRM_ERROR("amdgpu: IB test timed out\n"); 870 r = -ETIMEDOUT; 871 goto err1; 872 } else if (r < 0) { 873 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 874 goto err1; 875 } 876 tmp = le32_to_cpu(adev->wb.wb[index]); 877 if (tmp == 0xDEADBEEF) { 878 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 879 r = 0; 880 } else { 881 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 882 r = -EINVAL; 883 } 884 err1: 885 amdgpu_ib_free(adev, &ib, NULL); 886 dma_fence_put(f); 887 err0: 888 amdgpu_wb_free(adev, index); 889 return r; 890 } 891 892 893 /** 894 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 895 * 896 * @ib: indirect buffer to fill with commands 897 * @pe: addr of the page entry 898 * @src: src addr to copy from 899 * @count: number of page entries to update 900 * 901 * Update PTEs by copying them from the GART using sDMA (VEGA10). 902 */ 903 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 904 uint64_t pe, uint64_t src, 905 unsigned count) 906 { 907 unsigned bytes = count * 8; 908 909 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 910 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 911 ib->ptr[ib->length_dw++] = bytes - 1; 912 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 913 ib->ptr[ib->length_dw++] = lower_32_bits(src); 914 ib->ptr[ib->length_dw++] = upper_32_bits(src); 915 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 916 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 917 918 } 919 920 /** 921 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 922 * 923 * @ib: indirect buffer to fill with commands 924 * @pe: addr of the page entry 925 * @addr: dst addr to write into pe 926 * @count: number of page entries to update 927 * @incr: increase next addr by incr bytes 928 * @flags: access flags 929 * 930 * Update PTEs by writing them manually using sDMA (VEGA10). 931 */ 932 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 933 uint64_t value, unsigned count, 934 uint32_t incr) 935 { 936 unsigned ndw = count * 2; 937 938 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 939 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 940 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 941 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 942 ib->ptr[ib->length_dw++] = ndw - 1; 943 for (; ndw > 0; ndw -= 2) { 944 ib->ptr[ib->length_dw++] = lower_32_bits(value); 945 ib->ptr[ib->length_dw++] = upper_32_bits(value); 946 value += incr; 947 } 948 } 949 950 /** 951 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 952 * 953 * @ib: indirect buffer to fill with commands 954 * @pe: addr of the page entry 955 * @addr: dst addr to write into pe 956 * @count: number of page entries to update 957 * @incr: increase next addr by incr bytes 958 * @flags: access flags 959 * 960 * Update the page tables using sDMA (VEGA10). 961 */ 962 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 963 uint64_t pe, 964 uint64_t addr, unsigned count, 965 uint32_t incr, uint64_t flags) 966 { 967 /* for physically contiguous pages (vram) */ 968 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 969 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 970 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 971 ib->ptr[ib->length_dw++] = flags; /* mask */ 972 ib->ptr[ib->length_dw++] = 0; 973 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 974 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 975 ib->ptr[ib->length_dw++] = incr; /* increment size */ 976 ib->ptr[ib->length_dw++] = 0; 977 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 978 } 979 980 /** 981 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 982 * 983 * @ib: indirect buffer to fill with padding 984 * 985 */ 986 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 987 { 988 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 989 u32 pad_count; 990 int i; 991 992 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 993 for (i = 0; i < pad_count; i++) 994 if (sdma && sdma->burst_nop && (i == 0)) 995 ib->ptr[ib->length_dw++] = 996 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 997 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 998 else 999 ib->ptr[ib->length_dw++] = 1000 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1001 } 1002 1003 1004 /** 1005 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1006 * 1007 * @ring: amdgpu_ring pointer 1008 * 1009 * Make sure all previous operations are completed (CIK). 1010 */ 1011 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1012 { 1013 uint32_t seq = ring->fence_drv.sync_seq; 1014 uint64_t addr = ring->fence_drv.gpu_addr; 1015 1016 /* wait for idle */ 1017 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1018 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1019 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1020 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1021 amdgpu_ring_write(ring, addr & 0xfffffffc); 1022 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1023 amdgpu_ring_write(ring, seq); /* reference */ 1024 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 1025 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1026 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1027 } 1028 1029 1030 /** 1031 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1032 * 1033 * @ring: amdgpu_ring pointer 1034 * @vm: amdgpu_vm pointer 1035 * 1036 * Update the page table base and flush the VM TLB 1037 * using sDMA (VEGA10). 1038 */ 1039 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1040 unsigned vm_id, uint64_t pd_addr) 1041 { 1042 unsigned eng = ring->idx; 1043 unsigned i; 1044 1045 pd_addr = pd_addr | 0x1; /* valid bit */ 1046 /* now only use physical base address of PDE and valid */ 1047 BUG_ON(pd_addr & 0xFFFF00000000003EULL); 1048 1049 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { 1050 struct amdgpu_vmhub *hub = &ring->adev->vmhub[i]; 1051 uint32_t req = hub->get_invalidate_req(vm_id); 1052 1053 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1054 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1055 amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vm_id * 2); 1056 amdgpu_ring_write(ring, lower_32_bits(pd_addr)); 1057 1058 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1059 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1060 amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vm_id * 2); 1061 amdgpu_ring_write(ring, upper_32_bits(pd_addr)); 1062 1063 /* flush TLB */ 1064 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1065 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1066 amdgpu_ring_write(ring, hub->vm_inv_eng0_req + eng); 1067 amdgpu_ring_write(ring, req); 1068 1069 /* wait for flush */ 1070 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1071 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1072 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1073 amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2); 1074 amdgpu_ring_write(ring, 0); 1075 amdgpu_ring_write(ring, 1 << vm_id); /* reference */ 1076 amdgpu_ring_write(ring, 1 << vm_id); /* mask */ 1077 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1078 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1079 } 1080 } 1081 1082 static int sdma_v4_0_early_init(void *handle) 1083 { 1084 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1085 1086 adev->sdma.num_instances = 2; 1087 1088 sdma_v4_0_set_ring_funcs(adev); 1089 sdma_v4_0_set_buffer_funcs(adev); 1090 sdma_v4_0_set_vm_pte_funcs(adev); 1091 sdma_v4_0_set_irq_funcs(adev); 1092 1093 return 0; 1094 } 1095 1096 1097 static int sdma_v4_0_sw_init(void *handle) 1098 { 1099 struct amdgpu_ring *ring; 1100 int r, i; 1101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1102 1103 /* SDMA trap event */ 1104 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224, 1105 &adev->sdma.trap_irq); 1106 if (r) 1107 return r; 1108 1109 /* SDMA trap event */ 1110 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224, 1111 &adev->sdma.trap_irq); 1112 if (r) 1113 return r; 1114 1115 r = sdma_v4_0_init_microcode(adev); 1116 if (r) { 1117 DRM_ERROR("Failed to load sdma firmware!\n"); 1118 return r; 1119 } 1120 1121 for (i = 0; i < adev->sdma.num_instances; i++) { 1122 ring = &adev->sdma.instance[i].ring; 1123 ring->ring_obj = NULL; 1124 ring->use_doorbell = true; 1125 1126 DRM_INFO("use_doorbell being set to: [%s]\n", 1127 ring->use_doorbell?"true":"false"); 1128 1129 ring->doorbell_index = (i == 0) ? 1130 (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset 1131 : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset 1132 1133 sprintf(ring->name, "sdma%d", i); 1134 r = amdgpu_ring_init(adev, ring, 1024, 1135 &adev->sdma.trap_irq, 1136 (i == 0) ? 1137 AMDGPU_SDMA_IRQ_TRAP0 : 1138 AMDGPU_SDMA_IRQ_TRAP1); 1139 if (r) 1140 return r; 1141 } 1142 1143 return r; 1144 } 1145 1146 static int sdma_v4_0_sw_fini(void *handle) 1147 { 1148 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1149 int i; 1150 1151 for (i = 0; i < adev->sdma.num_instances; i++) 1152 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1153 1154 return 0; 1155 } 1156 1157 static int sdma_v4_0_hw_init(void *handle) 1158 { 1159 int r; 1160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1161 1162 sdma_v4_0_init_golden_registers(adev); 1163 1164 r = sdma_v4_0_start(adev); 1165 if (r) 1166 return r; 1167 1168 return r; 1169 } 1170 1171 static int sdma_v4_0_hw_fini(void *handle) 1172 { 1173 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1174 1175 if (amdgpu_sriov_vf(adev)) 1176 return 0; 1177 1178 sdma_v4_0_ctx_switch_enable(adev, false); 1179 sdma_v4_0_enable(adev, false); 1180 1181 return 0; 1182 } 1183 1184 static int sdma_v4_0_suspend(void *handle) 1185 { 1186 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1187 1188 return sdma_v4_0_hw_fini(adev); 1189 } 1190 1191 static int sdma_v4_0_resume(void *handle) 1192 { 1193 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1194 1195 return sdma_v4_0_hw_init(adev); 1196 } 1197 1198 static bool sdma_v4_0_is_idle(void *handle) 1199 { 1200 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1201 u32 i; 1202 for (i = 0; i < adev->sdma.num_instances; i++) { 1203 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_STATUS_REG)); 1204 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1205 return false; 1206 } 1207 1208 return true; 1209 } 1210 1211 static int sdma_v4_0_wait_for_idle(void *handle) 1212 { 1213 unsigned i; 1214 u32 sdma0,sdma1; 1215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1216 for (i = 0; i < adev->usec_timeout; i++) { 1217 sdma0 = RREG32(sdma_v4_0_get_reg_offset(0, mmSDMA0_STATUS_REG)); 1218 sdma1 = RREG32(sdma_v4_0_get_reg_offset(1, mmSDMA0_STATUS_REG)); 1219 1220 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1221 return 0; 1222 udelay(1); 1223 } 1224 return -ETIMEDOUT; 1225 } 1226 1227 static int sdma_v4_0_soft_reset(void *handle) 1228 { 1229 /* todo */ 1230 1231 return 0; 1232 } 1233 1234 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1235 struct amdgpu_irq_src *source, 1236 unsigned type, 1237 enum amdgpu_interrupt_state state) 1238 { 1239 u32 sdma_cntl; 1240 1241 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 1242 sdma_v4_0_get_reg_offset(0, mmSDMA0_CNTL) : 1243 sdma_v4_0_get_reg_offset(1, mmSDMA0_CNTL); 1244 1245 sdma_cntl = RREG32(reg_offset); 1246 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1247 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1248 WREG32(reg_offset, sdma_cntl); 1249 1250 return 0; 1251 } 1252 1253 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1254 struct amdgpu_irq_src *source, 1255 struct amdgpu_iv_entry *entry) 1256 { 1257 DRM_DEBUG("IH: SDMA trap\n"); 1258 switch (entry->client_id) { 1259 case AMDGPU_IH_CLIENTID_SDMA0: 1260 switch (entry->ring_id) { 1261 case 0: 1262 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1263 break; 1264 case 1: 1265 /* XXX compute */ 1266 break; 1267 case 2: 1268 /* XXX compute */ 1269 break; 1270 case 3: 1271 /* XXX page queue*/ 1272 break; 1273 } 1274 break; 1275 case AMDGPU_IH_CLIENTID_SDMA1: 1276 switch (entry->ring_id) { 1277 case 0: 1278 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1279 break; 1280 case 1: 1281 /* XXX compute */ 1282 break; 1283 case 2: 1284 /* XXX compute */ 1285 break; 1286 case 3: 1287 /* XXX page queue*/ 1288 break; 1289 } 1290 break; 1291 } 1292 return 0; 1293 } 1294 1295 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1296 struct amdgpu_irq_src *source, 1297 struct amdgpu_iv_entry *entry) 1298 { 1299 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1300 schedule_work(&adev->reset_work); 1301 return 0; 1302 } 1303 1304 1305 static void sdma_v4_0_update_medium_grain_clock_gating( 1306 struct amdgpu_device *adev, 1307 bool enable) 1308 { 1309 uint32_t data, def; 1310 1311 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1312 /* enable sdma0 clock gating */ 1313 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1314 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1315 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1316 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1317 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1318 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1319 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1320 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1321 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1322 if (def != data) 1323 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1324 1325 if (adev->asic_type == CHIP_VEGA10) { 1326 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1327 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1328 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1329 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1330 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1331 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1332 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1333 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1334 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1335 if(def != data) 1336 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1337 } 1338 } else { 1339 /* disable sdma0 clock gating */ 1340 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1341 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1342 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1343 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1344 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1345 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1346 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1347 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1348 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1349 1350 if (def != data) 1351 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1352 1353 if (adev->asic_type == CHIP_VEGA10) { 1354 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1355 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1356 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1357 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1358 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1359 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1360 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1361 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1362 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1363 if (def != data) 1364 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1365 } 1366 } 1367 } 1368 1369 1370 static void sdma_v4_0_update_medium_grain_light_sleep( 1371 struct amdgpu_device *adev, 1372 bool enable) 1373 { 1374 uint32_t data, def; 1375 1376 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1377 /* 1-not override: enable sdma0 mem light sleep */ 1378 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1379 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1380 if (def != data) 1381 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1382 1383 /* 1-not override: enable sdma1 mem light sleep */ 1384 if (adev->asic_type == CHIP_VEGA10) { 1385 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1386 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1387 if (def != data) 1388 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1389 } 1390 } else { 1391 /* 0-override:disable sdma0 mem light sleep */ 1392 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1393 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1394 if (def != data) 1395 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1396 1397 /* 0-override:disable sdma1 mem light sleep */ 1398 if (adev->asic_type == CHIP_VEGA10) { 1399 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1400 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1401 if (def != data) 1402 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1403 } 1404 } 1405 } 1406 1407 static int sdma_v4_0_set_clockgating_state(void *handle, 1408 enum amd_clockgating_state state) 1409 { 1410 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1411 1412 if (amdgpu_sriov_vf(adev)) 1413 return 0; 1414 1415 switch (adev->asic_type) { 1416 case CHIP_VEGA10: 1417 sdma_v4_0_update_medium_grain_clock_gating(adev, 1418 state == AMD_CG_STATE_GATE ? true : false); 1419 sdma_v4_0_update_medium_grain_light_sleep(adev, 1420 state == AMD_CG_STATE_GATE ? true : false); 1421 break; 1422 default: 1423 break; 1424 } 1425 return 0; 1426 } 1427 1428 static int sdma_v4_0_set_powergating_state(void *handle, 1429 enum amd_powergating_state state) 1430 { 1431 return 0; 1432 } 1433 1434 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 1435 { 1436 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1437 int data; 1438 1439 if (amdgpu_sriov_vf(adev)) 1440 *flags = 0; 1441 1442 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1443 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1444 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1445 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1446 1447 /* AMD_CG_SUPPORT_SDMA_LS */ 1448 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1449 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1450 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1451 } 1452 1453 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 1454 .name = "sdma_v4_0", 1455 .early_init = sdma_v4_0_early_init, 1456 .late_init = NULL, 1457 .sw_init = sdma_v4_0_sw_init, 1458 .sw_fini = sdma_v4_0_sw_fini, 1459 .hw_init = sdma_v4_0_hw_init, 1460 .hw_fini = sdma_v4_0_hw_fini, 1461 .suspend = sdma_v4_0_suspend, 1462 .resume = sdma_v4_0_resume, 1463 .is_idle = sdma_v4_0_is_idle, 1464 .wait_for_idle = sdma_v4_0_wait_for_idle, 1465 .soft_reset = sdma_v4_0_soft_reset, 1466 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 1467 .set_powergating_state = sdma_v4_0_set_powergating_state, 1468 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 1469 }; 1470 1471 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 1472 .type = AMDGPU_RING_TYPE_SDMA, 1473 .align_mask = 0xf, 1474 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1475 .support_64bit_ptrs = true, 1476 .get_rptr = sdma_v4_0_ring_get_rptr, 1477 .get_wptr = sdma_v4_0_ring_get_wptr, 1478 .set_wptr = sdma_v4_0_ring_set_wptr, 1479 .emit_frame_size = 1480 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1481 3 + /* sdma_v4_0_ring_emit_hdp_invalidate */ 1482 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1483 36 + /* sdma_v4_0_ring_emit_vm_flush */ 1484 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1485 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1486 .emit_ib = sdma_v4_0_ring_emit_ib, 1487 .emit_fence = sdma_v4_0_ring_emit_fence, 1488 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1489 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1490 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1491 .emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate, 1492 .test_ring = sdma_v4_0_ring_test_ring, 1493 .test_ib = sdma_v4_0_ring_test_ib, 1494 .insert_nop = sdma_v4_0_ring_insert_nop, 1495 .pad_ib = sdma_v4_0_ring_pad_ib, 1496 }; 1497 1498 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 1499 { 1500 int i; 1501 1502 for (i = 0; i < adev->sdma.num_instances; i++) 1503 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 1504 } 1505 1506 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 1507 .set = sdma_v4_0_set_trap_irq_state, 1508 .process = sdma_v4_0_process_trap_irq, 1509 }; 1510 1511 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 1512 .process = sdma_v4_0_process_illegal_inst_irq, 1513 }; 1514 1515 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 1516 { 1517 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1518 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 1519 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 1520 } 1521 1522 /** 1523 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 1524 * 1525 * @ring: amdgpu_ring structure holding ring information 1526 * @src_offset: src GPU address 1527 * @dst_offset: dst GPU address 1528 * @byte_count: number of bytes to xfer 1529 * 1530 * Copy GPU buffers using the DMA engine (VEGA10). 1531 * Used by the amdgpu ttm implementation to move pages if 1532 * registered as the asic copy callback. 1533 */ 1534 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 1535 uint64_t src_offset, 1536 uint64_t dst_offset, 1537 uint32_t byte_count) 1538 { 1539 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1540 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1541 ib->ptr[ib->length_dw++] = byte_count - 1; 1542 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1543 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1544 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1545 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1546 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1547 } 1548 1549 /** 1550 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 1551 * 1552 * @ring: amdgpu_ring structure holding ring information 1553 * @src_data: value to write to buffer 1554 * @dst_offset: dst GPU address 1555 * @byte_count: number of bytes to xfer 1556 * 1557 * Fill GPU buffers using the DMA engine (VEGA10). 1558 */ 1559 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 1560 uint32_t src_data, 1561 uint64_t dst_offset, 1562 uint32_t byte_count) 1563 { 1564 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1565 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1566 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1567 ib->ptr[ib->length_dw++] = src_data; 1568 ib->ptr[ib->length_dw++] = byte_count - 1; 1569 } 1570 1571 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 1572 .copy_max_bytes = 0x400000, 1573 .copy_num_dw = 7, 1574 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 1575 1576 .fill_max_bytes = 0x400000, 1577 .fill_num_dw = 5, 1578 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 1579 }; 1580 1581 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 1582 { 1583 if (adev->mman.buffer_funcs == NULL) { 1584 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 1585 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1586 } 1587 } 1588 1589 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 1590 .copy_pte = sdma_v4_0_vm_copy_pte, 1591 .write_pte = sdma_v4_0_vm_write_pte, 1592 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 1593 }; 1594 1595 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1596 { 1597 unsigned i; 1598 1599 if (adev->vm_manager.vm_pte_funcs == NULL) { 1600 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 1601 for (i = 0; i < adev->sdma.num_instances; i++) 1602 adev->vm_manager.vm_pte_rings[i] = 1603 &adev->sdma.instance[i].ring; 1604 1605 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1606 } 1607 } 1608 1609 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = 1610 { 1611 .type = AMD_IP_BLOCK_TYPE_SDMA, 1612 .major = 4, 1613 .minor = 0, 1614 .rev = 0, 1615 .funcs = &sdma_v4_0_ip_funcs, 1616 }; 1617