1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32 
33 #include "sdma0/sdma0_4_2_offset.h"
34 #include "sdma0/sdma0_4_2_sh_mask.h"
35 #include "sdma1/sdma1_4_2_offset.h"
36 #include "sdma1/sdma1_4_2_sh_mask.h"
37 #include "sdma2/sdma2_4_2_2_offset.h"
38 #include "sdma2/sdma2_4_2_2_sh_mask.h"
39 #include "sdma3/sdma3_4_2_2_offset.h"
40 #include "sdma3/sdma3_4_2_2_sh_mask.h"
41 #include "sdma4/sdma4_4_2_2_offset.h"
42 #include "sdma4/sdma4_4_2_2_sh_mask.h"
43 #include "sdma5/sdma5_4_2_2_offset.h"
44 #include "sdma5/sdma5_4_2_2_sh_mask.h"
45 #include "sdma6/sdma6_4_2_2_offset.h"
46 #include "sdma6/sdma6_4_2_2_sh_mask.h"
47 #include "sdma7/sdma7_4_2_2_offset.h"
48 #include "sdma7/sdma7_4_2_2_sh_mask.h"
49 #include "sdma0/sdma0_4_1_default.h"
50 
51 #include "soc15_common.h"
52 #include "soc15.h"
53 #include "vega10_sdma_pkt_open.h"
54 
55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
56 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
57 
58 #include "amdgpu_ras.h"
59 #include "sdma_v4_4.h"
60 
61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
72 MODULE_FIRMWARE("amdgpu/green_sardine_sdma.bin");
73 MODULE_FIRMWARE("amdgpu/aldebaran_sdma.bin");
74 
75 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
76 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
77 
78 #define WREG32_SDMA(instance, offset, value) \
79 	WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
80 #define RREG32_SDMA(instance, offset) \
81 	RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
82 
83 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
84 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
85 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
86 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
87 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev);
88 
89 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
90 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
91 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
92 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
93 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
95 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
96 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
97 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
98 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
99 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
100 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
101 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
102 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
103 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
104 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
105 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
106 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
107 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
108 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
109 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
110 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
111 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
112 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
113 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
114 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
115 };
116 
117 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
118 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
119 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
120 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
121 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
122 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
123 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
124 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
125 };
126 
127 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
128 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
129 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
130 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
131 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
132 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
133 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
134 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
135 };
136 
137 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
138 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
139 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
140 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
141 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
142 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
143 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
144 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
146 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
147 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
148 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
149 };
150 
151 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
152 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
153 };
154 
155 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
156 {
157 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
158 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
159 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
160 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
161 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
162 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
163 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
164 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
165 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
166 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
167 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
168 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
169 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
170 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
171 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
172 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
173 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
174 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
175 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
176 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
177 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
178 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
179 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
180 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
181 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
182 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
183 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
184 };
185 
186 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
187 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
188 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
189 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
190 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
191 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
192 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
193 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
194 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
195 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
196 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
197 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
198 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
199 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
200 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
201 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
202 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
203 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
204 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
205 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
206 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
207 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
208 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
209 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
210 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
211 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
212 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
213 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
214 };
215 
216 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
217 {
218 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
219 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
220 };
221 
222 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
223 {
224 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
225 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
226 };
227 
228 static const struct soc15_reg_golden golden_settings_sdma_arct[] =
229 {
230 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
231 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
232 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
233 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
234 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
235 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
236 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
237 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
238 	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
239 	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
240 	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
241 	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
242 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
243 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
244 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
245 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
246 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
247 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
248 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
249 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
250 	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
251 	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
252 	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
253 	SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
254 	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
255 	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
256 	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
257 	SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
258 	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
259 	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
260 	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
261 	SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_UTCL1_TIMEOUT, 0xffffffff, 0x00010001)
262 };
263 
264 static const struct soc15_reg_golden golden_settings_sdma_aldebaran[] = {
265 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
266 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
267 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
268 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
269 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
270 	SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
271 	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
272 	SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
273 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA2_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
274 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
275 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
276 	SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
277 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
278 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
279 	SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_UTCL1_TIMEOUT, 0xffffffff, 0x00010001),
280 };
281 
282 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
283 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
284 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
285 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
286 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
287 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
288 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
289 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
290 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
291 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003e0),
292 	SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
293 };
294 
295 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = {
296 	{ "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
297 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED),
298 	0, 0,
299 	},
300 	{ "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
301 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED),
302 	0, 0,
303 	},
304 	{ "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
305 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED),
306 	0, 0,
307 	},
308 	{ "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
309 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED),
310 	0, 0,
311 	},
312 	{ "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
313 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED),
314 	0, 0,
315 	},
316 	{ "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
317 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED),
318 	0, 0,
319 	},
320 	{ "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
321 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
322 	0, 0,
323 	},
324 	{ "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
325 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
326 	0, 0,
327 	},
328 	{ "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
329 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
330 	0, 0,
331 	},
332 	{ "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
333 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
334 	0, 0,
335 	},
336 	{ "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
337 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
338 	0, 0,
339 	},
340 	{ "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
341 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
342 	0, 0,
343 	},
344 	{ "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
345 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
346 	0, 0,
347 	},
348 	{ "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
349 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
350 	0, 0,
351 	},
352 	{ "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
353 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
354 	0, 0,
355 	},
356 	{ "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
357 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
358 	0, 0,
359 	},
360 	{ "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
361 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
362 	0, 0,
363 	},
364 	{ "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
365 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
366 	0, 0,
367 	},
368 	{ "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
369 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
370 	0, 0,
371 	},
372 	{ "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
373 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
374 	0, 0,
375 	},
376 	{ "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
377 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
378 	0, 0,
379 	},
380 	{ "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
381 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
382 	0, 0,
383 	},
384 	{ "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
385 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED),
386 	0, 0,
387 	},
388 	{ "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
389 	SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED),
390 	0, 0,
391 	},
392 };
393 
394 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
395 		u32 instance, u32 offset)
396 {
397 	switch (instance) {
398 	case 0:
399 		return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
400 	case 1:
401 		return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
402 	case 2:
403 		return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
404 	case 3:
405 		return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
406 	case 4:
407 		return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
408 	case 5:
409 		return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
410 	case 6:
411 		return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
412 	case 7:
413 		return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
414 	default:
415 		break;
416 	}
417 	return 0;
418 }
419 
420 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
421 {
422 	switch (seq_num) {
423 	case 0:
424 		return SOC15_IH_CLIENTID_SDMA0;
425 	case 1:
426 		return SOC15_IH_CLIENTID_SDMA1;
427 	case 2:
428 		return SOC15_IH_CLIENTID_SDMA2;
429 	case 3:
430 		return SOC15_IH_CLIENTID_SDMA3;
431 	case 4:
432 		return SOC15_IH_CLIENTID_SDMA4;
433 	case 5:
434 		return SOC15_IH_CLIENTID_SDMA5;
435 	case 6:
436 		return SOC15_IH_CLIENTID_SDMA6;
437 	case 7:
438 		return SOC15_IH_CLIENTID_SDMA7;
439 	default:
440 		break;
441 	}
442 	return -EINVAL;
443 }
444 
445 static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
446 {
447 	switch (client_id) {
448 	case SOC15_IH_CLIENTID_SDMA0:
449 		return 0;
450 	case SOC15_IH_CLIENTID_SDMA1:
451 		return 1;
452 	case SOC15_IH_CLIENTID_SDMA2:
453 		return 2;
454 	case SOC15_IH_CLIENTID_SDMA3:
455 		return 3;
456 	case SOC15_IH_CLIENTID_SDMA4:
457 		return 4;
458 	case SOC15_IH_CLIENTID_SDMA5:
459 		return 5;
460 	case SOC15_IH_CLIENTID_SDMA6:
461 		return 6;
462 	case SOC15_IH_CLIENTID_SDMA7:
463 		return 7;
464 	default:
465 		break;
466 	}
467 	return -EINVAL;
468 }
469 
470 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
471 {
472 	switch (adev->ip_versions[SDMA0_HWIP][0]) {
473 	case IP_VERSION(4, 0, 0):
474 		soc15_program_register_sequence(adev,
475 						golden_settings_sdma_4,
476 						ARRAY_SIZE(golden_settings_sdma_4));
477 		soc15_program_register_sequence(adev,
478 						golden_settings_sdma_vg10,
479 						ARRAY_SIZE(golden_settings_sdma_vg10));
480 		break;
481 	case IP_VERSION(4, 0, 1):
482 		soc15_program_register_sequence(adev,
483 						golden_settings_sdma_4,
484 						ARRAY_SIZE(golden_settings_sdma_4));
485 		soc15_program_register_sequence(adev,
486 						golden_settings_sdma_vg12,
487 						ARRAY_SIZE(golden_settings_sdma_vg12));
488 		break;
489 	case IP_VERSION(4, 2, 0):
490 		soc15_program_register_sequence(adev,
491 						golden_settings_sdma0_4_2_init,
492 						ARRAY_SIZE(golden_settings_sdma0_4_2_init));
493 		soc15_program_register_sequence(adev,
494 						golden_settings_sdma0_4_2,
495 						ARRAY_SIZE(golden_settings_sdma0_4_2));
496 		soc15_program_register_sequence(adev,
497 						golden_settings_sdma1_4_2,
498 						ARRAY_SIZE(golden_settings_sdma1_4_2));
499 		break;
500 	case IP_VERSION(4, 2, 2):
501 		soc15_program_register_sequence(adev,
502 						golden_settings_sdma_arct,
503 						ARRAY_SIZE(golden_settings_sdma_arct));
504 		break;
505 	case IP_VERSION(4, 4, 0):
506 		soc15_program_register_sequence(adev,
507 						golden_settings_sdma_aldebaran,
508 						ARRAY_SIZE(golden_settings_sdma_aldebaran));
509 		break;
510 	case IP_VERSION(4, 1, 0):
511 	case IP_VERSION(4, 1, 1):
512 		soc15_program_register_sequence(adev,
513 						golden_settings_sdma_4_1,
514 						ARRAY_SIZE(golden_settings_sdma_4_1));
515 		if (adev->apu_flags & AMD_APU_IS_RAVEN2)
516 			soc15_program_register_sequence(adev,
517 							golden_settings_sdma_rv2,
518 							ARRAY_SIZE(golden_settings_sdma_rv2));
519 		else
520 			soc15_program_register_sequence(adev,
521 							golden_settings_sdma_rv1,
522 							ARRAY_SIZE(golden_settings_sdma_rv1));
523 		break;
524 	case IP_VERSION(4, 1, 2):
525 		soc15_program_register_sequence(adev,
526 						golden_settings_sdma_4_3,
527 						ARRAY_SIZE(golden_settings_sdma_4_3));
528 		break;
529 	default:
530 		break;
531 	}
532 }
533 
534 static void sdma_v4_0_setup_ulv(struct amdgpu_device *adev)
535 {
536 	int i;
537 
538 	/*
539 	 * The only chips with SDMAv4 and ULV are VG10 and VG20.
540 	 * Server SKUs take a different hysteresis setting from other SKUs.
541 	 */
542 	switch (adev->ip_versions[SDMA0_HWIP][0]) {
543 	case IP_VERSION(4, 0, 0):
544 		if (adev->pdev->device == 0x6860)
545 			break;
546 		return;
547 	case IP_VERSION(4, 2, 0):
548 		if (adev->pdev->device == 0x66a1)
549 			break;
550 		return;
551 	default:
552 		return;
553 	}
554 
555 	for (i = 0; i < adev->sdma.num_instances; i++) {
556 		uint32_t temp;
557 
558 		temp = RREG32_SDMA(i, mmSDMA0_ULV_CNTL);
559 		temp = REG_SET_FIELD(temp, SDMA0_ULV_CNTL, HYSTERESIS, 0x0);
560 		WREG32_SDMA(i, mmSDMA0_ULV_CNTL, temp);
561 	}
562 }
563 
564 /**
565  * sdma_v4_0_init_microcode - load ucode images from disk
566  *
567  * @adev: amdgpu_device pointer
568  *
569  * Use the firmware interface to load the ucode images into
570  * the driver (not loaded into hw).
571  * Returns 0 on success, error on failure.
572  */
573 
574 // emulation only, won't work on real chip
575 // vega10 real chip need to use PSP to load firmware
576 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
577 {
578 	int ret, i;
579 
580 	for (i = 0; i < adev->sdma.num_instances; i++) {
581 		if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
582                     adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) {
583 			/* Acturus & Aldebaran will leverage the same FW memory
584 			   for every SDMA instance */
585 			ret = amdgpu_sdma_init_microcode(adev, 0, true);
586 			break;
587 		} else {
588 			ret = amdgpu_sdma_init_microcode(adev, i, false);
589 			if (ret)
590 				return ret;
591 		}
592 	}
593 
594 	return ret;
595 }
596 
597 /**
598  * sdma_v4_0_ring_get_rptr - get the current read pointer
599  *
600  * @ring: amdgpu ring pointer
601  *
602  * Get the current rptr from the hardware (VEGA10+).
603  */
604 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
605 {
606 	u64 *rptr;
607 
608 	/* XXX check if swapping is necessary on BE */
609 	rptr = ((u64 *)ring->rptr_cpu_addr);
610 
611 	DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
612 	return ((*rptr) >> 2);
613 }
614 
615 /**
616  * sdma_v4_0_ring_get_wptr - get the current write pointer
617  *
618  * @ring: amdgpu ring pointer
619  *
620  * Get the current wptr from the hardware (VEGA10+).
621  */
622 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
623 {
624 	struct amdgpu_device *adev = ring->adev;
625 	u64 wptr;
626 
627 	if (ring->use_doorbell) {
628 		/* XXX check if swapping is necessary on BE */
629 		wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
630 		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
631 	} else {
632 		wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
633 		wptr = wptr << 32;
634 		wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
635 		DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
636 				ring->me, wptr);
637 	}
638 
639 	return wptr >> 2;
640 }
641 
642 /**
643  * sdma_v4_0_ring_set_wptr - commit the write pointer
644  *
645  * @ring: amdgpu ring pointer
646  *
647  * Write the wptr back to the hardware (VEGA10+).
648  */
649 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
650 {
651 	struct amdgpu_device *adev = ring->adev;
652 
653 	DRM_DEBUG("Setting write pointer\n");
654 	if (ring->use_doorbell) {
655 		u64 *wb = (u64 *)ring->wptr_cpu_addr;
656 
657 		DRM_DEBUG("Using doorbell -- "
658 				"wptr_offs == 0x%08x "
659 				"lower_32_bits(ring->wptr << 2) == 0x%08x "
660 				"upper_32_bits(ring->wptr << 2) == 0x%08x\n",
661 				ring->wptr_offs,
662 				lower_32_bits(ring->wptr << 2),
663 				upper_32_bits(ring->wptr << 2));
664 		/* XXX check if swapping is necessary on BE */
665 		WRITE_ONCE(*wb, (ring->wptr << 2));
666 		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
667 				ring->doorbell_index, ring->wptr << 2);
668 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
669 	} else {
670 		DRM_DEBUG("Not using doorbell -- "
671 				"mmSDMA%i_GFX_RB_WPTR == 0x%08x "
672 				"mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
673 				ring->me,
674 				lower_32_bits(ring->wptr << 2),
675 				ring->me,
676 				upper_32_bits(ring->wptr << 2));
677 		WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
678 			    lower_32_bits(ring->wptr << 2));
679 		WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
680 			    upper_32_bits(ring->wptr << 2));
681 	}
682 }
683 
684 /**
685  * sdma_v4_0_page_ring_get_wptr - get the current write pointer
686  *
687  * @ring: amdgpu ring pointer
688  *
689  * Get the current wptr from the hardware (VEGA10+).
690  */
691 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
692 {
693 	struct amdgpu_device *adev = ring->adev;
694 	u64 wptr;
695 
696 	if (ring->use_doorbell) {
697 		/* XXX check if swapping is necessary on BE */
698 		wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
699 	} else {
700 		wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
701 		wptr = wptr << 32;
702 		wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
703 	}
704 
705 	return wptr >> 2;
706 }
707 
708 /**
709  * sdma_v4_0_page_ring_set_wptr - commit the write pointer
710  *
711  * @ring: amdgpu ring pointer
712  *
713  * Write the wptr back to the hardware (VEGA10+).
714  */
715 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
716 {
717 	struct amdgpu_device *adev = ring->adev;
718 
719 	if (ring->use_doorbell) {
720 		u64 *wb = (u64 *)ring->wptr_cpu_addr;
721 
722 		/* XXX check if swapping is necessary on BE */
723 		WRITE_ONCE(*wb, (ring->wptr << 2));
724 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
725 	} else {
726 		uint64_t wptr = ring->wptr << 2;
727 
728 		WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
729 			    lower_32_bits(wptr));
730 		WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
731 			    upper_32_bits(wptr));
732 	}
733 }
734 
735 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
736 {
737 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
738 	int i;
739 
740 	for (i = 0; i < count; i++)
741 		if (sdma && sdma->burst_nop && (i == 0))
742 			amdgpu_ring_write(ring, ring->funcs->nop |
743 				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
744 		else
745 			amdgpu_ring_write(ring, ring->funcs->nop);
746 }
747 
748 /**
749  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
750  *
751  * @ring: amdgpu ring pointer
752  * @job: job to retrieve vmid from
753  * @ib: IB object to schedule
754  * @flags: unused
755  *
756  * Schedule an IB in the DMA ring (VEGA10).
757  */
758 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
759 				   struct amdgpu_job *job,
760 				   struct amdgpu_ib *ib,
761 				   uint32_t flags)
762 {
763 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
764 
765 	/* IB packet must end on a 8 DW boundary */
766 	sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
767 
768 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
769 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
770 	/* base must be 32 byte aligned */
771 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
772 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
773 	amdgpu_ring_write(ring, ib->length_dw);
774 	amdgpu_ring_write(ring, 0);
775 	amdgpu_ring_write(ring, 0);
776 
777 }
778 
779 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
780 				   int mem_space, int hdp,
781 				   uint32_t addr0, uint32_t addr1,
782 				   uint32_t ref, uint32_t mask,
783 				   uint32_t inv)
784 {
785 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
786 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
787 			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
788 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
789 	if (mem_space) {
790 		/* memory */
791 		amdgpu_ring_write(ring, addr0);
792 		amdgpu_ring_write(ring, addr1);
793 	} else {
794 		/* registers */
795 		amdgpu_ring_write(ring, addr0 << 2);
796 		amdgpu_ring_write(ring, addr1 << 2);
797 	}
798 	amdgpu_ring_write(ring, ref); /* reference */
799 	amdgpu_ring_write(ring, mask); /* mask */
800 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
801 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
802 }
803 
804 /**
805  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
806  *
807  * @ring: amdgpu ring pointer
808  *
809  * Emit an hdp flush packet on the requested DMA ring.
810  */
811 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
812 {
813 	struct amdgpu_device *adev = ring->adev;
814 	u32 ref_and_mask = 0;
815 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
816 
817 	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
818 
819 	sdma_v4_0_wait_reg_mem(ring, 0, 1,
820 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
821 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
822 			       ref_and_mask, ref_and_mask, 10);
823 }
824 
825 /**
826  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
827  *
828  * @ring: amdgpu ring pointer
829  * @addr: address
830  * @seq: sequence number
831  * @flags: fence related flags
832  *
833  * Add a DMA fence packet to the ring to write
834  * the fence seq number and DMA trap packet to generate
835  * an interrupt if needed (VEGA10).
836  */
837 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
838 				      unsigned flags)
839 {
840 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
841 	/* write the fence */
842 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
843 	/* zero in first two bits */
844 	BUG_ON(addr & 0x3);
845 	amdgpu_ring_write(ring, lower_32_bits(addr));
846 	amdgpu_ring_write(ring, upper_32_bits(addr));
847 	amdgpu_ring_write(ring, lower_32_bits(seq));
848 
849 	/* optionally write high bits as well */
850 	if (write64bit) {
851 		addr += 4;
852 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
853 		/* zero in first two bits */
854 		BUG_ON(addr & 0x3);
855 		amdgpu_ring_write(ring, lower_32_bits(addr));
856 		amdgpu_ring_write(ring, upper_32_bits(addr));
857 		amdgpu_ring_write(ring, upper_32_bits(seq));
858 	}
859 
860 	/* generate an interrupt */
861 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
862 	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
863 }
864 
865 
866 /**
867  * sdma_v4_0_gfx_enable - enable the gfx async dma engines
868  *
869  * @adev: amdgpu_device pointer
870  * @enable: enable SDMA RB/IB
871  * control the gfx async dma ring buffers (VEGA10).
872  */
873 static void sdma_v4_0_gfx_enable(struct amdgpu_device *adev, bool enable)
874 {
875 	u32 rb_cntl, ib_cntl;
876 	int i;
877 
878 	amdgpu_sdma_unset_buffer_funcs_helper(adev);
879 
880 	for (i = 0; i < adev->sdma.num_instances; i++) {
881 		rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
882 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, enable ? 1 : 0);
883 		WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
884 		ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
885 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, enable ? 1 : 0);
886 		WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
887 	}
888 }
889 
890 /**
891  * sdma_v4_0_rlc_stop - stop the compute async dma engines
892  *
893  * @adev: amdgpu_device pointer
894  *
895  * Stop the compute async dma queues (VEGA10).
896  */
897 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
898 {
899 	/* XXX todo */
900 }
901 
902 /**
903  * sdma_v4_0_page_stop - stop the page async dma engines
904  *
905  * @adev: amdgpu_device pointer
906  *
907  * Stop the page async dma ring buffers (VEGA10).
908  */
909 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
910 {
911 	u32 rb_cntl, ib_cntl;
912 	int i;
913 
914 	amdgpu_sdma_unset_buffer_funcs_helper(adev);
915 
916 	for (i = 0; i < adev->sdma.num_instances; i++) {
917 		rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
918 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
919 					RB_ENABLE, 0);
920 		WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
921 		ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
922 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
923 					IB_ENABLE, 0);
924 		WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
925 	}
926 }
927 
928 /**
929  * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch
930  *
931  * @adev: amdgpu_device pointer
932  * @enable: enable/disable the DMA MEs context switch.
933  *
934  * Halt or unhalt the async dma engines context switch (VEGA10).
935  */
936 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
937 {
938 	u32 f32_cntl, phase_quantum = 0;
939 	int i;
940 
941 	if (amdgpu_sdma_phase_quantum) {
942 		unsigned value = amdgpu_sdma_phase_quantum;
943 		unsigned unit = 0;
944 
945 		while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
946 				SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
947 			value = (value + 1) >> 1;
948 			unit++;
949 		}
950 		if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
951 			    SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
952 			value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
953 				 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
954 			unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
955 				SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
956 			WARN_ONCE(1,
957 			"clamping sdma_phase_quantum to %uK clock cycles\n",
958 				  value << unit);
959 		}
960 		phase_quantum =
961 			value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
962 			unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
963 	}
964 
965 	for (i = 0; i < adev->sdma.num_instances; i++) {
966 		f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
967 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
968 				AUTO_CTXSW_ENABLE, enable ? 1 : 0);
969 		if (enable && amdgpu_sdma_phase_quantum) {
970 			WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
971 			WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
972 			WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
973 		}
974 		WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
975 
976 		/*
977 		 * Enable SDMA utilization. Its only supported on
978 		 * Arcturus for the moment and firmware version 14
979 		 * and above.
980 		 */
981 		if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) &&
982 		    adev->sdma.instance[i].fw_version >= 14)
983 			WREG32_SDMA(i, mmSDMA0_PUB_DUMMY_REG2, enable);
984 		/* Extend page fault timeout to avoid interrupt storm */
985 		WREG32_SDMA(i, mmSDMA0_UTCL1_TIMEOUT, 0x00800080);
986 	}
987 
988 }
989 
990 /**
991  * sdma_v4_0_enable - stop the async dma engines
992  *
993  * @adev: amdgpu_device pointer
994  * @enable: enable/disable the DMA MEs.
995  *
996  * Halt or unhalt the async dma engines (VEGA10).
997  */
998 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
999 {
1000 	u32 f32_cntl;
1001 	int i;
1002 
1003 	if (!enable) {
1004 		sdma_v4_0_gfx_enable(adev, enable);
1005 		sdma_v4_0_rlc_stop(adev);
1006 		if (adev->sdma.has_page_queue)
1007 			sdma_v4_0_page_stop(adev);
1008 	}
1009 
1010 	for (i = 0; i < adev->sdma.num_instances; i++) {
1011 		f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1012 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
1013 		WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1014 	}
1015 }
1016 
1017 /*
1018  * sdma_v4_0_rb_cntl - get parameters for rb_cntl
1019  */
1020 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
1021 {
1022 	/* Set ring buffer size in dwords */
1023 	uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
1024 
1025 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
1026 #ifdef __BIG_ENDIAN
1027 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
1028 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1029 				RPTR_WRITEBACK_SWAP_ENABLE, 1);
1030 #endif
1031 	return rb_cntl;
1032 }
1033 
1034 /**
1035  * sdma_v4_0_gfx_resume - setup and start the async dma engines
1036  *
1037  * @adev: amdgpu_device pointer
1038  * @i: instance to resume
1039  *
1040  * Set up the gfx DMA ring buffers and enable them (VEGA10).
1041  * Returns 0 for success, error for failure.
1042  */
1043 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
1044 {
1045 	struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1046 	u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1047 	u32 doorbell;
1048 	u32 doorbell_offset;
1049 	u64 wptr_gpu_addr;
1050 
1051 	rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1052 	rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1053 	WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1054 
1055 	/* Initialize the ring buffer's read and write pointers */
1056 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
1057 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1058 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1059 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1060 
1061 	/* set the wb address whether it's enabled or not */
1062 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1063 	       upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
1064 	WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1065 	       lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
1066 
1067 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1068 				RPTR_WRITEBACK_ENABLE, 1);
1069 
1070 	WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1071 	WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1072 
1073 	ring->wptr = 0;
1074 
1075 	/* before programing wptr to a less value, need set minor_ptr_update first */
1076 	WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1077 
1078 	doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1079 	doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1080 
1081 	doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1082 				 ring->use_doorbell);
1083 	doorbell_offset = REG_SET_FIELD(doorbell_offset,
1084 					SDMA0_GFX_DOORBELL_OFFSET,
1085 					OFFSET, ring->doorbell_index);
1086 	WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1087 	WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1088 
1089 	sdma_v4_0_ring_set_wptr(ring);
1090 
1091 	/* set minor_ptr_update to 0 after wptr programed */
1092 	WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1093 
1094 	/* setup the wptr shadow polling */
1095 	wptr_gpu_addr = ring->wptr_gpu_addr;
1096 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1097 		    lower_32_bits(wptr_gpu_addr));
1098 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1099 		    upper_32_bits(wptr_gpu_addr));
1100 	wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1101 	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1102 				       SDMA0_GFX_RB_WPTR_POLL_CNTL,
1103 				       F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1104 	WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1105 
1106 	/* enable DMA RB */
1107 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1108 	WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1109 
1110 	ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1111 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1112 #ifdef __BIG_ENDIAN
1113 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1114 #endif
1115 	/* enable DMA IBs */
1116 	WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1117 
1118 	ring->sched.ready = true;
1119 }
1120 
1121 /**
1122  * sdma_v4_0_page_resume - setup and start the async dma engines
1123  *
1124  * @adev: amdgpu_device pointer
1125  * @i: instance to resume
1126  *
1127  * Set up the page DMA ring buffers and enable them (VEGA10).
1128  * Returns 0 for success, error for failure.
1129  */
1130 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1131 {
1132 	struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1133 	u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1134 	u32 doorbell;
1135 	u32 doorbell_offset;
1136 	u64 wptr_gpu_addr;
1137 
1138 	rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1139 	rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1140 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1141 
1142 	/* Initialize the ring buffer's read and write pointers */
1143 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1144 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1145 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1146 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1147 
1148 	/* set the wb address whether it's enabled or not */
1149 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1150 	       upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
1151 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1152 	       lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
1153 
1154 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1155 				RPTR_WRITEBACK_ENABLE, 1);
1156 
1157 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1158 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1159 
1160 	ring->wptr = 0;
1161 
1162 	/* before programing wptr to a less value, need set minor_ptr_update first */
1163 	WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1164 
1165 	doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1166 	doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1167 
1168 	doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1169 				 ring->use_doorbell);
1170 	doorbell_offset = REG_SET_FIELD(doorbell_offset,
1171 					SDMA0_PAGE_DOORBELL_OFFSET,
1172 					OFFSET, ring->doorbell_index);
1173 	WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1174 	WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1175 
1176 	/* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1177 	sdma_v4_0_page_ring_set_wptr(ring);
1178 
1179 	/* set minor_ptr_update to 0 after wptr programed */
1180 	WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1181 
1182 	/* setup the wptr shadow polling */
1183 	wptr_gpu_addr = ring->wptr_gpu_addr;
1184 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1185 		    lower_32_bits(wptr_gpu_addr));
1186 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1187 		    upper_32_bits(wptr_gpu_addr));
1188 	wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1189 	wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1190 				       SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1191 				       F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1192 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1193 
1194 	/* enable DMA RB */
1195 	rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1196 	WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1197 
1198 	ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1199 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1200 #ifdef __BIG_ENDIAN
1201 	ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1202 #endif
1203 	/* enable DMA IBs */
1204 	WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1205 
1206 	ring->sched.ready = true;
1207 }
1208 
1209 static void
1210 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1211 {
1212 	uint32_t def, data;
1213 
1214 	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1215 		/* enable idle interrupt */
1216 		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1217 		data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1218 
1219 		if (data != def)
1220 			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1221 	} else {
1222 		/* disable idle interrupt */
1223 		def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1224 		data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1225 		if (data != def)
1226 			WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1227 	}
1228 }
1229 
1230 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1231 {
1232 	uint32_t def, data;
1233 
1234 	/* Enable HW based PG. */
1235 	def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1236 	data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1237 	if (data != def)
1238 		WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1239 
1240 	/* enable interrupt */
1241 	def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1242 	data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1243 	if (data != def)
1244 		WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1245 
1246 	/* Configure hold time to filter in-valid power on/off request. Use default right now */
1247 	def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1248 	data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1249 	data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1250 	/* Configure switch time for hysteresis purpose. Use default right now */
1251 	data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1252 	data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1253 	if(data != def)
1254 		WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1255 }
1256 
1257 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1258 {
1259 	if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1260 		return;
1261 
1262 	switch (adev->ip_versions[SDMA0_HWIP][0]) {
1263 	case IP_VERSION(4, 1, 0):
1264         case IP_VERSION(4, 1, 1):
1265 	case IP_VERSION(4, 1, 2):
1266 		sdma_v4_1_init_power_gating(adev);
1267 		sdma_v4_1_update_power_gating(adev, true);
1268 		break;
1269 	default:
1270 		break;
1271 	}
1272 }
1273 
1274 /**
1275  * sdma_v4_0_rlc_resume - setup and start the async dma engines
1276  *
1277  * @adev: amdgpu_device pointer
1278  *
1279  * Set up the compute DMA queues and enable them (VEGA10).
1280  * Returns 0 for success, error for failure.
1281  */
1282 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1283 {
1284 	sdma_v4_0_init_pg(adev);
1285 
1286 	return 0;
1287 }
1288 
1289 /**
1290  * sdma_v4_0_load_microcode - load the sDMA ME ucode
1291  *
1292  * @adev: amdgpu_device pointer
1293  *
1294  * Loads the sDMA0/1 ucode.
1295  * Returns 0 for success, -EINVAL if the ucode is not available.
1296  */
1297 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1298 {
1299 	const struct sdma_firmware_header_v1_0 *hdr;
1300 	const __le32 *fw_data;
1301 	u32 fw_size;
1302 	int i, j;
1303 
1304 	/* halt the MEs */
1305 	sdma_v4_0_enable(adev, false);
1306 
1307 	for (i = 0; i < adev->sdma.num_instances; i++) {
1308 		if (!adev->sdma.instance[i].fw)
1309 			return -EINVAL;
1310 
1311 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1312 		amdgpu_ucode_print_sdma_hdr(&hdr->header);
1313 		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1314 
1315 		fw_data = (const __le32 *)
1316 			(adev->sdma.instance[i].fw->data +
1317 				le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1318 
1319 		WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1320 
1321 		for (j = 0; j < fw_size; j++)
1322 			WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1323 				    le32_to_cpup(fw_data++));
1324 
1325 		WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1326 			    adev->sdma.instance[i].fw_version);
1327 	}
1328 
1329 	return 0;
1330 }
1331 
1332 /**
1333  * sdma_v4_0_start - setup and start the async dma engines
1334  *
1335  * @adev: amdgpu_device pointer
1336  *
1337  * Set up the DMA engines and enable them (VEGA10).
1338  * Returns 0 for success, error for failure.
1339  */
1340 static int sdma_v4_0_start(struct amdgpu_device *adev)
1341 {
1342 	struct amdgpu_ring *ring;
1343 	int i, r = 0;
1344 
1345 	if (amdgpu_sriov_vf(adev)) {
1346 		sdma_v4_0_ctx_switch_enable(adev, false);
1347 		sdma_v4_0_enable(adev, false);
1348 	} else {
1349 
1350 		if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1351 			r = sdma_v4_0_load_microcode(adev);
1352 			if (r)
1353 				return r;
1354 		}
1355 
1356 		/* unhalt the MEs */
1357 		sdma_v4_0_enable(adev, true);
1358 		/* enable sdma ring preemption */
1359 		sdma_v4_0_ctx_switch_enable(adev, true);
1360 	}
1361 
1362 	/* start the gfx rings and rlc compute queues */
1363 	for (i = 0; i < adev->sdma.num_instances; i++) {
1364 		uint32_t temp;
1365 
1366 		WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1367 		sdma_v4_0_gfx_resume(adev, i);
1368 		if (adev->sdma.has_page_queue)
1369 			sdma_v4_0_page_resume(adev, i);
1370 
1371 		/* set utc l1 enable flag always to 1 */
1372 		temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1373 		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1374 		WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1375 
1376 		if (!amdgpu_sriov_vf(adev)) {
1377 			/* unhalt engine */
1378 			temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1379 			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1380 			WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1381 		}
1382 	}
1383 
1384 	if (amdgpu_sriov_vf(adev)) {
1385 		sdma_v4_0_ctx_switch_enable(adev, true);
1386 		sdma_v4_0_enable(adev, true);
1387 	} else {
1388 		r = sdma_v4_0_rlc_resume(adev);
1389 		if (r)
1390 			return r;
1391 	}
1392 
1393 	for (i = 0; i < adev->sdma.num_instances; i++) {
1394 		ring = &adev->sdma.instance[i].ring;
1395 
1396 		r = amdgpu_ring_test_helper(ring);
1397 		if (r)
1398 			return r;
1399 
1400 		if (adev->sdma.has_page_queue) {
1401 			struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1402 
1403 			r = amdgpu_ring_test_helper(page);
1404 			if (r)
1405 				return r;
1406 
1407 			if (adev->mman.buffer_funcs_ring == page)
1408 				amdgpu_ttm_set_buffer_funcs_status(adev, true);
1409 		}
1410 
1411 		if (adev->mman.buffer_funcs_ring == ring)
1412 			amdgpu_ttm_set_buffer_funcs_status(adev, true);
1413 	}
1414 
1415 	return r;
1416 }
1417 
1418 /**
1419  * sdma_v4_0_ring_test_ring - simple async dma engine test
1420  *
1421  * @ring: amdgpu_ring structure holding ring information
1422  *
1423  * Test the DMA engine by writing using it to write an
1424  * value to memory. (VEGA10).
1425  * Returns 0 for success, error for failure.
1426  */
1427 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1428 {
1429 	struct amdgpu_device *adev = ring->adev;
1430 	unsigned i;
1431 	unsigned index;
1432 	int r;
1433 	u32 tmp;
1434 	u64 gpu_addr;
1435 
1436 	r = amdgpu_device_wb_get(adev, &index);
1437 	if (r)
1438 		return r;
1439 
1440 	gpu_addr = adev->wb.gpu_addr + (index * 4);
1441 	tmp = 0xCAFEDEAD;
1442 	adev->wb.wb[index] = cpu_to_le32(tmp);
1443 
1444 	r = amdgpu_ring_alloc(ring, 5);
1445 	if (r)
1446 		goto error_free_wb;
1447 
1448 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1449 			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1450 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1451 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1452 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1453 	amdgpu_ring_write(ring, 0xDEADBEEF);
1454 	amdgpu_ring_commit(ring);
1455 
1456 	for (i = 0; i < adev->usec_timeout; i++) {
1457 		tmp = le32_to_cpu(adev->wb.wb[index]);
1458 		if (tmp == 0xDEADBEEF)
1459 			break;
1460 		udelay(1);
1461 	}
1462 
1463 	if (i >= adev->usec_timeout)
1464 		r = -ETIMEDOUT;
1465 
1466 error_free_wb:
1467 	amdgpu_device_wb_free(adev, index);
1468 	return r;
1469 }
1470 
1471 /**
1472  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1473  *
1474  * @ring: amdgpu_ring structure holding ring information
1475  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1476  *
1477  * Test a simple IB in the DMA ring (VEGA10).
1478  * Returns 0 on success, error on failure.
1479  */
1480 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1481 {
1482 	struct amdgpu_device *adev = ring->adev;
1483 	struct amdgpu_ib ib;
1484 	struct dma_fence *f = NULL;
1485 	unsigned index;
1486 	long r;
1487 	u32 tmp = 0;
1488 	u64 gpu_addr;
1489 
1490 	r = amdgpu_device_wb_get(adev, &index);
1491 	if (r)
1492 		return r;
1493 
1494 	gpu_addr = adev->wb.gpu_addr + (index * 4);
1495 	tmp = 0xCAFEDEAD;
1496 	adev->wb.wb[index] = cpu_to_le32(tmp);
1497 	memset(&ib, 0, sizeof(ib));
1498 	r = amdgpu_ib_get(adev, NULL, 256,
1499 					AMDGPU_IB_POOL_DIRECT, &ib);
1500 	if (r)
1501 		goto err0;
1502 
1503 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1504 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1505 	ib.ptr[1] = lower_32_bits(gpu_addr);
1506 	ib.ptr[2] = upper_32_bits(gpu_addr);
1507 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1508 	ib.ptr[4] = 0xDEADBEEF;
1509 	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1510 	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1511 	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1512 	ib.length_dw = 8;
1513 
1514 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1515 	if (r)
1516 		goto err1;
1517 
1518 	r = dma_fence_wait_timeout(f, false, timeout);
1519 	if (r == 0) {
1520 		r = -ETIMEDOUT;
1521 		goto err1;
1522 	} else if (r < 0) {
1523 		goto err1;
1524 	}
1525 	tmp = le32_to_cpu(adev->wb.wb[index]);
1526 	if (tmp == 0xDEADBEEF)
1527 		r = 0;
1528 	else
1529 		r = -EINVAL;
1530 
1531 err1:
1532 	amdgpu_ib_free(adev, &ib, NULL);
1533 	dma_fence_put(f);
1534 err0:
1535 	amdgpu_device_wb_free(adev, index);
1536 	return r;
1537 }
1538 
1539 
1540 /**
1541  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1542  *
1543  * @ib: indirect buffer to fill with commands
1544  * @pe: addr of the page entry
1545  * @src: src addr to copy from
1546  * @count: number of page entries to update
1547  *
1548  * Update PTEs by copying them from the GART using sDMA (VEGA10).
1549  */
1550 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1551 				  uint64_t pe, uint64_t src,
1552 				  unsigned count)
1553 {
1554 	unsigned bytes = count * 8;
1555 
1556 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1557 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1558 	ib->ptr[ib->length_dw++] = bytes - 1;
1559 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1560 	ib->ptr[ib->length_dw++] = lower_32_bits(src);
1561 	ib->ptr[ib->length_dw++] = upper_32_bits(src);
1562 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1563 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1564 
1565 }
1566 
1567 /**
1568  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1569  *
1570  * @ib: indirect buffer to fill with commands
1571  * @pe: addr of the page entry
1572  * @value: dst addr to write into pe
1573  * @count: number of page entries to update
1574  * @incr: increase next addr by incr bytes
1575  *
1576  * Update PTEs by writing them manually using sDMA (VEGA10).
1577  */
1578 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1579 				   uint64_t value, unsigned count,
1580 				   uint32_t incr)
1581 {
1582 	unsigned ndw = count * 2;
1583 
1584 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1585 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1586 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1587 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1588 	ib->ptr[ib->length_dw++] = ndw - 1;
1589 	for (; ndw > 0; ndw -= 2) {
1590 		ib->ptr[ib->length_dw++] = lower_32_bits(value);
1591 		ib->ptr[ib->length_dw++] = upper_32_bits(value);
1592 		value += incr;
1593 	}
1594 }
1595 
1596 /**
1597  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1598  *
1599  * @ib: indirect buffer to fill with commands
1600  * @pe: addr of the page entry
1601  * @addr: dst addr to write into pe
1602  * @count: number of page entries to update
1603  * @incr: increase next addr by incr bytes
1604  * @flags: access flags
1605  *
1606  * Update the page tables using sDMA (VEGA10).
1607  */
1608 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1609 				     uint64_t pe,
1610 				     uint64_t addr, unsigned count,
1611 				     uint32_t incr, uint64_t flags)
1612 {
1613 	/* for physically contiguous pages (vram) */
1614 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1615 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1616 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1617 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1618 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1619 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1620 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1621 	ib->ptr[ib->length_dw++] = incr; /* increment size */
1622 	ib->ptr[ib->length_dw++] = 0;
1623 	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1624 }
1625 
1626 /**
1627  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1628  *
1629  * @ring: amdgpu_ring structure holding ring information
1630  * @ib: indirect buffer to fill with padding
1631  */
1632 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1633 {
1634 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1635 	u32 pad_count;
1636 	int i;
1637 
1638 	pad_count = (-ib->length_dw) & 7;
1639 	for (i = 0; i < pad_count; i++)
1640 		if (sdma && sdma->burst_nop && (i == 0))
1641 			ib->ptr[ib->length_dw++] =
1642 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1643 				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1644 		else
1645 			ib->ptr[ib->length_dw++] =
1646 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1647 }
1648 
1649 
1650 /**
1651  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1652  *
1653  * @ring: amdgpu_ring pointer
1654  *
1655  * Make sure all previous operations are completed (CIK).
1656  */
1657 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1658 {
1659 	uint32_t seq = ring->fence_drv.sync_seq;
1660 	uint64_t addr = ring->fence_drv.gpu_addr;
1661 
1662 	/* wait for idle */
1663 	sdma_v4_0_wait_reg_mem(ring, 1, 0,
1664 			       addr & 0xfffffffc,
1665 			       upper_32_bits(addr) & 0xffffffff,
1666 			       seq, 0xffffffff, 4);
1667 }
1668 
1669 
1670 /**
1671  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1672  *
1673  * @ring: amdgpu_ring pointer
1674  * @vmid: vmid number to use
1675  * @pd_addr: address
1676  *
1677  * Update the page table base and flush the VM TLB
1678  * using sDMA (VEGA10).
1679  */
1680 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1681 					 unsigned vmid, uint64_t pd_addr)
1682 {
1683 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1684 }
1685 
1686 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1687 				     uint32_t reg, uint32_t val)
1688 {
1689 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1690 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1691 	amdgpu_ring_write(ring, reg);
1692 	amdgpu_ring_write(ring, val);
1693 }
1694 
1695 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1696 					 uint32_t val, uint32_t mask)
1697 {
1698 	sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1699 }
1700 
1701 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1702 {
1703 	uint fw_version = adev->sdma.instance[0].fw_version;
1704 
1705 	switch (adev->ip_versions[SDMA0_HWIP][0]) {
1706 	case IP_VERSION(4, 0, 0):
1707 		return fw_version >= 430;
1708 	case IP_VERSION(4, 0, 1):
1709 		/*return fw_version >= 31;*/
1710 		return false;
1711 	case IP_VERSION(4, 2, 0):
1712 		return fw_version >= 123;
1713 	default:
1714 		return false;
1715 	}
1716 }
1717 
1718 static int sdma_v4_0_early_init(void *handle)
1719 {
1720 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1721 	int r;
1722 
1723 	r = sdma_v4_0_init_microcode(adev);
1724 	if (r) {
1725 		DRM_ERROR("Failed to load sdma firmware!\n");
1726 		return r;
1727 	}
1728 
1729 	/* TODO: Page queue breaks driver reload under SRIOV */
1730 	if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) &&
1731 	    amdgpu_sriov_vf((adev)))
1732 		adev->sdma.has_page_queue = false;
1733 	else if (sdma_v4_0_fw_support_paging_queue(adev))
1734 		adev->sdma.has_page_queue = true;
1735 
1736 	sdma_v4_0_set_ring_funcs(adev);
1737 	sdma_v4_0_set_buffer_funcs(adev);
1738 	sdma_v4_0_set_vm_pte_funcs(adev);
1739 	sdma_v4_0_set_irq_funcs(adev);
1740 	sdma_v4_0_set_ras_funcs(adev);
1741 
1742 	return 0;
1743 }
1744 
1745 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1746 		void *err_data,
1747 		struct amdgpu_iv_entry *entry);
1748 
1749 static int sdma_v4_0_late_init(void *handle)
1750 {
1751 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1752 
1753 	sdma_v4_0_setup_ulv(adev);
1754 
1755 	if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1756 		if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops &&
1757 		    adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count)
1758 			adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev);
1759 	}
1760 
1761 	return 0;
1762 }
1763 
1764 static int sdma_v4_0_sw_init(void *handle)
1765 {
1766 	struct amdgpu_ring *ring;
1767 	int r, i;
1768 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1769 
1770 	/* SDMA trap event */
1771 	for (i = 0; i < adev->sdma.num_instances; i++) {
1772 		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1773 				      SDMA0_4_0__SRCID__SDMA_TRAP,
1774 				      &adev->sdma.trap_irq);
1775 		if (r)
1776 			return r;
1777 	}
1778 
1779 	/* SDMA SRAM ECC event */
1780 	for (i = 0; i < adev->sdma.num_instances; i++) {
1781 		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1782 				      SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1783 				      &adev->sdma.ecc_irq);
1784 		if (r)
1785 			return r;
1786 	}
1787 
1788 	/* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1789 	for (i = 0; i < adev->sdma.num_instances; i++) {
1790 		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1791 				      SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1792 				      &adev->sdma.vm_hole_irq);
1793 		if (r)
1794 			return r;
1795 
1796 		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1797 				      SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1798 				      &adev->sdma.doorbell_invalid_irq);
1799 		if (r)
1800 			return r;
1801 
1802 		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1803 				      SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1804 				      &adev->sdma.pool_timeout_irq);
1805 		if (r)
1806 			return r;
1807 
1808 		r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1809 				      SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1810 				      &adev->sdma.srbm_write_irq);
1811 		if (r)
1812 			return r;
1813 	}
1814 
1815 	for (i = 0; i < adev->sdma.num_instances; i++) {
1816 		ring = &adev->sdma.instance[i].ring;
1817 		ring->ring_obj = NULL;
1818 		ring->use_doorbell = true;
1819 
1820 		DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1821 				ring->use_doorbell?"true":"false");
1822 
1823 		/* doorbell size is 2 dwords, get DWORD offset */
1824 		ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1825 
1826 		/*
1827 		 * On Arcturus, SDMA instance 5~7 has a different vmhub
1828 		 * type(AMDGPU_MMHUB_1).
1829 		 */
1830 		if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
1831 			ring->vm_hub = AMDGPU_MMHUB_1;
1832 		else
1833 			ring->vm_hub = AMDGPU_MMHUB_0;
1834 
1835 		sprintf(ring->name, "sdma%d", i);
1836 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1837 				     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1838 				     AMDGPU_RING_PRIO_DEFAULT, NULL);
1839 		if (r)
1840 			return r;
1841 
1842 		if (adev->sdma.has_page_queue) {
1843 			ring = &adev->sdma.instance[i].page;
1844 			ring->ring_obj = NULL;
1845 			ring->use_doorbell = true;
1846 
1847 			/* paging queue use same doorbell index/routing as gfx queue
1848 			 * with 0x400 (4096 dwords) offset on second doorbell page
1849 			 */
1850 			ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1851 			ring->doorbell_index += 0x400;
1852 
1853 			if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5)
1854 				ring->vm_hub = AMDGPU_MMHUB_1;
1855 			else
1856 				ring->vm_hub = AMDGPU_MMHUB_0;
1857 
1858 			sprintf(ring->name, "page%d", i);
1859 			r = amdgpu_ring_init(adev, ring, 1024,
1860 					     &adev->sdma.trap_irq,
1861 					     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1862 					     AMDGPU_RING_PRIO_DEFAULT, NULL);
1863 			if (r)
1864 				return r;
1865 		}
1866 	}
1867 
1868 	if (amdgpu_sdma_ras_sw_init(adev)) {
1869 		dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
1870 		return -EINVAL;
1871 	}
1872 
1873 	return r;
1874 }
1875 
1876 static int sdma_v4_0_sw_fini(void *handle)
1877 {
1878 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1879 	int i;
1880 
1881 	for (i = 0; i < adev->sdma.num_instances; i++) {
1882 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1883 		if (adev->sdma.has_page_queue)
1884 			amdgpu_ring_fini(&adev->sdma.instance[i].page);
1885 	}
1886 
1887 	if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) ||
1888             adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0))
1889 		amdgpu_sdma_destroy_inst_ctx(adev, true);
1890 	else
1891 		amdgpu_sdma_destroy_inst_ctx(adev, false);
1892 
1893 	return 0;
1894 }
1895 
1896 static int sdma_v4_0_hw_init(void *handle)
1897 {
1898 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1899 
1900 	if (adev->flags & AMD_IS_APU)
1901 		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1902 
1903 	if (!amdgpu_sriov_vf(adev))
1904 		sdma_v4_0_init_golden_registers(adev);
1905 
1906 	return sdma_v4_0_start(adev);
1907 }
1908 
1909 static int sdma_v4_0_hw_fini(void *handle)
1910 {
1911 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1912 	int i;
1913 
1914 	if (amdgpu_sriov_vf(adev)) {
1915 		/* disable the scheduler for SDMA */
1916 		amdgpu_sdma_unset_buffer_funcs_helper(adev);
1917 		return 0;
1918 	}
1919 
1920 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1921 		for (i = 0; i < adev->sdma.num_instances; i++) {
1922 			amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1923 				       AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1924 		}
1925 	}
1926 
1927 	sdma_v4_0_ctx_switch_enable(adev, false);
1928 	sdma_v4_0_enable(adev, false);
1929 
1930 	if (adev->flags & AMD_IS_APU)
1931 		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1932 
1933 	return 0;
1934 }
1935 
1936 static int sdma_v4_0_suspend(void *handle)
1937 {
1938 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1939 
1940 	/* SMU saves SDMA state for us */
1941 	if (adev->in_s0ix) {
1942 		sdma_v4_0_gfx_enable(adev, false);
1943 		return 0;
1944 	}
1945 
1946 	return sdma_v4_0_hw_fini(adev);
1947 }
1948 
1949 static int sdma_v4_0_resume(void *handle)
1950 {
1951 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1952 
1953 	/* SMU restores SDMA state for us */
1954 	if (adev->in_s0ix) {
1955 		sdma_v4_0_enable(adev, true);
1956 		sdma_v4_0_gfx_enable(adev, true);
1957 		amdgpu_ttm_set_buffer_funcs_status(adev, true);
1958 		return 0;
1959 	}
1960 
1961 	return sdma_v4_0_hw_init(adev);
1962 }
1963 
1964 static bool sdma_v4_0_is_idle(void *handle)
1965 {
1966 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1967 	u32 i;
1968 
1969 	for (i = 0; i < adev->sdma.num_instances; i++) {
1970 		u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
1971 
1972 		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1973 			return false;
1974 	}
1975 
1976 	return true;
1977 }
1978 
1979 static int sdma_v4_0_wait_for_idle(void *handle)
1980 {
1981 	unsigned i, j;
1982 	u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1983 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1984 
1985 	for (i = 0; i < adev->usec_timeout; i++) {
1986 		for (j = 0; j < adev->sdma.num_instances; j++) {
1987 			sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
1988 			if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
1989 				break;
1990 		}
1991 		if (j == adev->sdma.num_instances)
1992 			return 0;
1993 		udelay(1);
1994 	}
1995 	return -ETIMEDOUT;
1996 }
1997 
1998 static int sdma_v4_0_soft_reset(void *handle)
1999 {
2000 	/* todo */
2001 
2002 	return 0;
2003 }
2004 
2005 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
2006 					struct amdgpu_irq_src *source,
2007 					unsigned type,
2008 					enum amdgpu_interrupt_state state)
2009 {
2010 	u32 sdma_cntl;
2011 
2012 	sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
2013 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
2014 		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2015 	WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
2016 
2017 	return 0;
2018 }
2019 
2020 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
2021 				      struct amdgpu_irq_src *source,
2022 				      struct amdgpu_iv_entry *entry)
2023 {
2024 	uint32_t instance;
2025 
2026 	DRM_DEBUG("IH: SDMA trap\n");
2027 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2028 	switch (entry->ring_id) {
2029 	case 0:
2030 		amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2031 		break;
2032 	case 1:
2033 		if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 0))
2034 			amdgpu_fence_process(&adev->sdma.instance[instance].page);
2035 		break;
2036 	case 2:
2037 		/* XXX compute */
2038 		break;
2039 	case 3:
2040 		if (adev->ip_versions[SDMA0_HWIP][0] != IP_VERSION(4, 2, 0))
2041 			amdgpu_fence_process(&adev->sdma.instance[instance].page);
2042 		break;
2043 	}
2044 	return 0;
2045 }
2046 
2047 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
2048 		void *err_data,
2049 		struct amdgpu_iv_entry *entry)
2050 {
2051 	int instance;
2052 
2053 	/* When “Full RAS” is enabled, the per-IP interrupt sources should
2054 	 * be disabled and the driver should only look for the aggregated
2055 	 * interrupt via sync flood
2056 	 */
2057 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
2058 		goto out;
2059 
2060 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2061 	if (instance < 0)
2062 		goto out;
2063 
2064 	amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
2065 
2066 out:
2067 	return AMDGPU_RAS_SUCCESS;
2068 }
2069 
2070 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2071 					      struct amdgpu_irq_src *source,
2072 					      struct amdgpu_iv_entry *entry)
2073 {
2074 	int instance;
2075 
2076 	DRM_ERROR("Illegal instruction in SDMA command stream\n");
2077 
2078 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2079 	if (instance < 0)
2080 		return 0;
2081 
2082 	switch (entry->ring_id) {
2083 	case 0:
2084 		drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2085 		break;
2086 	}
2087 	return 0;
2088 }
2089 
2090 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2091 					struct amdgpu_irq_src *source,
2092 					unsigned type,
2093 					enum amdgpu_interrupt_state state)
2094 {
2095 	u32 sdma_edc_config;
2096 
2097 	sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2098 	sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2099 		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2100 	WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2101 
2102 	return 0;
2103 }
2104 
2105 static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev,
2106 					      struct amdgpu_iv_entry *entry)
2107 {
2108 	int instance;
2109 	struct amdgpu_task_info task_info;
2110 	u64 addr;
2111 
2112 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2113 	if (instance < 0 || instance >= adev->sdma.num_instances) {
2114 		dev_err(adev->dev, "sdma instance invalid %d\n", instance);
2115 		return -EINVAL;
2116 	}
2117 
2118 	addr = (u64)entry->src_data[0] << 12;
2119 	addr |= ((u64)entry->src_data[1] & 0xf) << 44;
2120 
2121 	memset(&task_info, 0, sizeof(struct amdgpu_task_info));
2122 	amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
2123 
2124 	dev_dbg_ratelimited(adev->dev,
2125 		   "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
2126 		   "pasid:%u, for process %s pid %d thread %s pid %d\n",
2127 		   instance, addr, entry->src_id, entry->ring_id, entry->vmid,
2128 		   entry->pasid, task_info.process_name, task_info.tgid,
2129 		   task_info.task_name, task_info.pid);
2130 	return 0;
2131 }
2132 
2133 static int sdma_v4_0_process_vm_hole_irq(struct amdgpu_device *adev,
2134 					      struct amdgpu_irq_src *source,
2135 					      struct amdgpu_iv_entry *entry)
2136 {
2137 	dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
2138 	sdma_v4_0_print_iv_entry(adev, entry);
2139 	return 0;
2140 }
2141 
2142 static int sdma_v4_0_process_doorbell_invalid_irq(struct amdgpu_device *adev,
2143 					      struct amdgpu_irq_src *source,
2144 					      struct amdgpu_iv_entry *entry)
2145 {
2146 	dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
2147 	sdma_v4_0_print_iv_entry(adev, entry);
2148 	return 0;
2149 }
2150 
2151 static int sdma_v4_0_process_pool_timeout_irq(struct amdgpu_device *adev,
2152 					      struct amdgpu_irq_src *source,
2153 					      struct amdgpu_iv_entry *entry)
2154 {
2155 	dev_dbg_ratelimited(adev->dev,
2156 		"Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
2157 	sdma_v4_0_print_iv_entry(adev, entry);
2158 	return 0;
2159 }
2160 
2161 static int sdma_v4_0_process_srbm_write_irq(struct amdgpu_device *adev,
2162 					      struct amdgpu_irq_src *source,
2163 					      struct amdgpu_iv_entry *entry)
2164 {
2165 	dev_dbg_ratelimited(adev->dev,
2166 		"SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
2167 	sdma_v4_0_print_iv_entry(adev, entry);
2168 	return 0;
2169 }
2170 
2171 static void sdma_v4_0_update_medium_grain_clock_gating(
2172 		struct amdgpu_device *adev,
2173 		bool enable)
2174 {
2175 	uint32_t data, def;
2176 	int i;
2177 
2178 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2179 		for (i = 0; i < adev->sdma.num_instances; i++) {
2180 			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2181 			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2182 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2183 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2184 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2185 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2186 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2187 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2188 				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2189 			if (def != data)
2190 				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2191 		}
2192 	} else {
2193 		for (i = 0; i < adev->sdma.num_instances; i++) {
2194 			def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2195 			data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2196 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2197 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2198 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2199 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2200 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2201 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2202 				 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2203 			if (def != data)
2204 				WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2205 		}
2206 	}
2207 }
2208 
2209 
2210 static void sdma_v4_0_update_medium_grain_light_sleep(
2211 		struct amdgpu_device *adev,
2212 		bool enable)
2213 {
2214 	uint32_t data, def;
2215 	int i;
2216 
2217 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2218 		for (i = 0; i < adev->sdma.num_instances; i++) {
2219 			/* 1-not override: enable sdma mem light sleep */
2220 			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2221 			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2222 			if (def != data)
2223 				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2224 		}
2225 	} else {
2226 		for (i = 0; i < adev->sdma.num_instances; i++) {
2227 		/* 0-override:disable sdma mem light sleep */
2228 			def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2229 			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2230 			if (def != data)
2231 				WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2232 		}
2233 	}
2234 }
2235 
2236 static int sdma_v4_0_set_clockgating_state(void *handle,
2237 					  enum amd_clockgating_state state)
2238 {
2239 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2240 
2241 	if (amdgpu_sriov_vf(adev))
2242 		return 0;
2243 
2244 	sdma_v4_0_update_medium_grain_clock_gating(adev,
2245 			state == AMD_CG_STATE_GATE);
2246 	sdma_v4_0_update_medium_grain_light_sleep(adev,
2247 			state == AMD_CG_STATE_GATE);
2248 	return 0;
2249 }
2250 
2251 static int sdma_v4_0_set_powergating_state(void *handle,
2252 					  enum amd_powergating_state state)
2253 {
2254 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2255 
2256 	switch (adev->ip_versions[SDMA0_HWIP][0]) {
2257 	case IP_VERSION(4, 1, 0):
2258 	case IP_VERSION(4, 1, 1):
2259 	case IP_VERSION(4, 1, 2):
2260 		sdma_v4_1_update_power_gating(adev,
2261 				state == AMD_PG_STATE_GATE);
2262 		break;
2263 	default:
2264 		break;
2265 	}
2266 
2267 	return 0;
2268 }
2269 
2270 static void sdma_v4_0_get_clockgating_state(void *handle, u64 *flags)
2271 {
2272 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2273 	int data;
2274 
2275 	if (amdgpu_sriov_vf(adev))
2276 		*flags = 0;
2277 
2278 	/* AMD_CG_SUPPORT_SDMA_MGCG */
2279 	data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2280 	if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2281 		*flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2282 
2283 	/* AMD_CG_SUPPORT_SDMA_LS */
2284 	data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2285 	if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2286 		*flags |= AMD_CG_SUPPORT_SDMA_LS;
2287 }
2288 
2289 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2290 	.name = "sdma_v4_0",
2291 	.early_init = sdma_v4_0_early_init,
2292 	.late_init = sdma_v4_0_late_init,
2293 	.sw_init = sdma_v4_0_sw_init,
2294 	.sw_fini = sdma_v4_0_sw_fini,
2295 	.hw_init = sdma_v4_0_hw_init,
2296 	.hw_fini = sdma_v4_0_hw_fini,
2297 	.suspend = sdma_v4_0_suspend,
2298 	.resume = sdma_v4_0_resume,
2299 	.is_idle = sdma_v4_0_is_idle,
2300 	.wait_for_idle = sdma_v4_0_wait_for_idle,
2301 	.soft_reset = sdma_v4_0_soft_reset,
2302 	.set_clockgating_state = sdma_v4_0_set_clockgating_state,
2303 	.set_powergating_state = sdma_v4_0_set_powergating_state,
2304 	.get_clockgating_state = sdma_v4_0_get_clockgating_state,
2305 };
2306 
2307 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2308 	.type = AMDGPU_RING_TYPE_SDMA,
2309 	.align_mask = 0xf,
2310 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2311 	.support_64bit_ptrs = true,
2312 	.secure_submission_supported = true,
2313 	.get_rptr = sdma_v4_0_ring_get_rptr,
2314 	.get_wptr = sdma_v4_0_ring_get_wptr,
2315 	.set_wptr = sdma_v4_0_ring_set_wptr,
2316 	.emit_frame_size =
2317 		6 + /* sdma_v4_0_ring_emit_hdp_flush */
2318 		3 + /* hdp invalidate */
2319 		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2320 		/* sdma_v4_0_ring_emit_vm_flush */
2321 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2322 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2323 		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2324 	.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2325 	.emit_ib = sdma_v4_0_ring_emit_ib,
2326 	.emit_fence = sdma_v4_0_ring_emit_fence,
2327 	.emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2328 	.emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2329 	.emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2330 	.test_ring = sdma_v4_0_ring_test_ring,
2331 	.test_ib = sdma_v4_0_ring_test_ib,
2332 	.insert_nop = sdma_v4_0_ring_insert_nop,
2333 	.pad_ib = sdma_v4_0_ring_pad_ib,
2334 	.emit_wreg = sdma_v4_0_ring_emit_wreg,
2335 	.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2336 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2337 };
2338 
2339 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2340 	.type = AMDGPU_RING_TYPE_SDMA,
2341 	.align_mask = 0xf,
2342 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2343 	.support_64bit_ptrs = true,
2344 	.secure_submission_supported = true,
2345 	.get_rptr = sdma_v4_0_ring_get_rptr,
2346 	.get_wptr = sdma_v4_0_page_ring_get_wptr,
2347 	.set_wptr = sdma_v4_0_page_ring_set_wptr,
2348 	.emit_frame_size =
2349 		6 + /* sdma_v4_0_ring_emit_hdp_flush */
2350 		3 + /* hdp invalidate */
2351 		6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2352 		/* sdma_v4_0_ring_emit_vm_flush */
2353 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2354 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2355 		10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2356 	.emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2357 	.emit_ib = sdma_v4_0_ring_emit_ib,
2358 	.emit_fence = sdma_v4_0_ring_emit_fence,
2359 	.emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2360 	.emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2361 	.emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2362 	.test_ring = sdma_v4_0_ring_test_ring,
2363 	.test_ib = sdma_v4_0_ring_test_ib,
2364 	.insert_nop = sdma_v4_0_ring_insert_nop,
2365 	.pad_ib = sdma_v4_0_ring_pad_ib,
2366 	.emit_wreg = sdma_v4_0_ring_emit_wreg,
2367 	.emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2368 	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2369 };
2370 
2371 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2372 {
2373 	int i;
2374 
2375 	for (i = 0; i < adev->sdma.num_instances; i++) {
2376 		adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
2377 		adev->sdma.instance[i].ring.me = i;
2378 		if (adev->sdma.has_page_queue) {
2379 			adev->sdma.instance[i].page.funcs =
2380 					&sdma_v4_0_page_ring_funcs;
2381 			adev->sdma.instance[i].page.me = i;
2382 		}
2383 	}
2384 }
2385 
2386 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2387 	.set = sdma_v4_0_set_trap_irq_state,
2388 	.process = sdma_v4_0_process_trap_irq,
2389 };
2390 
2391 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2392 	.process = sdma_v4_0_process_illegal_inst_irq,
2393 };
2394 
2395 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2396 	.set = sdma_v4_0_set_ecc_irq_state,
2397 	.process = amdgpu_sdma_process_ecc_irq,
2398 };
2399 
2400 static const struct amdgpu_irq_src_funcs sdma_v4_0_vm_hole_irq_funcs = {
2401 	.process = sdma_v4_0_process_vm_hole_irq,
2402 };
2403 
2404 static const struct amdgpu_irq_src_funcs sdma_v4_0_doorbell_invalid_irq_funcs = {
2405 	.process = sdma_v4_0_process_doorbell_invalid_irq,
2406 };
2407 
2408 static const struct amdgpu_irq_src_funcs sdma_v4_0_pool_timeout_irq_funcs = {
2409 	.process = sdma_v4_0_process_pool_timeout_irq,
2410 };
2411 
2412 static const struct amdgpu_irq_src_funcs sdma_v4_0_srbm_write_irq_funcs = {
2413 	.process = sdma_v4_0_process_srbm_write_irq,
2414 };
2415 
2416 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2417 {
2418 	adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
2419 	adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
2420 	/*For Arcturus and Aldebaran, add another 4 irq handler*/
2421 	switch (adev->sdma.num_instances) {
2422 	case 5:
2423 	case 8:
2424 		adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
2425 		adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
2426 		adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
2427 		adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
2428 		break;
2429 	default:
2430 		break;
2431 	}
2432 	adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2433 	adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2434 	adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2435 	adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs;
2436 	adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs;
2437 	adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs;
2438 	adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs;
2439 }
2440 
2441 /**
2442  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2443  *
2444  * @ib: indirect buffer to copy to
2445  * @src_offset: src GPU address
2446  * @dst_offset: dst GPU address
2447  * @byte_count: number of bytes to xfer
2448  * @tmz: if a secure copy should be used
2449  *
2450  * Copy GPU buffers using the DMA engine (VEGA10/12).
2451  * Used by the amdgpu ttm implementation to move pages if
2452  * registered as the asic copy callback.
2453  */
2454 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2455 				       uint64_t src_offset,
2456 				       uint64_t dst_offset,
2457 				       uint32_t byte_count,
2458 				       bool tmz)
2459 {
2460 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2461 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
2462 		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
2463 	ib->ptr[ib->length_dw++] = byte_count - 1;
2464 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2465 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2466 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2467 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2468 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2469 }
2470 
2471 /**
2472  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2473  *
2474  * @ib: indirect buffer to copy to
2475  * @src_data: value to write to buffer
2476  * @dst_offset: dst GPU address
2477  * @byte_count: number of bytes to xfer
2478  *
2479  * Fill GPU buffers using the DMA engine (VEGA10/12).
2480  */
2481 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2482 				       uint32_t src_data,
2483 				       uint64_t dst_offset,
2484 				       uint32_t byte_count)
2485 {
2486 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2487 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2488 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2489 	ib->ptr[ib->length_dw++] = src_data;
2490 	ib->ptr[ib->length_dw++] = byte_count - 1;
2491 }
2492 
2493 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2494 	.copy_max_bytes = 0x400000,
2495 	.copy_num_dw = 7,
2496 	.emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2497 
2498 	.fill_max_bytes = 0x400000,
2499 	.fill_num_dw = 5,
2500 	.emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2501 };
2502 
2503 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2504 {
2505 	adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2506 	if (adev->sdma.has_page_queue)
2507 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2508 	else
2509 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2510 }
2511 
2512 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2513 	.copy_pte_num_dw = 7,
2514 	.copy_pte = sdma_v4_0_vm_copy_pte,
2515 
2516 	.write_pte = sdma_v4_0_vm_write_pte,
2517 	.set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2518 };
2519 
2520 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2521 {
2522 	struct drm_gpu_scheduler *sched;
2523 	unsigned i;
2524 
2525 	adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2526 	for (i = 0; i < adev->sdma.num_instances; i++) {
2527 		if (adev->sdma.has_page_queue)
2528 			sched = &adev->sdma.instance[i].page.sched;
2529 		else
2530 			sched = &adev->sdma.instance[i].ring.sched;
2531 		adev->vm_manager.vm_pte_scheds[i] = sched;
2532 	}
2533 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2534 }
2535 
2536 static void sdma_v4_0_get_ras_error_count(uint32_t value,
2537 					uint32_t instance,
2538 					uint32_t *sec_count)
2539 {
2540 	uint32_t i;
2541 	uint32_t sec_cnt;
2542 
2543 	/* double bits error (multiple bits) error detection is not supported */
2544 	for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {
2545 		/* the SDMA_EDC_COUNTER register in each sdma instance
2546 		 * shares the same sed shift_mask
2547 		 * */
2548 		sec_cnt = (value &
2549 			sdma_v4_0_ras_fields[i].sec_count_mask) >>
2550 			sdma_v4_0_ras_fields[i].sec_count_shift;
2551 		if (sec_cnt) {
2552 			DRM_INFO("Detected %s in SDMA%d, SED %d\n",
2553 				sdma_v4_0_ras_fields[i].name,
2554 				instance, sec_cnt);
2555 			*sec_count += sec_cnt;
2556 		}
2557 	}
2558 }
2559 
2560 static int sdma_v4_0_query_ras_error_count_by_instance(struct amdgpu_device *adev,
2561 			uint32_t instance, void *ras_error_status)
2562 {
2563 	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
2564 	uint32_t sec_count = 0;
2565 	uint32_t reg_value = 0;
2566 
2567 	reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2568 	/* double bit error is not supported */
2569 	if (reg_value)
2570 		sdma_v4_0_get_ras_error_count(reg_value,
2571 				instance, &sec_count);
2572 	/* err_data->ce_count should be initialized to 0
2573 	 * before calling into this function */
2574 	err_data->ce_count += sec_count;
2575 	/* double bit error is not supported
2576 	 * set ue count to 0 */
2577 	err_data->ue_count = 0;
2578 
2579 	return 0;
2580 };
2581 
2582 static void sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev,  void *ras_error_status)
2583 {
2584 	int i = 0;
2585 
2586 	for (i = 0; i < adev->sdma.num_instances; i++) {
2587 		if (sdma_v4_0_query_ras_error_count_by_instance(adev, i, ras_error_status)) {
2588 			dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i);
2589 			return;
2590 		}
2591 	}
2592 }
2593 
2594 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
2595 {
2596 	int i;
2597 
2598 	/* read back edc counter registers to clear the counters */
2599 	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2600 		for (i = 0; i < adev->sdma.num_instances; i++)
2601 			RREG32_SDMA(i, mmSDMA0_EDC_COUNTER);
2602 	}
2603 }
2604 
2605 const struct amdgpu_ras_block_hw_ops sdma_v4_0_ras_hw_ops = {
2606 	.query_ras_error_count = sdma_v4_0_query_ras_error_count,
2607 	.reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
2608 };
2609 
2610 static struct amdgpu_sdma_ras sdma_v4_0_ras = {
2611 	.ras_block = {
2612 		.hw_ops = &sdma_v4_0_ras_hw_ops,
2613 		.ras_cb = sdma_v4_0_process_ras_data_cb,
2614 	},
2615 };
2616 
2617 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2618 {
2619 	switch (adev->ip_versions[SDMA0_HWIP][0]) {
2620 	case IP_VERSION(4, 2, 0):
2621 	case IP_VERSION(4, 2, 2):
2622 		adev->sdma.ras = &sdma_v4_0_ras;
2623 		break;
2624 	case IP_VERSION(4, 4, 0):
2625 		adev->sdma.ras = &sdma_v4_4_ras;
2626 		break;
2627 	default:
2628 		break;
2629 	}
2630 
2631 }
2632 
2633 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2634 	.type = AMD_IP_BLOCK_TYPE_SDMA,
2635 	.major = 4,
2636 	.minor = 0,
2637 	.rev = 0,
2638 	.funcs = &sdma_v4_0_ip_funcs,
2639 };
2640